Abstract: A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate insulation film, a gate electrode and the like. In the storage-type SiC-MISFET, a partially heavily doped layer is formed by partially implanting ions of a p-type impurity into an upper surface portion of the n-type drift layer and containing an impurity of the same conductive type as that of the impurity implanted into the well region at a higher concentration than that in the well region.

Abstract: A method of disordering a quantum well heterostructure, including the step of irradiating the heterostructure with a particle beam, wherein the energy of the beam is such that the beam creates a substantially constant distribution of defects within the heterostructure. The irradiating particles can be ions or electrons, and the energy is preferably such that the irradiating particles pass through the heterostructure. Light ions such as hydrogen ions are preferred because they are readily available and produce substantially uniform distributions of point defects at relatively low energies. The method can be used to tune the wavelength range of an optoelectronic device including such a heterostructure, such as a photodetector.

Abstract: A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained layer. During the annealing, interstitial dislocation loops are formed as uniformly tributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

Abstract: The present invention provides a method for manufacturing a semiconductor substrate, comprising the step of: forming a first buffer Si layer on a substrate having a silicon surface; epitaxially growing, in sequence, a first strained SiGe layer and a first Si layer above the first buffer Si layer; implanting ions into the resulting substrate followed by annealing so as to relax the lattice of the first strained SiGe layer and to thereby providing tensile strain in the first Si layer and so that tensile strain is provided in the first Si layer; and epitaxially growing, in sequence, a second buffer Si layer and a second SiGe layer above the resulting substrate; and forming a second Si layer having tensile strain on the second SiGe layer.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: The mobility enhancement of a strained silicon layer is augmented through incorporation of carbon into a strained silicon lattice to which strain is also imparted by an underlying silicon germanium layer. The presence of the relatively small carbon atoms effectively increases the spacing within the strained silicon lattice and thus imparts additional strain. This enhancement may be implemented for any MOSFET device including silicon on insulator MOSFETs, and is preferably selectively implemented for the PMOS components of CMOS devices to achieve approximately equal carrier mobility for the PMOS and NMOS devices.

Abstract: A method for transforming an amorphous silicon layer into a polysilicon layer is disclosed. The method includes following steps: providing an amorphous silicon substrate, doping the amorphous silicon substrate with an inert gas atom, and increasing the temperature of the surface of the amorphous silicon substrate by heat treatment or thermal process.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: A method is provided for printing electronic and opto-electronic circuits. The method comprises: (a) providing a substrate; (b) providing a film-forming precursor species; (c) forming a substantially uniform and continuous film of the film-forming precursor species on at least one side of the substrate, the film having a first electrical conductivity; and (d) altering portions of the film with at least one conductivity-altering species to form regions having a second electrical conductivity that is different than the first electrical conductivity, the regions thereby providing circuit elements. The method employs very simple and continuous processes, which make the time to produce a batch of circuits very short and leads to very inexpensive products, such as electronic memories (write once or rewriteable), electronically addressable displays, and generally any circuit for which organic electronics or opto-electronics are acceptable.

Abstract: A Schottky barrier diode and process of making is disclosed. The process forms a metal contact pattern in masked areas on a silicon carbide wafer. A preferred embodiment includes on insulating layer that is etched in the windows of the mask. An inert edge termination is implanted into the wafer beneath the oxide layer and adjacent the metal contacts to improve reliability. A further oxide layer may be added to improve surface resistance to physical damage.

Abstract: A p-GaN layer 5 comprising materials such as a Group III nitride compound semiconductor is formed on a sapphire substrate 1 through MOVPE treatment, and a first metal layer 6 made of Co/Au is formed thereon. Then in a planar electron beam irradiation apparatus using plasma, electron beams are irradiated to the p-GaN layer 5 through the first metal layer 6. Accordingly, the first metal layer 6 prevents the surface of the p-GaN layer 5 from being damaged and resistivity of the p-GaN layer 5 can be lowered. Next, a second metal (Ni) layer 10 is formed on the first metal layer 6. And the first metal layer 6 is etched through the second metal layer 10 by using fluoric nitric acid. As a result, the first metal layer is almost completely removed. Then a light-transmitting p-electrode 7 made of Co/Au is formed thereon. As a result, a p-type semiconductor having decreased contact resistance and lower driving voltage can be obtained and optical transmittance factor of the p-type semiconductor improves.

Abstract: A method for forming an epitaxial layer involves depositing a buffer layer on a substrate by a first deposition process, followed by deposition of an epitaxial layer by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer formed on a substrate by MOCVD, and an epitaxial layer formed on the buffer layer, the epitaxial layer deposited by hydride vapor-phase deposition.

Abstract: A highly reliable semiconductor laser device having a low operating voltage is obtained by increasing adhesive force of the overall electrode layer to a nitride-based semiconductor layer without deteriorating a low contact property. This nitride-based semiconductor laser device comprises a nitride-based semiconductor layer formed on an active layer and an electrode layer formed on the nitride-based semiconductor layer, while the electrode layer includes a first electrode layer containing a material having strong adhesive force to the nitride-based semiconductor layer and a second electrode layer, formed on the first electrode layer, having weaker adhesive force to the nitride-based semiconductor layer than the first electrode layer for reducing contact resistance of the electrode layer with respect to the nitride-based semiconductor layer.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

Abstract: The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: The invention, called hypercontacting, achieves a very high level of activated doping at an exposed surface region of a compound semiconductor. This enables production of low resistance ohmic contacts by creating a heavily doped region near the contact. Such region lowers the contact's tunneling barrier by decreasing the extent of the depletion region at the contact, thereby reducing resistance.

Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth and a fourth depth so as to counteract a change in band gap in the base between the first depth and the second depth. For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth and fourth depth so as to counteract the change in band gap at approximately the second depth.

Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm−3 at Al mole fractions up to 65% are obtained.

Abstract: A method for forming a p-type semiconductor film comprises the steps of: providing on a substrate a group II-VI compound semiconductor film which is doped with a p-type impurity and comprises either MgXZn1−XO (0≦X≦1) or CdXZn1−XO (0≦X≦1) and activating the p-type impurity by annealing the doped semiconductor film.

Abstract: A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A method for doping Gallium Nitride (GaN) substrates is provided wherein Gallium (Ga) is transmuted to Germanium (Ge) by applying thermal neutron irradiation to a GaN substrate material or wafer. The Ge is introduced as an impurity in GaN and acts as a donor. The concentration of Ge introduced is controlled by the thermal neutron flux. When the thermal neutron irradiation is applied to a GaN wafer the fast neutrons are transmuted together with the former and cause defects such as the collapse of the crystallization. The GaN wafer is thermally treated or processed at a fixed temperature to eliminate such defects.

Abstract: A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.

Abstract: In this bypass-function added solar cell, a plurality of island-like p+ regions, which is third regions, are formed at a boundary between a p-type region and an n-type region layer constituting a substrate so that the p+ regions project into the region and the region and are separated away from the surface of the substrate. Therefore, in this solar cell, unlike prior art counterparts, the insulating film for isolating the p+ regions and the n electrodes constituting the np+ diode from one another is no longer necessary, thus allowing a reduction in manufacturing cost. As a result, a bypass-function added solar cell with a bypass-diode function added thereto can be provided with low cost and by simple process.

Abstract: A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal, mass outer surfaces and diffuse at least some of the projecting metal, mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: A power MOSFET includes an n−-drain layer, a drain contact layer disposed on a first side of the drain layer, a p-type base layer disposed on a second side of the drain layer, and an n-source layer disposed on the base layer. A gate electrode faces, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers. Source and drain electrodes are electrically connected to the source and drain contact layers, respectively. A plurality of hetero regions having a dielectric constant higher than that of the drain layer is disposed in the drain layer between the source and drain electrodes.

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract: In a semiconductor device such as GaN semiconductor laser having an electrode formed on a nitride III-V compound semiconductor layer containing at least Ga, such as GaN layer, at least a part of the electrode in contact with the nitride III-V compound semiconductor layer is made of a &ggr;-GaNi alloy or a &ggr;′-GaNi alloy. The electrode is made by first stacking the &ggr;-GaNi alloy layer or &ggr;′-GaNi alloy layer, or its component elements, on the nitride III-V compound semiconductor layer, and then annealing it at a temperature not lower than 680° C., or by stacking any of them on the nitride-compound III-V compound semiconductor layer heated to a temperature not lower than 680° C. At least a part of the electrode in contact with the nitride III-V compound semiconductor layer may be made of an alloy of Ga and at least one kind of element selected from the group consisting of Pt, Ag, Pd, Mg, Hf, Al, Cr, Ti, Mo, W, Zr, Si and Ge.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: A method of fabricating an Emode HIGFET semiconductor device, and the device, is disclosed including epitaxially growing by metal-organic chemical vapor deposition an epitaxial buffer. The buffer includes a layer of short-lifetime gallium arsenide on a gallium arsenide substrate and a layer of aluminum gallium arsenide on the layer of short-lifetime gallium arsenide. The short-lifetime gallium arsenide is grown at a temperature below approximately 550° C. so as to have a lifetime less than approximately 500 picoseconds. A stack of compound semiconductor layers is then epitaxially grown on the layer of aluminum gallium arsenide of the buffer and an Emode field effect transistor is formed in the stack.

Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.

Abstract: The semiconductor light emitting element of the present invention includes: a compound semiconductor substrate having a first conductivity type; a light emitting layer; a compound semiconductor interface layer having a second conductivity type and not containing Al; and a current diffusion layer having the second conductivity type and being made of a compound semiconductor not containing Al.

Abstract: A method for fabricating a semiconductor device that includes a semiconductor layer, containing Si and C, for its active region. Ions of a dopant are implanted into an SiC substrate a number of times, thereby forming a doped layer with multiple dopant concentration peaks in the substrate. Thereafter, the substrate is placed and annealed in a chamber with an etching gas (e.g., hydrogen gas) supplied thereto. In this manner, while the substrate is being annealed, the upper part of the doped layer is removed with the lower part thereof left. Accordingly, the dopant concentration at the surface of the lower doped layer can be easily controlled to such a value as required for forming a Schottky or ohmic electrode thereon. In addition, the upper doped layer with a lot of defects is removed, and therefore the surface region of the substrate can have its crystallinity improved.

Abstract: In a method for manufacturing a silicon carbide semiconductor device, preliminary heat treatment is conducted after implanting impurity ions into a silicon carbide substrate, such that the silicon carbide substrate is heated at a temperature in a range of, for example, 800 to 1200° C., in a hydrogen atmosphere or a mixed gas ambient comprising hydrogen and inert gas. After the preliminary heat treatment, the silicon carbide substrate may be annealed at a high temperature.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.

Abstract: A method of activating a compound semiconductor layer into a p-type compound semiconductor layer is provided. In order to reduce the electrical conductivity of the compound semiconductor layer grown by a VPE method, electromagnetic waves having energy larger than the band gap of the compound semiconductor layer are irradiated and annealing is performed. If the amount of the p-type impurities contained in the layer during growth thereof increases, the resistivity of the layer increases and an annealing temperature is lowered. Also, the contact resistance between the compound semiconductor layer and an electrode is reduced.

Abstract: In one aspect, the invention includes a method of maintaining dimensions of an opening in a semiconductive material stencil mask comprising providing two different dopants within a periphery of the opening, the dopants each being provided to a concentration of at least about 1017 atoms/cm3.

Abstract: Acceptor atoms such as aluminum (Al) and boron (B) are introduced into a silicon carbide (SiC) semiconductor by ion implantation, and carbon (C) atoms additionally are introduced by ion implantation, whereby the electrical activation of the acceptor atoms is enhanced while controlling their diffusion that results from a subsequent thermal treatment. The process enables the production of a p-type SiC semiconductor of better quality.

Abstract: A surface portion of a p type base region is made amorphous as an amorphous layer by implanting nitrogen ions which serve as impurities and ions which do not serve as impurities. After that, the amorphous layer is crystallized to have a specific crystal structure through solid-phase growth while disposing the impurities at lattice positions of the crystal structure. As a result, a surface channel layer is formed with a high activation rate of the impurities.

Abstract: A process is disclosed for producing pn junctions and p-i-n junctions from group III nitride compound semiconductor materials. The process comprises growing of pn junctions and p-i-n junctions by hydride vapor phase epitaxy employing hydride of nitrogen (ammonia, hydrozine) as a source of nitrogen and halides of group III metal as a source of metal. Mg is used as acceptor impurity to form p-type III-V nitride layers. The preferred sources for Ga and Al are Ga and Al metals, respectively. The process is carried out in the temperature range from 900 to 1200° C.

Abstract: A variable bandgap infrared absorbing material, Hg1-x Cdx Te, is manufactured by use of the process termed MOCVD-IMP (Metalorganic Chemical Vapor Deposition-Interdiffused Multilayer Process). A substantial reduction in the dislocation defect density can be achieved through this method by use of CdZnTe layers which have a zinc mole fraction selected to produce a lattice constant which is substantially similar to the lattice constant of HgTe. After the multilayer pairs of HgTe and Cd0.944Zn0.056Te are produced by epitaxial growth, the structure is annealed to interdiffuse the alternating layers to produce a homogeneous alloy of mercury cadmium zinc telluride. The mole fraction x in Hg1-x(Cd0.944Zn0.056)xTe can be varied to produce a structure responsive to multiple wavelength bands of infrared radiation, but without changing the lattice constant. The alloy composition is varied by changing the relative thicknesses of HgTe and Cd0.944Zn0.056Te.

Abstract: A method of fabricating a semiconductor device on a substrate, wherein the substrate comprises a first layer of doped silicon carbide of a first conducting type and exhibits at least one hollow defect. In a first step the positions of the hollow defects in the substrate are identified, whereafter a second SiC layer of a second conducting type is formed in contact with the first layer, whereafter the first and second layer constituting the pn junction are provided with at least one edge termination surrounding any hollow defect, whereby the defect is excluded from the high-field region of the device.