Thermally Responsive Patents (Class 438/54)
-
Publication number: 20080099681Abstract: First, an electrode is formed on an insulation layer that has been formed on a silicon substrate, when manufacturing an infrared detection device. The electrode has a shape matching that of a thermal resistance element constituting the infrared detection device. A semiconductor substrate is placed in a reaction chamber, given a predetermined potential, and heated. Next, a material of a thermal resistor substance constituting the thermal resistance element is vaporized into a gaseous material, and the gaseous material is ion-clusterized and supplied into the reaction chamber. The gaseous material collects toward the electrode as a result of an action of an electric field generated by giving the electrode the predetermined potential. The gaseous material that came into contact with the electrode is stabilized by receiving electrons, and thermally decomposes, thus growing a thermal resistor substance on the electrode.Type: ApplicationFiled: February 17, 2004Publication date: May 1, 2008Inventors: Yasuhiro Shimada, Daisuke Ueda
-
Patent number: 7354786Abstract: A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one of the access holes and the cavity being produced in the substrate by a trench etching and/or, in particular, an isotropic etching process. The trench etching process includes different trenching (trench etching) steps which may be divided into a first phase and a second phase. Thus, in the first phase, at least one first trenching step is carried out in which, in a predeterminable first time period, material is etched out of the substrate and a depression is produced. In that trenching step, a typical concavity is produced in the wall of the depression.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Stefan Finkbeiner, Matthias Illing, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
-
Publication number: 20080079109Abstract: A thermoelectric device includes: a first insulator substrate; a plurality of first pads of copper foil attached to the first insulator substrate; a second insulator substrate; a plurality of second pads of copper foil attached to the second insulator substrate; and a plurality of alternately disposed p-type and n-type semiconductor elements disposed between the first and second insulator substrates. Each of the p-type and n-type semiconductor elements has two opposite ends that are respectively bonded to a respective one of the first pads of copper foil and a respective one of the second pads of copper foil through a copper brazing material.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventor: Chin-Kuang Luo
-
Patent number: 7351602Abstract: A process for producing a thin film with MEMS probe circuits by using semiconductor process technology comprises steps of providing a flatted process substrate; forming a separable interface on the flatted process substrate; forming a probe circuit thin film with electric circuits, probes and circuit contacts on the separable interface; forming a raised probe supported-spacer on the probe circuit thin film; separating the probe circuit thin film from the process substrate; and processing a subsequent microstructure working to obtain a thin film with MEMS probe circuits which use the raised probe supported-spacer to form a buffer to prevent the probes from being exposed to much pressure.Type: GrantFiled: December 29, 2005Date of Patent: April 1, 2008Inventor: Wen-Chang Dong
-
Patent number: 7349762Abstract: Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.Type: GrantFiled: November 10, 2005Date of Patent: March 25, 2008Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Takashi Omizo, Charles R. Johns, Michael F. Wang, Kazuaki Yazawa, Toshiyuki Hiroi
-
Publication number: 20080057611Abstract: A method of manufacturing a thin-film thermoelectric generator comprises the steps of: coating of a carrier film with a first semiconductor of a first conductor type, structuring of the first semiconductor, coating of the carrier film with a second semiconductor of a second conductor type and structuring of the second semiconductor. The carrier film is provided for the coating and structuring operations as a film roll.Type: ApplicationFiled: August 10, 2007Publication date: March 6, 2008Applicant: ANGARIS GMBHInventors: Matthias Stordeur, Bernd Engers, Jens Schultz
-
Publication number: 20080036101Abstract: A process for synthesizing a metal telluride is provided that includes the dissolution of a metal precursor in a solvent containing a ligand to form a metal-ligand complex soluble in the solvent. The metal-ligand complex is then reacted with a telluride-containing reagent to form metal telluride domains having a mean linear dimension of from 2 to 40 nanometers. NaHTe represents a well-suited telluride reagent. A composition is provided that includes a plurality of metal telluride crystalline domains (PbTe)1-x-y(SnTe)x(Bi2Te3)y ??(I) having a mean linear dimension of from 2 to 40 nanometers inclusive where x is between 0 and 1 inclusive and y is between 0 and 1 inclusive with the proviso that x+y is less than or equal to 1. Each of the metal telluride crystalline domains has a surface passivated with a saccharide moiety or a polydentate carboxylate.Type: ApplicationFiled: August 14, 2006Publication date: February 14, 2008Applicant: Toyota Engineering & Manufacturing North America, Inc.Inventors: Qiangfeng Xiao, Yunfeng Lu, Minjuan Zhang
-
Publication number: 20080026503Abstract: Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of the three or more edges. The temperatures sensors are arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors. Thermal management of the integrated circuit may be accomplished by modifying functional aspects of the integrated circuit in response to measurements provided by the temperature sensors.Type: ApplicationFiled: July 27, 2006Publication date: January 31, 2008Inventor: Vivian Ryan
-
Patent number: 7309830Abstract: A thermoelectric material comprises two or more components, at least one of which is a thermoelectric material. The first component is nanostructured, for example as an electrically conducting nanostructured network, and can include nanowires, nanoparticles, or other nanostructures of the first component. The second component may comprise an electrical insulator, such as an inorganic oxide, other electrical insulator, other low thermal conductivity material, voids, air-filled gaps, and the like. Additional components may be included, for example to improve mechanical properties. Quantum size effects within the nanostructured first component can advantageously modify the thermoelectric properties of the first component. In other examples, the second component may be a thermoelectric material, and additional components may be included.Type: GrantFiled: May 3, 2005Date of Patent: December 18, 2007Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., The Administrators of the Tulane Educational FundInventors: Minjuan Zhang, Yunfeng Lu
-
Patent number: 7306967Abstract: A method of manufacturing high temperature thermistors from an ingot. The high temperature thermistors can be comprised of germanium or silicon. The high temperature thermistors have at least one ohmic contact.Type: GrantFiled: May 15, 2004Date of Patent: December 11, 2007Assignee: AdSem, Inc.Inventor: Michael Kozhukh
-
Patent number: 7282384Abstract: The present invention provides an SiGe-based thin film, a method for manufacturing this thin film, and applications of this thin film.Type: GrantFiled: November 11, 2003Date of Patent: October 16, 2007Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Woosuck Shin, Fabin Qiu, Noriya Izu, Ichiro Matsubara, Norimitsu Murayama
-
Patent number: 7276277Abstract: A micromechanical component and a method of producing same are described; the component has a supporting body, in particular a silicon body, and a membrane which is connected to the supporting body and is unsupported at least in some areas. The membrane is also provided with at least one stabilizing element in an unsupported area in some areas of the surface.Type: GrantFiled: June 21, 2001Date of Patent: October 2, 2007Assignee: Robert Bosch GmbHInventors: Hans Artmann, Robert Siegel
-
Patent number: 7268008Abstract: A method for manufacturing a pressure sensor includes the steps of: preparing a semiconductor substrate; forming an insulation film on the substrate; forming a first metal film on the insulation film; forming a first protection film on the first metal film and the insulation film; forming a second protection film on the first metal film and the first protection film; performing reduction treatment of adhesive force on the second protection film, the force between the second protection film and a second metal film; forming the second metal film on the first metal film and the first protection film; and removing a part of the second metal film.Type: GrantFiled: January 5, 2006Date of Patent: September 11, 2007Assignee: DENSO CorporationInventors: Manabu Tomisaka, Yoshifumi Watanabe, Hiroaki Tanaka
-
Patent number: 7233000Abstract: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the cavity (3) underneath provides very good thermal isolation for the sensor elements, so as the power needed to maintain the heater (4) at a given temperature is very low. The formation process of the porous silicon membrane (2) with the cavity (3) underneath is a two-step single electrochemical process. It is based on the fact that when the anodic current is relatively low, we are in a regime of porous silicon formation, while if this current exceeds a certain value we turn into a regime of electropolishing. The process starts at low current to form porous silicon (2) and it is then turned into electropolishing conditions to form the cavity (3) underneath.Type: GrantFiled: January 16, 2003Date of Patent: June 19, 2007Inventors: Androula G. Nassiopoulou, Grigoris Kaltsas, Dimitrios N. Pagonis
-
Patent number: 7229694Abstract: A micromechanical component includes an anti-adhesive layer, formed from at least one fluorine-containing silane, applied to at least parts of its surface for reducing surface forces. To increase mechanical and thermal load capacity, the anti-adhesive layer is provided as a multilayer coating which is formed from at least one metal oxide layer and at least one layer composed of at least one fluorine-containing silane.Type: GrantFiled: May 27, 2003Date of Patent: June 12, 2007Assignee: Robert Bosch GmbHInventors: Lutz Mueller, Kersten Kehr, Markus Ulm
-
Patent number: 7205231Abstract: The present invention is directed to a method for thermally processing a substrate in a thermal processing system. The method provides an amount of heat to the substrate and obtains information associated with the substrate when the amount of heat is provided. For example, the substrate is provided at a presoak position within the thermal processing system, wherein the presoak position, and one or more properties associated with the substrate, such as a position and temperature, are measured. An optimal process parameter value to provide an optimal thermal uniformity of the substrate is then determined, based, at least in part, on the information obtained from the substrate. For example, a soak position of the substrate is determined, wherein the determination is based, at least in part, on the one or more measured properties associated with the substrate, and a thermal uniformity associated with a reference data set.Type: GrantFiled: October 29, 2004Date of Patent: April 17, 2007Assignee: Axcelis Technologies, Inc.Inventors: Peter A. Frisella, Paul Lustiber, James Willis
-
Patent number: 7195946Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.Type: GrantFiled: July 2, 2004Date of Patent: March 27, 2007Assignee: STMicroelectronics, S.r.L.Inventors: Giuseppe D'Arrigo, Rosario Corrado Spinella
-
Patent number: 7166796Abstract: In devices used for the direct conversion of heat into electricity, or vice versa, known in the art as thermoelectric power generators, thermoelectric refrigerators and thermoelectric heat pumps, the efficiency of energy conversion and/or coefficient of performance have been considerably lower than those of conventional reciprocating or rotary, heat engines and/or vapor-compression systems, employing certain refrigerants. The energy conversion efficiency of power generating devices, for example, aside from the hot and cold junction temperatures, also depends on a parameter known in the art as the thermoelectric figure of merit Z=S2?/k, where S is the thermoelectric power, ? is the electrical conductivity and k is the thermal conductivity, of the material that constitutes the p-type, and/or n-type, thermoelements, or branches, of the said devices. In order to achieve a considerable increase in the energy conversion efficiency, a thermoelectric figure of merit of the order of 10?2 K?1, or more, is needed.Type: GrantFiled: September 5, 2002Date of Patent: January 23, 2007Inventor: Michael C. Nicoloau
-
Patent number: 7115437Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.Type: GrantFiled: September 8, 2004Date of Patent: October 3, 2006Assignee: Georgia Tech Research CorporationInventors: Mark G. Allen, Charles C. Chung
-
Patent number: 7112862Abstract: A light emitting and detecting device and a method of manufacturing the same are provided. The method includes forming an insulating layer on a substrate doped with an n-type dopant or a p-type dopant, and removing a portion of the insulating layer to expose a predetermined area of the substrate; forming a doping layer doped with an opposite dopant to the dopant of the substrate by applying a dopant on the exposed area of the substrate and heat treating the substrate to create a light conversion effect in a p-n junction between the substrate and the doping layer; and forming first and second electrodes on the substrate to electrically connect the doping layer. Thus, it is possible to control the diffusion depth of the doping layer with opposite dopant to the substrate in the substrate.Type: GrantFiled: October 15, 2004Date of Patent: September 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-kyung Lee, Byoung-lyong Choi, Jun-young Kim
-
Patent number: 7087451Abstract: A microfabricated vacuum sensor may be formed using semiconductor integrated circuit processes. The sensor may be formed inside an enclosure with a microfabricated component. The sensor may then be used to measure the pressure within the enclosure.Type: GrantFiled: March 24, 2004Date of Patent: August 8, 2006Assignee: Intel CorporationInventors: Leonel R. Arana, Yuelin Lee Zou, John Heck
-
Patent number: 7081677Abstract: A thermoelectric module is constituted by a pair of substrates having electrodes, which are arranged opposite to each other with a prescribed space therebetween, in which a prescribed number of thermoelectric elements are arranged in such a way that a p-type and an n-type are alternately arranged, so that the thermoelectric elements are connected in series or in parallel together with the electrodes. Herein, one substrate is a heat absorption side, and other substrate is a heat radiation side. In addition, a current density in a current transmission area of the heat-absorption-side electrode is set to 50 A/mm2 or less, and a height of the thermoelectric element is set to 0.7 mm or less. Furthermore, a temperature-controlled semiconductor module can be realized by combining a thermoelectric module with a semiconductor component such as a semiconductor laser.Type: GrantFiled: March 21, 2003Date of Patent: July 25, 2006Assignee: Yamaha CorporationInventors: Masayoshi Yamashita, Naoki Kamimura, Fumiyasu Tanoue, Katsuhiko Onoue, Toshiharu Hoshi
-
Patent number: 7078259Abstract: A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).Type: GrantFiled: January 8, 2004Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Jon A. Casey, William J. Ferrante, Edward W. Kiewra, Carl J. Radens, William R. Tonti
-
Patent number: 7075129Abstract: An image sensor includes a substrate of the first conductivity type; a channel of the first conductivity type that spans at least a portion of the substrate; a well of the second conductivity type that is positioned between the channel and substrate for a predetermined portion and that is not between the substrate and the channel for a predetermined portion all of which well is substantially continuous; and a connection to the well; wherein a resistance of the well not between the substrate and the channel is substantially equal to or greater than twenty five percent of a total resistance of the well between the channel and the substrate.Type: GrantFiled: January 9, 2004Date of Patent: July 11, 2006Assignee: Eastman Kodak CompanyInventor: Christopher Parks
-
Patent number: 7071008Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.Type: GrantFiled: August 4, 2003Date of Patent: July 4, 2006Inventors: Darrell Rinerson, Wayne Kinney, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Steve Kuo-Ren Hsia
-
Patent number: 7067733Abstract: Thermoelectric material is produced through a process sequence including a liquid quenching, a primary solidification such as a hot pressing or extrusion and an upset forging; although the C-planes of the crystal grains are directed in parallel to the direction in which the force is exerted on flakes during the hot pressing/extrusion, the a-axes are randomly directed; the a-axes are oriented in a predetermined direction through the upset forging; this results in improvement of electric resistivity without reduction in the figure of merit.Type: GrantFiled: December 12, 2002Date of Patent: June 27, 2006Assignee: Yamaha CorporationInventors: Yuma Horio, Junya Suzuki
-
Patent number: 7009268Abstract: A Wheatstone bridge circuit for a sensor has: first and second sensor elements which respond to a stimulus generated when the sensor is exposed to a sample to be measured, the first and second sensor elements comprising first and second elongated n type nano width regions formed in a suitable substrate; third and fourth sensor elements which respond to the stimulus generated when the sensor is exposed to the sample to be measured, comprising third and fourth elongated p type nano width regions formed in the substrate; and interconnections which interconnect the first and second sensor elements with the third and fourth sensor elements so that the first and second sensor elements are separated from and connected to the third and fourth sensor elements in a manner to form a Wheatstone bridge configuration.Type: GrantFiled: April 21, 2004Date of Patent: March 7, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Xiaofeng Yang, Kevin Peters
-
Patent number: 6995028Abstract: A method of manufacturing thermal type flow sensing elements is provided which improves workability and reliability without increasing manufacturing costs. Each flow sensing element comprises two lead patterns that are connected to both ends of a heat generating resistance and two lead patterns that are connected to both ends of a temperature sensing resistance. The lead patterns connected to the ends of the heat generating resistance are both connected to dummy patterns in the vicinity of electrodes. As for the lead patterns connected to the ends of the temperature sensing resistance, either one of them is connected to the dummy pattern in the vicinity of the electrode. The dummy patterns are patterned so as to provide parallel connection of the heat generating resistances of a plurality of flow sensing elements formed on a substrate, through the lead patterns.Type: GrantFiled: September 20, 2004Date of Patent: February 7, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masahiro Kawai
-
Patent number: 6984543Abstract: A method of producing a laminated PTC thermistor involves alternately laminating electroconductive pastes to form internal electrodes and ceramic green sheets to form semiconductor ceramic layers with a positive resistance-temperature characteristic to form a laminate, firing the laminate to form a ceramic piece, and forming external electrodes on both of the end-faces of the ceramic piece, and heat-treating the ceramic piece having the external electrodes formed thereon at a temperature between about 60° C. and 200° C.Type: GrantFiled: August 13, 2003Date of Patent: January 10, 2006Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenjirou Mihara, Atsushi Kishimoto, Hideaki Niimi
-
Patent number: 6972199Abstract: A cutting instrument including a metal blade has a recess formed therein and a semiconductor substrate affixed to the blade in the recess. The semiconductor substrate includes at least one sensor formed thereon. The sensor formed on the semiconductor substrate may comprise at least one or an array of a strain sensors, pressure sensors, nerve sensors, temperature sensors, density sensors, accelerometers, and gyroscopes. The cutting instrument may also further include a handle wherein the blade is affixed to the handle and the semiconductor substrate is electrically coupled to the handle. The handle may then be coupled, either physically or by wireless transmission, to a computer that is adapted to display information to a person using the cutting instrument based on signals generated by one or more of the sensors formed on the semiconductor substrate. The computer or handle may also be adapted to store data based on the signals generated by one or more of the sensors.Type: GrantFiled: April 17, 2002Date of Patent: December 6, 2005Assignee: Verimetra, Inc.Inventors: Kyle S. Lebouitz, Michele Migliuolo
-
Patent number: 6963119Abstract: An integrated optical transducer assembly includes a substrate and an optoelectronic array attached to the substrate. The optoelectronic array further includes a plurality of individual subunits bonded together to form a single array, with each of the subunits including a defined number of individual optoelectronic elements associated therewith. The elastomeric material maintains an original alignment between the plurality of subunits.Type: GrantFiled: May 30, 2003Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventors: Evan G. Colgan, Casimer M. DeCusatis, Lawrence Jacobowitz, Daniel J. Stigliani, Jr.
-
Patent number: 6958256Abstract: The present invention relates to a process for the back-surface grinding of wafers using films which have a support layer, which is known per se, and an adhesion layer which can be polymerized in steps, and to films which include such an adhesion layer which can be polymerized in steps, and to the use thereof.Type: GrantFiled: October 30, 2003Date of Patent: October 25, 2005Assignee: Infineon Technologies AGInventors: Michael Rogalli, Manfred Schneegans
-
Patent number: 6955935Abstract: Disclosure is a method for a chemical mechanical polishing process for fabricating a semiconductor device. The method for performing the chemical mechanical polishing process for a copper layer on a semiconductor wafer comprises the steps of: performing the chemical mechanical polishing process for the copper layer on the semiconductor wafer by using slurry; performing a standstill process in a middle of the chemical mechanical polishing process; and carrying out the chemical mechanical polishing process again after performing the standstill process.Type: GrantFiled: June 25, 2004Date of Patent: October 18, 2005Assignee: Hynix Semiconductor Inc.Inventor: Jong Hyuk Park
-
Patent number: 6953921Abstract: A bolometric humidity sensor, cooker having the same applied thereto, and method for controlling the cooker are provided. The bolometric humidity sensor has two static bolometric temperature sensors for detecting humidity more accurately. A cooker may have such a bolometric humidity sensor fitted to one side of a bracket on an air outlet for deflecting air flowing out of the cooker. This arrangement allows for more accurate detection of the humidity in the cooking chamber. A method of controlling a cooker could include the use of such a sensor to permit a cooking time period to differ depending on whether the cooked food is wrapped.Type: GrantFiled: March 31, 2001Date of Patent: October 11, 2005Assignee: LG Electronics Inc.Inventor: Sang Doo Kim
-
Patent number: 6946316Abstract: An image sensor package includes a molding having a locking feature. The package further includes a snap lid having a tab, where the tab is attached to the locking feature of the molding. To form the image sensor package, a window is placed in a pocket of the molding. The snap lid is secured in place. Once secured, the snap lid presses against a peripheral region of an exterior surface of the window. The window is sandwiched between the molding and the snap lid and held in place.Type: GrantFiled: October 31, 2002Date of Patent: September 20, 2005Assignee: Amkor Technology, Inc.Inventors: Thomas P. Glenn, Steven Webster
-
Patent number: 6933166Abstract: A method of manufacturing a component, in particular a thermal sensor, and a thermal sensor. The component has at least two regions having different heat conductivities, a surface region being created in a substrate and the heat conductivity of the surface region being lower than that of the surrounding substrate. For producing a flat topography on the component a layer is created which covers the surface region. The layer and the surface region have at least approximately similar physical properties.Type: GrantFiled: April 23, 2003Date of Patent: August 23, 2005Assignee: Robert Bosch GmbHInventor: Thorsten Pannek
-
Patent number: 6933585Abstract: The invention concerns a color image sensor that can be used to make a miniature camera, and a corresponding method for making this sensor. The image sensor comprises a transparent substrate (40) on the upper part of which are superimposed, successively, a mosaic of color filters (18), a very thin silicon layer (30) comprising photosensitive zones, and a stack of conductive layers (14) and insulating layers (16) defining image detection circuits enabling the collection of the electrical charges generated by the illumination of the photosensitive zones through the transparent substrate. The manufacturing method consists in producing the photosensitive circuits on a silicon wafer, transferring said wafer on to a temporary substrate, thinning the wafer down to a thickness of about three to 30 micrometers, depositing color filters on the surface of the remaining silicon layer and transferring the structure to a permanent transparent substrate and eliminating the temporary substrate.Type: GrantFiled: August 30, 2002Date of Patent: August 23, 2005Assignee: Atmel Grenoble S.A.Inventors: Louis Brissot, Eric Pourquier
-
Patent number: 6927087Abstract: An active matrix substrate for a liquid crystal display and method of forming the same. To form the active matrix substrate five masks are needed. The first mask forms gate lines on the transparent substrate. The second mask patterns a stacked layer of a metal layer/an n-doped layer/a semiconductor layer formed on a gate insulating layer to form data lines. After forming a low k dielectric layer, the third mask forms openings therein. The forth mask patterns pixel electrodes and conducting lines with source pattern on the low k dielectric layer and further patterns the metal layer and the n-doped layer. After depositing a passivating layer the fifth mask defines the passivating layer.Type: GrantFiled: August 16, 2004Date of Patent: August 9, 2005Assignee: AU Optronics Corp.Inventor: Han-Chung Lai
-
Patent number: 6867059Abstract: An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition (PE-LPCVD) to obtain an a-C:H ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the a-C:H ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rates of the a-C:H ISFET for different pH and hysteresis width of the a-C:H ISFET for different pH loops are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the a-C:H ISFET.Type: GrantFiled: March 29, 2004Date of Patent: March 15, 2005Assignee: National Yunlin University of Science and TechnologyInventors: Jung-Chuan Chou, Hsuan-Ming Tsai
-
Patent number: 6847067Abstract: An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition (PE-LPCVD) to obtain an a-C:H ISFET. The present invention also measures the current-voltage curve for different pH and temperatures by a current measuring system. The temperature parameter of the a-C:H ISFET is calculated according to the relationship between the current-voltage curve and temperature. In addition, the drift rates of the a-C:H ISFET for different pH and hysteresis width of the a-C:H ISFET for different pH loops are calculated by a constant voltage/current circuit and a voltage-time recorder to measure the gate voltage of the a-C:H ISFET.Type: GrantFiled: April 22, 2003Date of Patent: January 25, 2005Assignee: National Yunlin University of Science and TechnologyInventors: Jung-Chuan Chou, Hsuan-Ming Tsai
-
Patent number: 6843596Abstract: A device for thermal sensing is based on only one thermopile. The junctions of the thermopile are coupled thermally to a first region which includes a first substance while the hot junctions of the thermopile are coupled thermally to a second region which includes a second substance. The first and second regions are separated and thermally isolated from each other. The device can further include a membrane to thermally and electrically isolate the thermopile and to mechanically support the thermopile.Type: GrantFiled: March 7, 2003Date of Patent: January 18, 2005Assignee: Vivactis NVInventor: Katarina Verhaegen
-
Patent number: 6841412Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (122), which is glass in the case of many DMD packages, seals the device (100) in a package cavity (120).Type: GrantFiled: November 3, 2000Date of Patent: January 11, 2005Assignee: Texas Instruments IncorporatedInventors: Edward C. Fisher, Lawrence T. Latham
-
Patent number: 6838303Abstract: The present invention relates to a silicon pressure sensor that in need of three strips of piezoresistors on each side and the manufacturing method thereof; wherein, the impurity concentration of the piezoresistors are about 1019-1020 cm?3 in order to reduce the influence of temperature; the lead between the piezoresistors (namely the internal connection lead) is a highly-doping interconnect (about 1021 cm?3) fabricated along the direction with minimum piezoresistance coefficient; with regard to the connection circuit for connecting the piezoresistors with the external Wheatstone bridge circuit (namely the external connection circuit), of which one end near the inner side of the membrane is also fabricated along the direction with minimum piezoresistance coefficient, and another end of the lead near the edge of the membrane is a interconnect that is perpendicular to the diaphragm, and is connected out to the external circuit; with this structure, the four resistors of the Whetstone bridge are balanced and symType: GrantFiled: March 19, 2003Date of Patent: January 4, 2005Assignee: Asia Pacific Microsystems, Inc.Inventors: Hung-Dar Wang, Shih-Chin Gong
-
Patent number: 6835578Abstract: A method of measuring the stress migration of vias, and a the structure, the method comprising the following steps. A metal line having a middle and opposing first and second ends is formed. First and second opposing pads electrically connected to the respective opposing first and second ends of the metal line through respective first and second step-width line structures are formed. A third pad connected to the metal line proximate its first end by a first via through a first metal structure is formed. A fourth pad connected to the metal line proximate its second end by a second via through a second metal structure is formed. The first and second vias are equidistant from the respective first and second ends of the metal line. The stress migration of the first via is determined by measuring the: sheet resistance between the first pad and the third pad; and/or the stress migration of the second via is determined by measuring the sheet resistance between the fourth pad and the second pad.Type: GrantFiled: September 26, 2003Date of Patent: December 28, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Te S. Lin, Chin-Chiu Hsia
-
Patent number: 6825057Abstract: A process for manufacturing a membrane sensor over a silicon substrate, preferably a thermal membrane sensor. A thin layer of silicon carbide or silicon nitride is deposited over an area of porous silicon formed in the surface of the substrate, and then openings that extend as far as the layer of porous silicon are formed in the silicon carbide or silicon nitride layer via a dry etching process. Next, semiconductor structures and conductor path structures are implanted into the upper surface of the membrane layer via lithographic steps, and then the sacrificial layer of porous silicon is removed using a suitable solvent such as ammonia. Thus an empty space that thermally isolates the sensor membrane from the substrate is created beneath the membrane layer.Type: GrantFiled: October 25, 1999Date of Patent: November 30, 2004Assignee: Robert Bosch GmbHInventors: Klaus Heyers, Wilhelm Frey
-
Patent number: 6821819Abstract: A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.Type: GrantFiled: February 20, 2003Date of Patent: November 23, 2004Assignee: Sandia CorporationInventors: Gilbert L. Benavides, Paul C. Galambos, John A. Emerson, Kenneth A. Peterson, Rachel K. Giunta, David Lee Zamora, Robert D. Watson
-
Patent number: 6818468Abstract: Methods and apparatuses for incorporating low contrast and high contrast interfaces in optical devices. In one embodiment an insulator is disposed proximate to a plurality of regions of a semiconductor including regions through which an optical beam is directed. High contrast interfaces are defined between the semiconductor and the insulator. Low contrast interfaces are defined between a doped region and the semiconductor. The optical beam is directed through the doped region from one of the plurality of semiconductor regions to another of the plurality of regions with relatively low loss. Optical coupling or evanescent coupling depending on an incident angle of the optical beam relative to the low contrast interface may occur through the doped region and low contrast interface.Type: GrantFiled: January 3, 2003Date of Patent: November 16, 2004Assignee: Intel CorporationInventor: Michael T. Morse
-
Patent number: 6815244Abstract: A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive V-VI layer, in particular a (Bi, Sb)2 (Te, Se)3 layer. The V-VI layer is formed by use of a seed layer or by a structure formed in the substrate, and disposed relative to the substrate such that an angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. The orientation can also be effected by an electric field. Components are formed of the thermoelectric layer structure in which the angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. As a result, the known anisotropy of the V-VI materials can advantageously be used for the construction of components.Type: GrantFiled: June 27, 2003Date of Patent: November 9, 2004Assignee: Infineon Technologies AGInventors: Harald Böttner, Axel Schubert, Joachim Nurnus, Christa Künzel
-
Patent number: 6806510Abstract: In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.Type: GrantFiled: December 14, 2001Date of Patent: October 19, 2004Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Minoru Suzuki, Susumu Yoshida
-
Patent number: RE39143Abstract: A method for fabricating a wafer-pair having at least one recess in one wafer and the recess formed into a chamber with the attaching of the other wafer which has a port plugged with a deposited layer on its external surface. The deposition of the layer may be performed in a very low pressure environment, thus assuring the same kind of environment in the sealed chamber. The chamber may enclose at least one device such as a thermoelectric sensor, bolometer, emitter or other kind of device. The wafer-pair typically will have numerous chambers, with devices, respectively, and may be divided into a multiplicity of chips.Type: GrantFiled: December 3, 2001Date of Patent: June 27, 2006Assignee: Honeywell International Inc.Inventors: R. Andrew Wood, Jeffrey A. Ridley, Robert E. Higashi