Abstract: Ohmic contact formation on p-type Silicon Carbide is disclosed. The formed contact includes an initial amorphous Carbon film layer converted to graphitic sp2 Carbon during an elevated temperature annealing sequence. Decreased annealing sequence temperature, reduced Silicon Carbide doping concentration and reduced specific resistivity in the formed ohmic contact are achieved with respect to a conventional p-type Silicon Carbide ohmic contact. Addition of a Boron carbide layer covering the p-type Silicon Carbide along with the sp2 Carbon is also disclosed. Ohmic contact improvement with increased annealing temperature up to an optimum temperature near 1000° C. is included. Addition of several metals including Aluminum, the optimum metal identified, over the Carbon layer is also included; many other of the identified metals provide Schottky rather than the desired ohmic contacts, however.

Abstract: A method of making a transparent electrode for a light-emitting diode includes depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal, the mask having at least one opening so that the first region is covered by the mask and a second region is aligned with the at least one opening in the mask. The method also includes removing metal aligned with the at least one opening in the mask in the second region to form the first electrode overlying the first region of the semiconductor structure and so as to reveal the top surface of the semiconductor structure in the second region.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A metal layer A constituting the stripe-shaped cathode electrode is formed on the surface of the organic electroluminescence layer 13, a peeling film B is stuck to the surface of the metal layer A through such an adhesive C as to reduce adhesion to the metal layer by the irradiation of ultraviolet light, and a pattern according to the stripe-shaped cathode electrodes 14 is baked onto the peeling film B by the irradiation of ultraviolet light E by using a mask D and the peeling film B is then peeled from the organic electroluminescence layer 13.

Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.

Abstract: A p-type contact electrode device in a ZnSe-based II-VI compound semiconductor, which electrode device uses, as a contact layer, a BeTe layer having a high p-type doping and a low lattice mismatching with a GaAs substrate to prevent oxidation in air. The device 2 includes a contact layer 5 composed of p-BeTe and a cap layer 4 is composed of p-ZnSe. The cap layer 4 is positioned on the contact layer 5 and an electrode 3 sits atop the cap layer. Preferably, the thickness of the cap layer is 30 to 70 Å and the electrode is composed of gold or gold is dispersed in the cap layer.

Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.

Abstract: A p-type ohmic electrode in a gallium nitride based(GaN based) optical device and a fabrication method thereof. The p-type ohmic electrode in a GaN based optical device is fabricated using a rutile structure transition metal layer, such as an Ru, Ir or Os layer, or an oxide layer thereof, or using a double layer comprised of an Ru layer as a base layer and an Ni layer, an ITO layer or an AuO layer on the Ru layer. Thus, the p-type ohmic electrode is good in light transmittance and is thermally stable while having low contact resistance with the p-GaN layer.

Abstract: A bi-functional optical detector including a first active photoconduction detection element configured to detect light within first and second wavelength ranges, a first diffraction grating associated with the first detection element and configured to couple the light within the first wavelength range so that the first active photoconducting detection element detects the light in the first wavelength range, a second active photoconduction detection element configured to detect light within the first and second wavelength ranges, and a second diffraction grating associated with the second detection element and configured to couple the light within the second wavelength range so that the second active photoconduction detection element detects the light in the second wavelength range.

Abstract: An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a laser beam having a wavelength absorbable in at least one of the semiconductor and the metal layer. The irradiation energy of the laser beam is set in a range of 20 to 100 mJ/cm2. The material having a low thermal conductivity is a resin or amorphous silicon. According to the alloying method using laser irradiation, since the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effect on characteristics of the semiconductor device.

Abstract: A light-emitting element comprising a transparent electrode, a light-emitting layer, and a back electrode, on a substrate, wherein the light-emitting layer comprises photoluminescent metal oxide nanoparticles having an average particle size of 1 to 50 nm; and a method of producing the same.

Abstract: A method of producing an ohmic contact to p-type silicon carbide comprising two layers, the first one comprising nickel silicide and the second one comprising titanium carbide is disclosed. The deposited layers are annealed to convert at least a part of deposited metals to nickel silicide and titanium carbide. The contact is formed by reaction between the metals and the semiconductor, and thus the in-situ simultaneous formation of metal silicide and carbide suppress the release of excess carbon at the contact interface. Noble metals may be deposited preferably in between titanium and nickel to improve the contact morphology.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: A method for selectively doping an organic semiconductor 1material in the region of a contact area 0.1formed between a contact and the organic semiconductor material disposed thereon includes introducing the dopant with the aid of nanoparticles, the nanoparticles being disposed in a manner adjoining the contact area and, as a result, only a very narrow region of the organic semiconductor material being doped. The field increase effected by the nanoparticles results in a further reduction of the contact resistance.

Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.

Abstract: Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a first (lower) electrode, sputter depositing a thin diffusion layer of a conductive material over the chalcogenide material, diffusing metal from the diffusion layer into the chalcogenide material resulting in a metal-comprising resistance variable material, and then plating a conductive material to a desired thickness to form a second (upper) electrode.

Abstract: The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

Abstract: An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.

Abstract: A nitride semiconductor laser device of high reliability such that the width of contact between a p-side ohmic electrode and a p-type contact layer is precisely controlled. The device comprises a substrate, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer. All the layers are formed in order on the substrate. A ridge part including the uppermost layer of the p-type nitride semiconductor layer of the p-type nitride semiconductor layer i.e., a p-type contact layer is formed in the p-type nitride semiconductor layer. A p-side ohmic electrode is formed on the p-type contact layer of the top of the ridge part. A first insulating film having an opening over the top of the ridge part covers the side of the ridge part and the portion near the side of the ridge part. The p-side ohmic electrode is in contact with the p-type contact layer through the opening. A second insulating film is formed on the first insulating film.

Abstract: A method of forming a silicide layer in contact with a silicon substrate. The method comprises forming the silicide layer by supplying a silicon-containing source that is different from the silicon substrate, such that the silicon in the silicide layer originates primarily from the silicon-containing source.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: A method for manufacturing III-nitride semiconductor devices is disclosed. The method employs oxidation and sulfurated treatment to reduce the specific contact resistance between metal and p-type III-nitride semiconductors. The method includes surface treatment of p-type III-nitride semiconductors using (NH4)2Sx solution to remove the native oxide from their surface; evaporating metal layer onto the surface-treated p-type III-nitride semiconductors; and then alloy processing the metals and the p-type III-nitride semiconductor with thermal alloy treatment. The method may further include a pre-oxidation step prior to the sulfurated treatment. In this way, ohmic contact can be formed between the metal layer and the p-type III-nitride semiconductors.

Abstract: A semiconductor device for generating spin-polarized conduction electrons including a ferromagnetic semiconductor layer and a non-magnetic semiconductor layer having a band alignment of Type II with respect to the ferromagnetic semiconductor, said ferromagnetic semiconductor layer and non-magnetic semiconductor layer being connected together directly or with interposing therebetween another non-magnetic semiconductor layer or energy barrier layer such that a spin splitting of a conduction band of the non-magnetic semiconductor layer is induced by a spontaneous spin splitting of a valence band of the ferromagnetic semiconductor layer, and spin-polarized conduction electrons are generated in the non-magnetic semiconductor layer by the spin splitting of the conduction band of the non-magnetic semiconductor layer.

Abstract: A production method of a GaN-based compound semiconductor having excellent crystallinity and a GaN-based semiconductor device produced therefrom. A discrete SiN buffer body is formed on a substrate, and a GaN buffer layer is formed thereon at low temperatures and a GaN semiconductor layer is then formed at high temperatures. By forming the discrete SiN buffer body, the crystal growth, which is dependent on the substrate, of the low-temperature buffer layer is inhibited and monocrystallization is promoted to generate seed crystals used at the time of growing the GaN buffer layer. Further, by forming SiO2 discretely between the substrate and the SiN buffer body or by forming InGaN or a superlattice layer on the GaN semiconductor layer, distortion of the GaN semiconductor layer is reduced.

Abstract: A composite semiconductor including silicon and compound semiconductor, and having a silicate layer for promoting layer-by-layer monocrystalline growth. Silicon may be introduced to react with the monocrystalline oxide layer to form the silicate layer. During the fabrication process, the thickness of the amorphous oxide layer may be increased by suitable methods, such as annealing or oxygen diffusion.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Mixed technology structures are provided in which a microprocessor is formed entirely in a monocrystalline compound semiconductor material layer overlying the silicon substrate.

Abstract: A method for preparing a barium fluorotitanate (BaTiF6) powder and depositing a barium titanate (BaTiO3) thin film on a silicon wafer is disclosed. The method includes steps of a) producing a barium fluorotitanate powder by mixing a hexafluorotitanic acid solution and a barium nitrate solution at a low temperature, b) dissolving the barium fluorotitanate powder into water and mixing with a boric acid solution, and c) immersing a silicon wafer into the mixture at a low temperature to grow a barium titanate thin film on the silicon wafer.

Abstract: Composite semiconductor structures and methods are provided for communications systems, specifically, those utilizing RF signals. Antenna switches, and amplifiers in receiver and transmitter sections of the communications systems are shown that are fabricated within a compound semiconductor layer of a composite semiconductor structure is integrated with support circuitry in a non-compound semiconductor substrate. Support circuitry that may be integrated include negative voltage generation circuitry, drain current protection circuitry, and voltage regulation circuitry.

Abstract: Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of a first conductive type formed in a part of a compound semiconductor substrate having a semi-insulating layer. The semiconductor laminated structure includes at least an active layer including a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed. A source electrode is formed on the semiconductor laminated structure, being electrically connected to the charge absorption layer.

Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, x+y≦1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A method of forming a self-aligned contact on a semiconductor includes forming a layer of a dielectric material over a semiconductor, providing a photoresist layer over the dielectric layer and then exposing the photoresist layer with a desired pattern and developing an opening in the photoresist layer. The dielectric material exposed through the photoresist layer opening is then removed to form a contact opening extending through the dielectric material to the semiconductor. The photoresist layer is then eroded so as to enlarge the size of the opening in the photoresist layer, whereby the dielectric material adjacent the contact opening is exposed through the enlarged opening of the photoresist layer. A barrier metal is then deposited in the enlarged opening of the photoresist layer and in the contact opening of the dielectric material, whereby the barrier metal overlies the exposed portion of the dielectric material. A conductive metal is then deposited atop the barrier metal.

Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.

Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1−x−yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1−x−yN layer or a p-type InxAlyGa1−x−yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1−x−yN layer while maintaining the crystallinity of the InxAlyGa1−x−yN layer.

Abstract: Devices and methods for fabricating wholly silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. In one variation, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, to form a graded implant. In other variations, the device epitaxial layers are 1) grown directly onto a semi-insulating substrate, 2) the semi-insulating epitaxial layer is grown onto a conducting substrate; 3) the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate; and 4) the subcollector is grown directly on a conducting substrate. Another variation comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another variation includes growth of layers using dopants other than nitrogent or aluminum.

Abstract: A II-VI semiconductor component is produced with an active layer sequence having at least one II-VI semiconductor layer containing Se and/or S on a substrate. First, an Se-free II-VI interlayer based on BeTe is grown epitaxially on the substrate in an essentially Se-free and S-free first epitaxy chamber. The active layer sequence is then grown epitaxially on the Se-free II-VI semiconductor layer.

Abstract: A II-VI semiconductor device includes a stack of semiconductor layers. An ohmic contact is provided that electrically couples to the stack. The ohmic contact has an oxidation rate when exposed to an oxidizing substance. A passivation capping layer overlies the ohmic contact and has an oxidation rate that is less than the oxidation rate of the ohmic contact.

Abstract: The invention provides a method of fabricating a wafer including growing a single crystal layer comprising a III-V compound in a first chamber at a temperature above 350° C. A temperature of a surface of the single crystal layer is reduced to below about 350° C. in the first chamber. An indium arsenide layer is deposited on the single crystal layer, to form an intermediate structure, in the first chamber at a temperature below 350° C. and above 100° C. The intermediate structure is transferred to a second chamber. A surface of the intermediate structure is heated to a temperature above about 600° C. to remove substantially all of the indium arsenide layer and impurities collected in the indium arsenide layer during the transfer to the second chamber. Another material is deposited on the single crystal layer in the second chamber.

Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.

Abstract: A semiconductor device has a substrate body, an AlxGayInzN (x+y+z=1,x,y,z≧0) film epitaxially grown direct on the substrate body or epitaxially grown via a buffer layer on the substrate body, and a metal film provided on the rear surface of the substrate body. In the case of the manufacturing the semiconductor device, the substrate body is heated, by a heater, uniformly and efficiently through the thermal radiation of the heater.

Abstract: The subject invention pertains to a method and device for producing large area single crystalline III-V nitride compound semiconductor substrates with a composition AlxInyGa1-x-y N (where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1). In a specific embodiment, GaN substrates, with low dislocation densities (˜107 cm2) can be produced. These crystalline III-V substrates can be used to fabricate lasers and transistors. Large area free standing single crystals of III-V compounds, for example GaN, can be produced in accordance with the subject invention. By utilizing the rapid growth rates afforded by hydride vapor phase epitaxy (HVPE) and growing on lattice matching orthorhombic structure oxide substrates, good quality III-V crystals can be grown. Examples of oxide substrates include LiGaO2, LiAlO2, MgAlScO4, Al2MgO4, and LiNdO2. The subject invention relates to a method and apparatus, for the deposition of III-V compounds, which can alternate between MOVPE and HVPE, combining the advantages of both.

Abstract: In a semiconductor light-emitting device, on an n-GaAs substrate are stacked an n-GaAs buffer layer, an n-cladding layer, an undoped active layer, a p-cladding layer, a p-intermediate band gap layer and a p-current diffusion layer. Further, a first electrode is formed under the n-GaAs substrate, and a second electrode is formed on the grown-layer side. In this process, a region of the p-intermediate band gap layer just under the second electrode is removed, the p-current diffusion layer is stacked in the removal region on the p-cladding layer, and a junction plane of the p-current diffusion layer and the p-cladding layer becomes high in resistance due to an energy band structure of type II. This semiconductor light-emitting device is capable of reducing ineffective currents with a simple construction and taking out light effectively to outside, thus enhancing the emission intensity.

Abstract: A polycrystalline semiconductor material containing Si, Ge or SiGe, wherein the material contains H atoms and the number of monohydride structures of couplings between Si or Ge, and H is larger than the number of higher-order hydride structures, or in other words, a peak intensity of a monohydride structure in a local vibration mode measured by a Raman spectral analysis is higher than a peak intensity of a higher-order hydride structure. By configuring the compositions of a polycrystalline semiconductor material in the above manner, the carrier mobility can be made high.

Abstract: A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.

Abstract: A method of fabricating on ohmic metal electrode. The p-type ohmic metal electrode according to the present invention employs Ru and RuOx as the cover layer in lieu of conventional Au, in order to effectively prevent penetration by contaminants in the air, such as oxygen, carbon, and H2O, and to form a stable metal-Ga intermetallic phase at the junction between the contact layer and the nitride compound semiconductor. The n-type ohmic metal electrode according to the present invention employs Ru as the diffusion barrier in lieu of conventional Ni or Pt, in order to effectively form a metal-nitride phase such as titanium nitride that contributes to superior ohmic characteristics during the heating process, without destruction of the junction. According to the present invention, it is possible to fabricate devices having superior electrical, optical, and thermal characteristics compared with conventional devices.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2 O3 can be used.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: A semiconductor device for generating spin-polarized conduction electrons including a ferromagnetic semiconductor layer and a non-magnetic semiconductor layer having a band alignment of Type II with respect to the ferromagnetic semiconductor, said ferromagnetic semiconductor layer and non-magnetic semiconductor layer being connected together directly or with interposing therebetween another non-magnetic semiconductor layer or energy barrier layer such that a spin splitting of a conduction band of the non-magnetic semiconductor layer is induced by a spontaneous spin splitting of a valence band of the ferromagnetic semiconductor layer, and spin-polarized conduction electrons are generated in the non-magnetic semiconductor layer by the spin splitting of the conduction band of the non-magnetic semiconductor layer.