To Compound Semiconductor Patents (Class 438/602)
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Patent number: 8652949Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.Type: GrantFiled: August 5, 2011Date of Patent: February 18, 2014Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 8623752Abstract: An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.Type: GrantFiled: August 13, 2007Date of Patent: January 7, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Hideto Tamaso
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Patent number: 8563088Abstract: A method for preparing a Group 1a-1b-3a-6a material using a selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.Type: GrantFiled: October 12, 2012Date of Patent: October 22, 2013Assignee: Rohm and Haas Electronic Materials LLCInventors: Kevin Calzia, David Mosley, David L. Thorsen, Charles R. Szmanda
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Patent number: 8564129Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.Type: GrantFiled: August 3, 2012Date of Patent: October 22, 2013Assignee: Phononic Devices, Inc.Inventors: Robert Joseph Therrien, Jason D. Reed, Jaime A. Rumsey, Allen L. Gray
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Patent number: 8519482Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.Type: GrantFiled: September 28, 2011Date of Patent: August 27, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Hong Yu, Huang Liu
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Patent number: 8507364Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.Type: GrantFiled: May 20, 2009Date of Patent: August 13, 2013Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka UniversityInventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
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Publication number: 20130143398Abstract: A method for manufacturing a MOSFET includes the steps of: preparing a substrate made of silicon carbide; forming a drain electrode making ohmic contact with the substrate; and forming a backside pad electrode on and in contact with the drain electrode. The drain electrode formed in the step of forming the drain electrode is made of an alloy containing Ti and Si. Further, the backside pad electrode formed is maintained at a temperature of 300° C. or smaller until completion of the MOSFET. Accordingly, the manufacturing process can be efficient while achieving excellent adhesion between the electrodes.Type: ApplicationFiled: September 11, 2012Publication date: June 6, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hiroyuki Kitabayashi, Hideto Tamaso, Taku Horii
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Patent number: 8450122Abstract: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.Type: GrantFiled: June 2, 2010Date of Patent: May 28, 2013Assignee: Infineon Technologies AGInventor: Sajan Marokkey
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Patent number: 8450826Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first electrode ohmic-contacting the semiconductor layer; a ohmic contact unit ohmic-contacting the semiconductor layer and spaced apart from the first electrode; and a schottky contact unit schottky-contacting the semiconductor layer and covering the ohmic contact unit.Type: GrantFiled: March 16, 2011Date of Patent: May 28, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Younghwan Park, Kiyeol Park, Woochul Jeon
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Patent number: 8415241Abstract: A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.Type: GrantFiled: January 12, 2012Date of Patent: April 9, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Shunsuke Yamada
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Publication number: 20130082307Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.Type: ApplicationFiled: July 16, 2012Publication date: April 4, 2013Applicant: FUJITSU LIMITEDInventors: Naoya OKAMOTO, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
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Publication number: 20130072010Abstract: A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer.Type: ApplicationFiled: September 28, 2012Publication date: March 21, 2013Applicant: NICHIA CORPORATIONInventors: Kentaro WATANABE, Shunsuke MINATO, Giichi MARUTSUKI
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Patent number: 8395184Abstract: A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.Type: GrantFiled: June 6, 2012Date of Patent: March 12, 2013Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Masaaki Sakuta
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Patent number: 8383499Abstract: A method for forming a gallium nitride based semiconductor diode includes forming Schottky contacts on the upper surface of mesas formed in a semiconductor body formed on a substrate. Ohmic contacts are formed on the lower surface of the semiconductor body. In one embodiment, an insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and ohmic contacts to form the anode and cathode electrodes. In another embodiment, vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the ohmic contacts. An anode electrode is formed in electrical contact with the Schottky contacts. A cathode electrode is formed in electrical contact with the ohmic contacts on the backside of the substrate.Type: GrantFiled: July 19, 2012Date of Patent: February 26, 2013Assignee: Alpha and Omega Semiconductor IncorporatedInventor: TingGang Zhu
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Patent number: 8309179Abstract: A selenium/Group 1b ink comprising, as initial components: a selenium component comprising selenium, an organic chalcogenide component having a formula selected from RZ—Z?R? and R2—SH, a Group 1b component and a liquid carrier; wherein Z and Z? are each independently selected from sulfur, selenium and tellurium; wherein R is selected from H, C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; wherein R? and R2 are selected from a C1-20 alkyl group, a C6-20 aryl group, a C1-20 alkylhydroxy group, an arylether group and an alkylether group; and wherein the selenium/Group 1b ink is a stable dispersion.Type: GrantFiled: September 28, 2009Date of Patent: November 13, 2012Assignee: Rohm and Haas Electronics Materials LLCInventors: Kevin Calzia, David W. Mosley, Charles R. Szmanda, David L. Thorsen
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Patent number: 8310028Abstract: A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film.Type: GrantFiled: January 9, 2009Date of Patent: November 13, 2012Assignee: Rohm Co., Ltd.Inventors: Tatsuya Kiriyama, Noriaki Kawamoto
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Patent number: 8288198Abstract: A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C. with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.Type: GrantFiled: March 12, 2007Date of Patent: October 16, 2012Assignee: Advanced Technology Materials, Inc.Inventors: Jeffrey F. Roeder, Thomas H. Baum, Bryan C. Hendrix, Gregory T. Stauf, Chongying Xu, William Hunks, Tianniu Chen, Matthias Stender
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Patent number: 8282995Abstract: A selenium/Group Ib/Group 3a ink is provided, comprising, as initial components: (a) a selenium/Group Ib/Group 3a system which comprises a combination of, as initial components: a selenium; an organic chalcogenide component; a Group Ib containing substance; optionally, a bidentate thiol component; a Group 3a containing substance; and, (b) a liquid carrier component; wherein the selenium/Group Ib/Group 3a system is stably dispersed in the liquid carrier component. Also provided are methods of preparing the selenium/Group Ib/Group 3a ink and for using the selenium/Group Ib/Group 3a ink to deposit a selenium/Group Ib/Group 3a material on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photoresponsive devices (e.g., electrophotography (e.g.Type: GrantFiled: September 30, 2010Date of Patent: October 9, 2012Assignee: Rohm and Haas Electronic Materials LLCInventors: Kevin Calzia, David Mosley, David L. Thorsen
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Patent number: 8277894Abstract: A selenium ink comprising selenium stably dispersed in a liquid medium is provided, wherein the selenium ink is hydrazine free and hydrazinium free. Also provided are methods of preparing the selenium ink and of using the selenium ink to deposit selenium on a substrate for use in the manufacture of a variety of chalcogenide containing semiconductor materials, such as, thin film transistors (TFTs), light emitting diodes (LEDs); and photo responsive devices (e.g., electrophotography (e.g., laser printers and copiers), rectifiers, photographic exposure meters and photo voltaic cells) and chalcogenide containing phase change memory materials.Type: GrantFiled: July 16, 2009Date of Patent: October 2, 2012Assignee: Rohm and Haas Electronic Materials LLCInventors: David Mosley, Kevin Calzia
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Publication number: 20120238090Abstract: One object of the present invention is to provide a method for producing a thick film metal electrode that is able to form a positive-negative reverse type resist, which has a thickness of 7 ?m or more and excellent in-plane uniformity, on the circuit element formed on the silicon carbide substrate, and a method for producing a thick film resist, and the present invention provides a method for producing a thick film resist wherein a first positive-negative reverse type resist having a first viscosity is formed on an upper surface of a circuit element layer which is treated with HMDS, and a second positive-negative reverse type resist having a second viscosity, which is larger than the first viscosity, on the first positive-negative reverse type resist such that a total thickness of the first and second positive-negative reverse type resists constituting a thick film resist be 7 ?m or more.Type: ApplicationFiled: March 9, 2012Publication date: September 20, 2012Applicant: SHOWA DENKO K.K.Inventor: Kenji SUZUKI
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Patent number: 8247905Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.Type: GrantFiled: August 10, 2009Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
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Patent number: 8216929Abstract: In a method of manufacturing a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and having first and second opposing surfaces is prepared. The second surface of the semiconductor substrate is processed so that a surface roughness of the second surface is less than or equal to 10 nm and a value of (100%-reflectance-transmittance) at a wavelength of a laser light is greater than or equal to 80%. A metal layer is formed on the second surface of the semiconductor substrate after the processing the second surface. The metal layer is irradiated with the laser light and thereby an ohmic electrode is formed on the second surface.Type: GrantFiled: September 9, 2010Date of Patent: July 10, 2012Assignee: DENSO CORPORATIONInventors: Jun Kawai, Kazuhiro Tsuruta
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Patent number: 8212261Abstract: A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film.Type: GrantFiled: May 13, 2008Date of Patent: July 3, 2012Assignee: DENSO CORPORATIONInventors: Hiroyuki Ichikawa, Hideki Kawahara, Hiroki Nakamura
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Patent number: 8207054Abstract: A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film 2? with mesh structure in which micro voids are provided on a starting substrate 1, and growing a III group nitride semiconductor crystal layer 3 via the metal film or metal nitride film 2?.Type: GrantFiled: July 30, 2009Date of Patent: June 26, 2012Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
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Patent number: 8202794Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.Type: GrantFiled: April 5, 2011Date of Patent: June 19, 2012Assignee: Oki Electric Industry Co., Ltd.Inventors: Juro Mita, Katsuaki Kaifu
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Publication number: 20120132927Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1?x?y)Si(s)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.Type: ApplicationFiled: August 4, 2010Publication date: May 31, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Akinori Seki, Masahiro Sugimoto, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
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Patent number: 8176566Abstract: An information distribution device including a storage section, a reception section, a selection section and a distribution section. The storage section stores, for each of predetermined distribution destinations, at least one set of output destination information representing predetermined output destinations, and security level information associated with each set of output destination information. The reception section receives electronic information and distribution destination information which represents a distribution destination of the electronic information. The selection section reads from the storage section the output destination information and security level information that correspond to the distribution destination represented by the received distribution destination information, and selects an output destination of the electronic information on the basis of the security level information. The distribution section distributes the electronic information to the selected output destination.Type: GrantFiled: March 28, 2007Date of Patent: May 8, 2012Assignee: Fuji Xerox Co., Ltd.Inventor: Yoshiaki Hatano
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Publication number: 20120098054Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.Type: ApplicationFiled: January 3, 2012Publication date: April 26, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matthew T. Currie, Richard Hammond
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Patent number: 8158496Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.Type: GrantFiled: September 9, 2010Date of Patent: April 17, 2012Assignee: Siltron Inc.Inventors: Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ji-Hoon Kim
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Patent number: 8158501Abstract: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.Type: GrantFiled: December 14, 2010Date of Patent: April 17, 2012Assignee: Siltron, Inc.Inventors: Yong-Jin Kim, Doo-Soo Kim, Ho-Jun Lee, Dong-Kun Lee
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Patent number: 8133806Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: GrantFiled: September 30, 2010Date of Patent: March 13, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Christiaan J. Werkhoven
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Patent number: 8093618Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.Type: GrantFiled: October 11, 2007Date of Patent: January 10, 2012Assignees: Seoul Opto Device Co., Ltd., Postech Academy-Industry FoundationInventors: Jong Lam Lee, Sang Han Lee
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Patent number: 8093139Abstract: The present invention describes a method of fabrication of nanocomposite semiconductor materials comprising aligned arrays of metal or semiconductor nanowires incorporated into semiconductor material for application in various electronic, optoelectronic, photonic and plasmonic devices employing self-assembling of the nanowires under light illumination from charged interstitial defect atoms, which are either inherently present in the semiconductor material or artificially introduced in the matrix semiconductor material.Type: GrantFiled: December 11, 2008Date of Patent: January 10, 2012Assignees: Anteos, Inc., Altair Center, LLCInventor: Sergei Krivoshlykov
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Publication number: 20110287626Abstract: The invention provides an ohmic electrode of a p-type SiC semiconductor element, which includes an ohmic electrode layer that is made of Ti3SiC2, and that is formed directly on a surface of a p-type SiC semiconductor. The invention also provides a method of forming an ohmic electrode of a p-type SiC semiconductor element. The ohmic electrode includes an ohmic electrode layer that is made of Ti3SiC2, and that is formed directly on a surface of a p-type SiC semiconductor. The method includes forming a ternary mixed film that includes Ti, Si, and C in a manner such that an atomic composition ratio, Ti:Si:C is 3:1:2, on a surface of a p-type SiC semiconductor to produce a laminated film; and annealing the produced laminated film under vacuum or under an inert gas atmosphere.Type: ApplicationFiled: January 29, 2010Publication date: November 24, 2011Inventors: Akinori Seki, Masahiro Sugimoto, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
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Patent number: 8030665Abstract: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are laminated to form a stack of nitride semiconductor on the first face of the substrate 1. A first bonding layer including more than one metal layer is formed on the p-type nitride semiconductor layer 8. A supporting substrate having a first and second face has a thermal expansion coefficient that is larger than that of the nitride semiconductor and is equal or smaller than that of the substrate 1 for growing nitride semiconductor. A second bonding layer including more than one metal layer is formed on the first face of the supporting substrate. The first bonding layer 9 and the second bonding layer 11 are faced with each other and, then, pressed with heat to bond together.Type: GrantFiled: April 30, 2008Date of Patent: October 4, 2011Assignee: Nichia CorporationInventors: Shinichi Nagahama, Masahiko Sano, Tomoya Yanamoto, Keiji Sakamoto, Masashi Yamamoto, Daisuke Morita
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Publication number: 20110233560Abstract: An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal.Type: ApplicationFiled: March 16, 2011Publication date: September 29, 2011Applicant: Advanced Interconnect Materials, LLCInventors: Junichi Koike, Akihiro Shibatomi, Kunhwa Jung, Yuji Sutou
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Patent number: 8021950Abstract: Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g.Type: GrantFiled: October 26, 2010Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, John J. Ellis-Monaghan, Jeffrey P. Gambino, Tom C. Lee
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Patent number: 8012783Abstract: The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. The semiconductor element of the present invention has an n-type Gallium nitride based compound semiconductor and an electrode that forms an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferable embodiment, the above-mentioned electrode can also serve as a contact electrode. According to a preferable embodiment, the above-mentioned electrode is superior in the heat resistance. Moreover, a production method of the semiconductor element is also provided.Type: GrantFiled: April 4, 2006Date of Patent: September 6, 2011Assignee: Mitsubishi Chemical CorporationInventors: Tsuyoshi Takano, Takahide Joichi, Hiroaki Okagawa
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Patent number: 8012864Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.Type: GrantFiled: September 25, 2008Date of Patent: September 6, 2011Assignee: Seiko Epson CorporationInventors: Haruki Ito, Nobuaki Hashimoto
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Patent number: 8008180Abstract: A method of forming an Ohmic contact on a P-type 4H—SiC and an Ohmic contact formed by the same are provided. A method of forming an Ohmic contact on a P-type 4H—SiC substrate including a deposition step of successively depositing a 1 to 60 nm thick first Al layer, Ti layer, and second Al layer on a P-type 4H—SiC substrate and an alloying step of forming an alloy layer between the SiC substrate and the Ti layer through the first Al layer by heat treatment in a nonoxidizing atmosphere. An Ohmic contact on a P-type 4H—SiC substrate formed by this method is also provided.Type: GrantFiled: March 13, 2008Date of Patent: August 30, 2011Assignees: Toyota Jidosha Kabushiki Kaisha, Osaka UniversityInventors: Yasuo Takahashi, Masakatsu Maeda, Akinori Seki, Akira Kawahashi, Masahiro Sugimoto
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Patent number: 8004077Abstract: A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals.Type: GrantFiled: November 17, 2010Date of Patent: August 23, 2011Assignee: Seiko Epson CorporationInventors: Haruki Ito, Nobuaki Hashimoto
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Patent number: 8003510Abstract: Fabrication methods for nano-scale chalcopyritic powders and polymeric thin-film solar cells are presented. The fabrication method for nano-scale chalcopyritic powders includes providing a solution consisting of group IB, IIIA, VIA elements on the chemistry periodic table or combinations thereof. The solution is heated by a microwave generator. The solution is washed and filtered by a washing agent. The solution is subsequently dried, thereby acquiring nano-scale chalcopyritic powders.Type: GrantFiled: April 26, 2008Date of Patent: August 23, 2011Assignee: Industrial Technology Research InstituteInventors: Yu Huang, Bing-Joe Hwang, Hsuan-Fu Wang, Chih-Chung Wu, Shih-Hong Chang
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Patent number: 7993948Abstract: A method for fabricating an electrode by (i) depositing a palladium film on a p-type semiconductor layer; (ii) introducing an oxygen gas onto the palladium film to provide an oxygen ambient; (iii) oxidizing the palladium film adjacent to the semiconductor layer by annealing the palladium film in the oxygen ambient; and (iv) forming a palladium oxide film directly in contact with the semiconductor layer.Type: GrantFiled: August 11, 2009Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Saito, Shinya Nunoue, Toshiyuki Oka
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Publication number: 20110092063Abstract: In a method of manufacturing a silicon carbide semiconductor device, a semiconductor substrate made of silicon carbide and having first and second opposing surfaces is prepared. The second surface of the semiconductor substrate is processed so that a surface roughness of the second surface is less than or equal to 10 nm and a value of (100%-reflectance-transmittance) at a wavelength of a laser light is greater than or equal to 80%. A metal layer is formed on the second surface of the semiconductor substrate after the processing the second surface. The metal layer is irradiated with the laser light and thereby an ohmic electrode is formed on the second surface.Type: ApplicationFiled: September 9, 2010Publication date: April 21, 2011Applicant: DENSO CORPORATIONInventors: Jun Kawai, Kazuhiro Tsuruta
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Patent number: 7921550Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.Type: GrantFiled: December 29, 2008Date of Patent: April 12, 2011Assignee: Unimicron Technology Corp.Inventor: Cheng-Po Yu
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Patent number: 7897490Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.Type: GrantFiled: November 30, 2006Date of Patent: March 1, 2011Assignee: Kyma Technologies, Inc.Inventors: Edward A. Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
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Patent number: 7875470Abstract: A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al2O3) substrate in a reaction chamber; introducing a nitrogen source gas into a reaction chamber; and annealing the substrate in a state where the nitrogen source gas is introduced into the reaction chamber, to form an AIN compound layer on the substrate. The AIN compound layer having intermediate properties between those of the substrate and a semiconductor layer is formed between the substrate and the semiconductor layer. Thus, an interface space between the AIN compound layer and the buffer layer or the semiconductor layer that is to be formed on the AIN compound layer becomes smaller and a crystal stress also becomes smaller, thereby reducing a crack that may be generated due to differences in lattice constant and thermal expansion coefficient between the substrate and the semiconductor layer.Type: GrantFiled: March 9, 2007Date of Patent: January 25, 2011Assignee: Seoul Opto Device Co., Ltd.Inventor: Hyun Kyu Park
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Patent number: 7875545Abstract: A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.Type: GrantFiled: January 28, 2008Date of Patent: January 25, 2011Assignee: Cree, Inc.Inventors: Allan Ward, III, Jason Patrick Henning, Helmut Hagleitner, Keith Dennis Wieber
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Patent number: 7863178Abstract: The present invention relates to an AlGaInN based optical device fabricated by a new p-type AlGaInN:Mg growth method and method for manufacturing the same, including a p-type nitride semiconductor layer that is grown using both NH3 and a hydrazine based source as a nitrogen precursor, thereby an additional subsequent annealing process for extracting hydrogen is not necessary and thus the process is simple and an active layer can be prevented from being thermally damaged by subsequent annealing.Type: GrantFiled: August 21, 2004Date of Patent: January 4, 2011Assignees: Epivalley Co., Ltd., Samsung LED Co., Ltd.Inventors: Tae-Kyung Yoo, Joong Seo Park, Eun Hyun Park
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Patent number: 7851343Abstract: A method of forming an ohmic layer for a semiconductor device includes forming a metal layer on a Silicon Carbide (SiC) layer and forming an ablation capping layer on the metal layer. Laser light is impinged through the ablation capping layer to form a metal-SiC material.Type: GrantFiled: June 14, 2007Date of Patent: December 14, 2010Assignee: Cree, Inc.Inventors: Eric Mayer, Marc Alberti