Abstract: A high electron mobility transistor comprises a GaN-based electron accumulation layer formed on a substrate, an electron supply layer formed on the electron accumulation layer, a source electrode and a drain electrode formed on the electron supply layer and spaced from each other, a gate electrode formed on the electron supply layer between the source and drain electrodes, and a hole absorption electrode formed on the electron accumulation layer so as to be substantially spaced from the electron supply layer. Since the hole absorption electrode is formed on the electron absorption layer in order to prevent holes generated by impact ionization from being accumulated on the electron accumulation layer, a kink phenomenon is prevented. Good drain-current/voltage characteristics are therefore obtained. A high power/high electron mobility transistor is provided with a high power-added efficiency and good linearity.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: A semiconductor configuration with ohmic contact-connection includes a first and a second semiconductor region made of silicon carbide, each having a different conduction type. A first and a second contact region serve for contact-connection. The first contact region and the second contact region have an at least approximately identical material composition which is practically homogeneous within the respective contact region. A method is provided for contact-connecting n-conducting and p-conducting silicon carbide, in each case with at least approximately identical material.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A semi-insulating bulk single crystal of silicon carbide is disclosed that has a resistivity of at least 5000 &OHgr;-cm at room temperature and a concentration of deep level trapping elements that is below the amounts that will affect the resistivity of the crystal, preferably below detectable levels. A method of forming the crystal is also disclosed, along with some resulting devices that take advantage of the microwave frequency capabilities of devices formed using substrates according to the invention.

Abstract: A first surface layer made of compound semiconductor material is defined in a surface area of a substrate. A first intermediate layer is formed on the surface layer, the first intermediate layer being made of compound material having Ga as a III group element and S as a VI element and having a thickness of at least two monolayers or thicker. A first electrode is formed on the first intermediate layer, being electrically connected to the first surface layer with an ohmic contact.

Abstract: As will be described in more detail hereinafter, there is disclosed herein a titanium nitride diffusion barrier layer and associated method for use in non-silicon semiconductor technologies. In one aspect of the invention, a semiconductor device includes a non-silicon active surface. The improvement comprises an ohmic contact serving to form an external electrical connection to the non-silicon active surface in which the ohmic contact includes at least one layer consisting essentially of titanium nitride. In another aspect of the invention, a semiconductor ridge waveguide laser is disclosed which includes a semiconductor substrate and an active layer disposed on the substrate. A cladding layer is supported partially on the substrate and partially on the active layer. The cladding layer includes a ridge portion disposed in a confronting relationship with the active region.

Abstract: A method for making electrical contacts and junctions in silicon carbide that concurrently incorporates and activates dopants from a gaseous ambient. The low temperature processing of the present invention prevents the formation of crystalline defects during annealing and preserves the quantitative chemical properties of the silicon carbide. Improved activation of dopants incorporated in a silicon carbide sample is provided for making the electrical contacts and junctions.

Abstract: Metallic osmium on SiC (either .beta. or .alpha.) forms a contact that remains firmly attached to the SiC surface and forms an effective barrier against diffusion from the conductive metal. On n-type SiC, Os forms an abrupt Schottky rectifying junction having essentially unchanged operating characteristics to at least 1050.degree. C. and Schottky diodes that remain operable to 1175.degree. C. and a barrier height over 1.5 ev. On p-type SiC, Os forms an ohmic contact with specific contact resistance of <10.sup.-4 ohm-cm.sup.2. Ohmic and rectifying contacts to a TiC layer on a SiC substrate are formed by depositing a WC layer over the TiC layer, followed by a metallic W layer. Such contacts are stable to at least 1150.degree. C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer.

Abstract: A method and an apparatus of fabricating a metal interconnection in a contact hole of a semiconductor device reduces contact resistance and improves step coverage. A contact hole is opened in an interlayer insulating film formed on a semiconductor substrate. A conductive layer used as an ohmic contact layer is formed on the interlayer insulating film including the contact hole. An upper surface of the conductive layer is nitrided to form a protective layer. An ALD (atomic layer deposition)-metal barrier layer is formed on the protective layer. The resulting metal barrier layer has good step coverage and no impurities, and the protective layer prevents defects in the conductive layer caused by precursor impurities used during the formation of the metal barrier layer.

Abstract: Methods of forming a film on a substrate using chemical vapor deposition techniques and pyrazolyl complexes. The complexes and methods are particularly suitable for the preparation of semiconductor structures.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.

Abstract: The invention uses hydrogen ambient atmosphere to directly form PdGe contacts on Group III-V materials. Specific GaAs HBT's have been formed in a 100% H.sub.2 ambient, and demonstrate low etch reactivity attributable to the significant incorporation of hydrogen. The LP-MOCVD method used to demonstrate the invention produced a specific contact resistivity of less than 1.times.10.sup.-7 .OMEGA.-cm-.sup.-2, at preferred conditions of a 100% hydrogen ambient, 300.degree. C., and 15 minute reaction time. This is believed to be the lowest known resistance of any alloy method employed for PdGe on GaAs. Equally significant, the contacts demonstrate increased durability during etching.

Abstract: A GaN group compound semiconductor device includes an electrode structure provided on a p-GaN group compound semiconductor layer, the electrode structure including: a first layer formed on the p-GaN group compound semiconductor layer, the first layer including a compound including a first metal element and Ga; and a second layer formed on the first layer, the second layer including the first metal element. The first layer contains substantially no nitrogen.

Abstract: A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.

Abstract: In a method of producing an ohmic contact (5) to a p-type .alpha.-SiC layer (3b) in a semiconductor device (1), layers of aluminium, titanium and silicon are deposited on said .alpha.-SiC layer (3b), and said deposited layers (5) are annealed to convert at least part of said deposited layers (5) to aluminium-titanium-silicide.

Abstract: It is intended to realize an ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics. Provided on an n.sup.+ -type GaAs substrate is an ohmic electrode in which an n.sup.++ -type regrown GaAs layer regrown from the n.sup.+ -type GaAs substrate and a NiGe film containing precipitates composed of .alpha.'-AuGa are sequentially stacked. The ohmic electrode may be fabricated by sequentially stacking a Ni film, Au film and Ge film on the n.sup.+ -type GaAs substrate, then patterning these films by, for example, lift-off, and thereafter annealing the structure at a temperature of 400.about.750.degree. C. for several seconds to several minutes.

Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A semiconductor device having an ohmic electrode having a satisfactory ohmic contact to an n-type GaAs can be obtained by heat treatment at low temperature. A method of manufacturing the semiconductor device having the ohmic electrode includes two processes. In the first process, a metal layer containing Ni, Sn and AuGe is formed on one main surface of the n-type GaAs. In the second process, the n-type GaAs is subjected to a heat treatment at a temperature which is equal to or higher than 190 C. and equal to or lower than 300 C. Thus, the ohmic electrode is formed on the one main surface of the n-type GaAs.

Abstract: A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising:depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance;depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; anddepositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: It has been identified that a known loss mechanism in the access path to a mesa type device is more significant than previously believed. The source of the loss is due to the electromagnetic interaction of the wire bond and the device side wall which induces an image current at the side wall along the path of the wire bond. According to the teachings of the present invention, a process for forming a conductive coating on a semiconductor device is disclosed. The coating reduces high frequency losses associated with the device. The processes disclosed are compatible with existing semiconductor fabrication devices and advantageously provide improved uniformity and repeatability.

Abstract: In a method of producing an ohmic contact to a p-type .alpha.-SiC layer in a semiconductor device, layers of aluminum, titanium and silicon are deposited on the .alpha.-SiC layer, and the deposited layers are annealed to convert at least a part of the deposited layers to aluminum-titanium-silicide.

Abstract: After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.

Abstract: A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.