Iii-v Compound Semiconductor Patents (Class 438/604)
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Patent number: 8253221Abstract: A gallium nitride crystal with a polyhedron shape having exposed {10-10} m-planes and an exposed (000-1) N-polar c-plane, wherein a surface area of the exposed (000-1) N-polar c-plane is more than 10 mm2 and a total surface area of the exposed {10-10} m-planes is larger than half of the surface area of (000-1) N-polar c-plane. The GaN bulk crystals were grown by an ammonothermal method with a higher temperature and temperature difference than is used conventionally, and using an autoclave having a high-pressure vessel with an upper region and a lower region. The temperature of the lower region of the high-pressure vessel is at or above 550° C., the temperature of the upper region of the high-pressure vessel is set at or above 500° C., and the temperature difference between the lower and upper regions is maintained at or above 30° C. GaN seed crystals having a longest dimension along the c-axis and exposed large area m-planes are used.Type: GrantFiled: September 19, 2008Date of Patent: August 28, 2012Assignee: The Regents of the University of CaliforniaInventors: Tadao Hashimoto, Shuji Nakamura
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Patent number: 8252662Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.Type: GrantFiled: March 29, 2010Date of Patent: August 28, 2012Assignee: Soraa, Inc.Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
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Patent number: 8242540Abstract: A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.Type: GrantFiled: June 11, 2010Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Cheng-Hsien Wu
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Publication number: 20120193687Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: Jeehwan Kim, Jin-Hong Park, Devendra Sadana, Kuen-Ting Shiu
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Patent number: 8227898Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.Type: GrantFiled: July 14, 2010Date of Patent: July 24, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinji Tokuyama, Masahiro Adachi, Takashi Kyono, Yoshihiro Saito
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Patent number: 8211760Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.Type: GrantFiled: April 12, 2011Date of Patent: July 3, 2012Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.Inventors: Nathan Ray Perkins, Timothy Arthur Valade, Albert William Wang
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Patent number: 8207054Abstract: A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film 2? with mesh structure in which micro voids are provided on a starting substrate 1, and growing a III group nitride semiconductor crystal layer 3 via the metal film or metal nitride film 2?.Type: GrantFiled: July 30, 2009Date of Patent: June 26, 2012Assignee: Hitachi Cable, Ltd.Inventor: Masatomo Shibata
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Publication number: 20120153297Abstract: Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.Type: ApplicationFiled: August 1, 2011Publication date: June 21, 2012Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Chia-Lin Hsiung, You-Da Lin, Hiroaki Ohta, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8202794Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.Type: GrantFiled: April 5, 2011Date of Patent: June 19, 2012Assignee: Oki Electric Industry Co., Ltd.Inventors: Juro Mita, Katsuaki Kaifu
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Patent number: 8202793Abstract: In a method for making an inclusion-free uniformly semi-insulating GaN crystal, an epitaxial nitride layer is deposited on a substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode, wherein a surface of the nucleation layer is substantially covered with pits and the aspect ratio of the pits is essentially the same. A GaN transitional layer is grown on the nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. After growing the transitional layer, a surface of the transitional layer is substantially pit-free. A bulk GaN layer is grown on the transitional layer by HVPE. After growing the bulk layer, a surface of the bulk layer is smooth and substantially pit-free. The GaN is doped with a transition metal during at least one of the foregoing GaN growth steps.Type: GrantFiled: August 12, 2010Date of Patent: June 19, 2012Assignee: Kyma Technologies, Inc.Inventors: Edward A. Preble, Denis Tsvetkov, Andrew D. Hanser, N. Mark Williams, Xueping Xu
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Patent number: 8183134Abstract: Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.Type: GrantFiled: January 19, 2011Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 8178372Abstract: A method for production of a plurality of semiconductor chips (6) in a wafer composite. A semiconductor layer sequence (2) is grown on a growth substrate (1), metallization (3) is applied to the semiconductor layer sequence (2), a metal layer (4) is electrochemically deposited onto the metallization (3), and the semiconductor layer sequence (2) is then structured and separated to form individual semiconductor chips (6). The electrochemically applied metal layer (4) is particularly suitable for use as a heat spreader, for dissipation of the heat produced by the semiconductor chips (6).Type: GrantFiled: September 28, 2006Date of Patent: May 15, 2012Assignee: OSRAM Opto Semiconductors GmbHInventors: Stephan Lutgen, Tony Albrecht, Wolfgang Reill
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Publication number: 20120098132Abstract: A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.Type: ApplicationFiled: October 24, 2011Publication date: April 26, 2012Applicant: Hynix Semiconductor Inc.Inventors: Cheol Hwan PARK, Ho Jin Cho, Dong Kyun Lee
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Patent number: 8158490Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.Type: GrantFiled: March 30, 2010Date of Patent: April 17, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Umemura, Masahiro Ohashi
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Patent number: 8158496Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.Type: GrantFiled: September 9, 2010Date of Patent: April 17, 2012Assignee: Siltron Inc.Inventors: Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ji-Hoon Kim
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Patent number: 8158501Abstract: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.Type: GrantFiled: December 14, 2010Date of Patent: April 17, 2012Assignee: Siltron, Inc.Inventors: Yong-Jin Kim, Doo-Soo Kim, Ho-Jun Lee, Dong-Kun Lee
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Patent number: 8153515Abstract: A nitride based heterojunction transistor includes a substrate and a first Group III nitride layer, such as an AlGaN based layer, on the substrate. The first Group III-nitride based layer has an associated first strain. A second Group III-nitride based layer, such as a GaN based layer, is on the first Group III-nitride based layer. The second Group III-nitride based layer has a bandgap that is less than a bandgap of the first Group III-nitride based layer and has an associated second strain. The second strain has a magnitude that is greater than a magnitude of the first strain. A third Group III-nitride based layer, such as an AlGaN or AlN layer, is on the GaN layer. The third Group III-nitride based layer has a bandgap that is greater than the bandgap of the second Group III-nitride based layer and has an associated third strain. The third strain is of opposite strain type to the second strain. A source contact, a drain contact and a gate contact may be provided on the third Group III-nitride based layer.Type: GrantFiled: January 5, 2006Date of Patent: April 10, 2012Assignee: Cree, Inc.Inventor: Adam William Saxler
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Patent number: 8148252Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: March 2, 2011Date of Patent: April 3, 2012Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 8143147Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.Type: GrantFiled: February 10, 2011Date of Patent: March 27, 2012Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
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Patent number: 8133806Abstract: Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns.Type: GrantFiled: September 30, 2010Date of Patent: March 13, 2012Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Christiaan J. Werkhoven
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Patent number: 8129732Abstract: An adhesion layer of a hexagonal crystal is laid on a facet an optical resonator of a nitride semiconductor laser bar having a nitride-based III-V group compound semiconductor layer, and a facet coat is laid on the adhesion layer. In this way, a structure in which the facet coat is laid on the adhesion layer is obtained.Type: GrantFiled: September 15, 2010Date of Patent: March 6, 2012Assignee: Sharp Kabushiki KaishaInventors: Masahumi Kondou, Takeshi Kamikawa, Yoshinobu Kawaguchi
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Patent number: 8110482Abstract: A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an InxGa1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the InxGa1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure.Type: GrantFiled: February 22, 2010Date of Patent: February 7, 2012Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: John F. Kaeding, Dong-Seon Lee, Michael Iza, Troy J. Baker, Hitoshi Sato, Benjamin A. Haskell, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8105919Abstract: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.Type: GrantFiled: April 14, 2010Date of Patent: January 31, 2012Assignee: The Regents of the University of CaliforniaInventors: Arpan Chakraborty, Kwang-Choong Kim, Steven P. DenBaars, James S. Speck, Umesh K. Mishra
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Publication number: 20120021572Abstract: A method for fabricating a semiconductor device includes forming ohmic electrodes on a source region and a drain region of a nitride semiconductor layer, forming a low-resistance layer between an uppermost surface of the nitride semiconductor layer and the ohmic electrodes by annealing the nitride semiconductor layer, removing the ohmic electrodes from at least one of the source region and the drain region after forming the low-resistance layer, and forming at least one of a source electrode and a drain electrode on the low-resistance layer, the at least one of a source electrode and a drain electrode having an edge, a distance between the edge and a gate electrode is longer than a distance between an edge of the low-resistance layer and the gate electrode.Type: ApplicationFiled: July 20, 2011Publication date: January 26, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Shinya Mizuno
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Publication number: 20120015513Abstract: A method for fabricating a semiconductor device includes forming a recess to an AlGaN layer by etching, the AlGaN layer having an Al composition ratio of 0.2 or greater, the recess having a bottom having an RMS roughness less than 0.3 nm, forming a first Ta layer having a thickness of 4 nm to 8 nm on the bottom of the recess, and annealing the first Ta layer to make an ohmic contact in the AlGaN layer.Type: ApplicationFiled: July 13, 2011Publication date: January 19, 2012Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Masatoshi Koyama
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Patent number: 8097482Abstract: A method for manufacturing a Group III nitride semiconductor of the present invention, comprising a sputtering step for disposing a substrate and a target in a chamber and forming a Mg-doped Group III nitride semiconductor on the substrate by a reactive sputtering method, wherein the sputtering step includes respective substeps of: a film formation step for forming a semiconductor thin film while doping with Mg; and a plasma treatment step for applying an inert gas plasma treatment to the semiconductor thin film that has been formed in the film formation step, and the Group III nitride semiconductor is formed by laminating the semiconductor thin film through alternate repetitions of the film formation step and the plasma treatment step.Type: GrantFiled: June 3, 2008Date of Patent: January 17, 2012Assignee: Showa Denko K.KInventors: Kenzo Hanawa, Yasumasa Sasaki, Hisayuki Miki
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Patent number: 8097481Abstract: A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer, such as aluminum nitride (AlN), on the annealed substrate, and growing the non-polar m-plane III-nitride film on the nucleation layer using MOCVD.Type: GrantFiled: October 10, 2007Date of Patent: January 17, 2012Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Bilge M. Imer, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8093618Abstract: There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective layer made of Ag metal, formed on the contact layer and having some particles in-diffused to the semiconductor layer, and a protective layer formed on the reflective layer to restrain out-diffusion of the reflective layer; a method of forming the ohmic electrode; and a semiconductor light emitting element having the ohmic electrode. The present invention has strong adhesive strength and low contact resistance since the reflective layer and the light emitting layer directly form an ohmic contact due to the interface reaction during heat treatment, and the present invention has high light reflectance and excellent thermal stability since the contact layer and the protective layer restrain out-diffusion of the reflective layer during heat treatment.Type: GrantFiled: October 11, 2007Date of Patent: January 10, 2012Assignees: Seoul Opto Device Co., Ltd., Postech Academy-Industry FoundationInventors: Jong Lam Lee, Sang Han Lee
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Patent number: 8080469Abstract: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.Type: GrantFiled: September 19, 2008Date of Patent: December 20, 2011Assignee: The Regents of the University of CaliforniaInventors: Asako Hirai, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Publication number: 20110291147Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: ApplicationFiled: May 25, 2010Publication date: December 1, 2011Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Patent number: 8062967Abstract: Methods for producing nanostructures, particularly Group III-V semiconductor nanostructures, are provided. The methods include use of novel Group III and/or Group V precursors, novel surfactants, oxide acceptors, high temperature, and/or stable co-products. Related compositions are also described. Methods and compositions for producing Group III inorganic compounds that can be used as precursors for nanostructure synthesis are provided. Methods for increasing the yield of nanostructures from a synthesis reaction by removal of a vaporous by-product are also described.Type: GrantFiled: June 1, 2009Date of Patent: November 22, 2011Assignee: Nanosys, Inc.Inventors: Erik C. Scher, Mihai A. Buretea, William P. Freeman, Joel Gamoras, Baixin Qian, Jeffery A. Whiteford
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Patent number: 8048786Abstract: The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved.Type: GrantFiled: November 3, 2008Date of Patent: November 1, 2011Assignee: National Central UniversityInventors: Jen-Inn Chyi, Guan-Ting Chen, Hsueh-Hsing Liu
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Patent number: 8039329Abstract: A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InxAlyGa1?yN (wherein 0<x?1, 0?y<1 and 0<x+y?1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.Type: GrantFiled: March 12, 2010Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Satoshi Nakazawa, Tetsuzo Ueda
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Patent number: 8017513Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.Type: GrantFiled: July 15, 2008Date of Patent: September 13, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Jong-han Jeong, Jae-kyeong Jeong, Jin-seong Park, Yeon-gon Mo, Hui-won Yang, Min-kyu Kim, Tae-kyung Ahn, Hyun-soo Shin, Hun Jung Lee
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Patent number: 8018019Abstract: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at TBLIP in the range of about 220° to about 240° K.Type: GrantFiled: May 8, 2008Date of Patent: September 13, 2011Assignee: University of RochesterInventor: Gary Wicks
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Patent number: 8012783Abstract: The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. The semiconductor element of the present invention has an n-type Gallium nitride based compound semiconductor and an electrode that forms an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferable embodiment, the above-mentioned electrode can also serve as a contact electrode. According to a preferable embodiment, the above-mentioned electrode is superior in the heat resistance. Moreover, a production method of the semiconductor element is also provided.Type: GrantFiled: April 4, 2006Date of Patent: September 6, 2011Assignee: Mitsubishi Chemical CorporationInventors: Tsuyoshi Takano, Takahide Joichi, Hiroaki Okagawa
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Patent number: 8008181Abstract: Misfit dislocations are redirected from the buffer/Si interface and propagated to the Si substrate due to the formation of bubbles in the substrate. The buffer layer growth process is generally a thermal process that also accomplishes annealing of the Si substrate so that bubbles of the implanted ion species are formed in the Si at an appropriate distance from the buffer/Si interface so that the bubbles will not migrate to the Si surface during annealing, but are close enough to the interface so that a strain field around the bubbles will be sensed by dislocations at the buffer/Si interface and dislocations are attracted by the strain field caused by the bubbles and move into the Si substrate instead of into the buffer epi-layer. Fabrication of improved integrated devices based on GaN and Si, such as continuous wave (CW) lasers and light emitting diodes, at reduced cost is thereby enabled.Type: GrantFiled: August 12, 2009Date of Patent: August 30, 2011Assignee: The Regents of The University of CaliforniaInventors: Zuzanna Liliental-Weber, Rogerio Luis Maltez, Hadis Morkoc, Jinqiao Xie
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Patent number: 8003452Abstract: A compound semiconductor device includes a carrier transit layer formed over a substrate; a carrier supply layer formed over the carrier transit layer; a first metal film and a second metal film formed over the carrier supply layer; a first Al comprising film formed over the first metal film; a second Al comprising film formed over the second metal film; a first Au comprising film formed over the first metal film and is free of direct contact with the first Al comprising film; a second Au comprising film formed over the second metal film and free of direct contact with the second Al comprising film; and a gate electrode that is located over the carrier supply layer between the first metal film and the second metal film.Type: GrantFiled: December 16, 2009Date of Patent: August 23, 2011Assignee: Fujitsu LimitedInventor: Toshihiro Ohki
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Publication number: 20110201191Abstract: A method for nondestructive laser lift-off of GaN from sapphire substrates utilizing a solid-state laser is disclosed in the present invention, wherein, a solid-state laser is used as the laser source, and a small laser-spot with a circumference of 3 to 1000 micrometers and a distance of two farthest corners or a longest diameter of no more than 400 micrometers is used for laser scanning point-by-point and line-by-line, wherein the energy in the small laser-spot is distributed such that the energy in the center of the laser-spot is the strongest and is gradually reduced toward the periphery. According to the present invention, a nondestructive laser lift-off with a small laser-spot is achieved, and a scanning mode of the laser lift-off is improved, thereby a lift-off method without the need of aiming is achieved.Type: ApplicationFiled: April 21, 2009Publication date: August 18, 2011Inventors: Guoyi Zhang, Yongjian Sun, Xiangning Kang, Zhizhong Chen, Zhijian Yang, Xinrong Yang
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Patent number: 7998877Abstract: This invention describes a method of making solar cells wherein the efficiency of the solar cell is enhanced by defining a diffraction grating either on top of the cell or at the bottom of the cell. The diffraction grating spacing is defined such that it bends one or more wavelengths of the incident radiation thereby making those wavelengths traverse in the direction of the plane of the device. The addition of a diffraction grating is done in conjunction with thinning down the cell such that the minority carriers generated (holes and electrons) have a higher probability of being collected. The combined effect of the diffraction grating and the reduced thickness in the solar cell increases the efficiency of the solar cell.Type: GrantFiled: May 2, 2008Date of Patent: August 16, 2011Inventor: Saket Chadda
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Patent number: 7998272Abstract: A method of fabricating a plurality of freestanding GaN wafers includes mounting a GaN substrate in a reactor, forming a GaN crystal growth layer on the GaN substrate through crystal growth, performing surface processing of the GaN crystal growth layer to form a GaN porous layer having a predetermined thickness on the GaN crystal growth layer, repeating the forming of the GaN crystal growth layer and the forming of the GaN porous layer a plurality of times to form a stack of alternating GaN crystal growth layers and GaN porous layers on the GaN substrate, and cooling the stack such that the GaN layers self-separate to form the freestanding GaN wafers. The entire process of forming a GaN porous layer and a thick GaN layer is performed in-situ in a single reactor. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN surface processing and growth proceed using an HVPE process gas such that costs are greatly reduced.Type: GrantFiled: November 14, 2006Date of Patent: August 16, 2011Assignee: Samsung Corning Precision Materials, Co., Ltd.Inventor: In-Jae Song
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Patent number: 7993948Abstract: A method for fabricating an electrode by (i) depositing a palladium film on a p-type semiconductor layer; (ii) introducing an oxygen gas onto the palladium film to provide an oxygen ambient; (iii) oxidizing the palladium film adjacent to the semiconductor layer by annealing the palladium film in the oxygen ambient; and (iv) forming a palladium oxide film directly in contact with the semiconductor layer.Type: GrantFiled: August 11, 2009Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Saito, Shinya Nunoue, Toshiyuki Oka
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Patent number: 7989239Abstract: A light emitting diode having high light extraction efficiency and a method of manufacturing the same are provided. The LED includes a semiconductor multiple layer including an active layer; a transparent electrode layer formed on the semiconductor multiple layer; and refraction field unit embedded in the transparent electrode layer and formed of a material having a different refractive index than the transparent electrode layer.Type: GrantFiled: May 22, 2009Date of Patent: August 2, 2011Assignee: Samsung LED Co., Ltd.Inventor: Jin-seo Im
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Publication number: 20110175103Abstract: A semiconductor device has a satisfactory ohmic contact on a p-type principal surface tilting from a c-plane. The principal surface 13a of a p-type semiconductor region 13 extends along a plane tilting from a c-axis (axis <0001>) of hexagonal group-III nitride. A metal layer 15 is deposited on the principal surface 13a of the p-type semiconductor region 13. The metal layer 15 and the p-type semiconductor region 13 are separated by an interface 17 such that the metal layer functions as a non-alloy electrode. Since the hexagonal group-III nitride contains gallium as a group-III element, the principal surface 13a comprising the hexagonal group-III nitride is more susceptible to oxidation compared to the c-plane of the hexagonal group-III nitride. The interface 17 avoids an increase in amount of oxide after the formation of the metal layer 15 for the electrode.Type: ApplicationFiled: July 14, 2010Publication date: July 21, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shinji TOKUYAMA, Masahiro ADACHI, Takashi KYONO, Yoshihiro SAITO
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Patent number: 7981787Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.Type: GrantFiled: August 17, 2009Date of Patent: July 19, 2011Assignee: OKI Semiconductor Co., Ltd.Inventors: Takayuki Izumi, Ryoji Shigemasa, Tomoyuki Ohshima
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Publication number: 20110169138Abstract: A method of fabricating a p-type contact on a nonpolar or semipolar (Al,Ga,In)N device, includes the steps of growing a p-type layer on an (Al,Ga,In)N device, wherein the (Al,Ga,In)N device is a nonpolar or semipolar (Al,Ga,In)N device, and the p-type layer is a nonpolar or semipolar (Al,Ga,In)N layer; and cooling the p-type layer down, in the presence of Bis(Cyclopentadienyl)Magnesium (Cp2Mg), to form a magnesium-nitride (MgxNy) layer on the p-type layer. A metal deposition is performed to fabricate a p-type contact on the p-type layer of the (Al,Ga,In)N device, after the cooling step, wherein the p-type contact has a contact resistivity lower than a p-type contact of a polar (Al,Ga,In)N device with substantially similar composition. A hydrogen chloride (HCl) pre-treatment of the p-type layer may be performed, after the cooling step and before the metal deposition step.Type: ApplicationFiled: October 21, 2010Publication date: July 14, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: You-Da Lin, Arpan Chakraborty, Shuji Nakamura, Steven P. DenBaars
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Publication number: 20110156048Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.Type: ApplicationFiled: June 4, 2009Publication date: June 30, 2011Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Ryou Kato
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Patent number: 7968435Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.Type: GrantFiled: June 24, 2009Date of Patent: June 28, 2011Assignee: HRL Laboratories, LLCInventors: Peter Deelman, Ken Elliott, David Chow
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Patent number: 7968909Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.Type: GrantFiled: November 4, 2010Date of Patent: June 28, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Frederic Dupont
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Patent number: 7964482Abstract: The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer (5), on a substrate (1), the substrate (1) comprising at least a Ge surface (3), preferably with hexagonal symmetry. The method comprises heating the substrate (1) to a nitridation temperature between 400° C. and 940° C. while exposing the substrate (1) to a nitrogen gas flow and subsequently depositing the group III-nitride layer, e.g. GaN layer (5), onto the Ge surface (3) at a deposition temperature between 100° C. and 940° C. By a method according to embodiments of the invention, a group III-nitride layer, e.g. GaN layer (5), with good crystal quality may be obtained. The present invention furthermore provides a group III-nitride/substrate structure formed by the method according to embodiments of the present invention and a semiconductor device comprising at least one such structure.Type: GrantFiled: July 9, 2007Date of Patent: June 21, 2011Assignees: IMEC, Vrije Universiteit BrusselInventors: Ruben Lieten, Stefan Degroote