Abstract: Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: A method for packaging solar cell module. The method includes providing a first substrate member and forming a plurality of thin film photovoltaic cells overlying the surface region of the first substrate member. A first connector member and a second connector member having a second thickness are operably coupled to each of the plurality of thin film photovoltaic cells. A first spacer element and a second spacer element overly portions of the surface region of the first substrate member. The method provides a laminating material overlying the plurality of thin film photovoltaic cells, the spacer elements, and the connector members. A second substrate member overlies the laminating material. A lamination process is performed to form the solar cell module by maintaining a spatial gap occupied by the laminating material between an upper surface regions of the connector members and the second substrate member using the spacer elements.

Abstract: A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.

Abstract: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm?2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A method of selectively attaching a capping agent to an H-passivated Si or Ge surface is disclosed. The method includes providing the H-passivated Si or Ge surface, the H-passivated Si or Ge surface including a set of covalently bonded Si or Ge atoms and a set of surface substitutional atoms, wherein the set of surface substitutional atoms includes at least one of boron atoms, aluminum atoms, gallium atoms, indium atoms, tin atoms, lead atoms, phosphorus atoms, arsenic atoms, sulfur atoms, and bismuth atoms. The method also includes exposing the set of surface functional atoms to a set of capping agents, each capping agent of the set of capping agents having a set of functional groups bonded to a pair of carbon atoms, wherein the pair of carbon atoms includes at least one pi orbital bond, and further wherein a covalent bond is formed between at least some surface substitutional atoms of the set of surface substitutional atoms and at least some capping agents of the set of capping agents.

Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.

Abstract: A method of making a nitride semiconductor laser comprises forming a first InGaN film for an active layer on a gallium nitride based semiconductor region, and the first InGaN film has a first thickness. In the formation of the first InGaN film, a first gallium raw material, a first indium raw material, and a first nitrogen raw material are supplied to a reactor to deposit a first InGaN for forming the first InGaN film at a first temperature, and the first InGaN has a thickness thinner than the first thickness. Next, the first InGaN is heat-treated at a second temperature lower than the first temperature in the reactor, while supplying a second indium raw material and a second nitrogen raw material to the reactor. Then, after the heat treatment, a second InGaN is deposited at least once to form the first InGaN film.

Abstract: A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer.

Abstract: A method of forming a buffer layer for a nitride compound semiconductor light emitting device includes placing a sapphire (Al2O3) substrate in a reaction chamber; introducing a nitrogen source gas into a reaction chamber; and annealing the substrate in a state where the nitrogen source gas is introduced into the reaction chamber, to form an AIN compound layer on the substrate. The AIN compound layer having intermediate properties between those of the substrate and a semiconductor layer is formed between the substrate and the semiconductor layer. Thus, an interface space between the AIN compound layer and the buffer layer or the semiconductor layer that is to be formed on the AIN compound layer becomes smaller and a crystal stress also becomes smaller, thereby reducing a crack that may be generated due to differences in lattice constant and thermal expansion coefficient between the substrate and the semiconductor layer.

Abstract: The present invention relates to an AlGaInN based optical device fabricated by a new p-type AlGaInN:Mg growth method and method for manufacturing the same, including a p-type nitride semiconductor layer that is grown using both NH3 and a hydrazine based source as a nitrogen precursor, thereby an additional subsequent annealing process for extracting hydrogen is not necessary and thus the process is simple and an active layer can be prevented from being thermally damaged by subsequent annealing.

Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.

Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.

Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes forming a metal catalytic pattern on a semiconductor substrate; etching the semiconductor substrate using the metal catalytic pattern as an etching mask to form a recess; forming an insulating layer over a structure including the recess, the metal catalytic pattern, and the semiconductor substrate; patterning the insulating layer to cross over the metal catalytic pattern and to expose a predetermined portion of the metal catalytic pattern; and growing a nano wire using the exposed predetermined portion of the metal catalytic pattern.

Abstract: A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.

Abstract: An adhesion layer of a hexagonal crystal is laid on a facet an optical resonator of a nitride semiconductor laser bar having a nitride-based III-V group compound semiconductor layer, and a facet coat is laid on the adhesion layer. In this way, a structure in which the facet coat is laid on the adhesion layer is obtained.

Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.

Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.

Abstract: Multi-layered carbon-based hardmask and method to form the same. The multi-layered carbon-based hardmask includes at least top and bottom carbon-based hardmask layers having different refractive indexes. The top and bottom carbon-based hardmask layer thicknesses and refractive indexes are tuned so that the top carbon-based hardmask layer serves as an anti-reflective coating (ARC) layer.

Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

Abstract: A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.

Abstract: In one aspect, a method includes forming a silicon dioxide layer on a surface of a diamond layer disposed on a gallium nitride (GaN)-type layer. The method also includes etching the silicon dioxide layer to form a pattern. The method further includes etching portions of the diamond exposed by the pattern.

Abstract: A process for the semiconductor laser diode is disclosed, which prevents the abnormal growth occurred at the second growth for the burying region of the buried hetero structure. The ICP (Induction-Coupled Plasma) CVD apparatus forms a silicon oxide file with a thickness of above 2 ?m as adjusting the bias power PBIAS. Patterning the silicon oxide mask and dry-etching the semiconductor layers, a mesa structure including the active layer may be formed. As leaving the patterned silicon oxide film, the second growth for the burying region buries the mesa structure. The residual stress of the silicon oxide film is ?250 to ?150 MPa at a room temperature, while, it is ?200 to 100 MPa at temperatures from 500 to 700° C.

Abstract: A semiconductor device includes a p-type nitride semiconductor layer (14); and a p-side electrode (18) including a palladium oxide film (30) connected to a surface of the nitride semiconductor layer (14).

Abstract: Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation.

Abstract: An object of the present invention is to provide a method for producing a gallium nitride-based compound semiconductor multilayer structure useful for the production of a gallium nitride-based compound semiconductor light-emitting device which can ensure that the operating voltage is reduced, the light emission output is good and the light emission output is less changed due to aging.

Abstract: A method for growing reduced defect density planar gallium nitride (GaN) films is disclosed. The method includes the steps of (a) growing at least one silicon nitride (SiNx) nanomask layer over a GaN template, and (b) growing a thickness of a GaN film on top of the SiNx nanomask layer.

Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.

Abstract: Fabrication method of GaN power LED with electrodes formed by composite optical coatings, comprising epitaxially growing N—GaN, active, and P—GaN layers successively on a substrate; depositing a mask layer thereon; coating the mask layer with photoresist; etching the mask layer into an N—GaN electrode pattern; etching through that electrode pattern to form an N—GaN electrode region; removing the mask layer and cleaning; forming a transparent, electrically conductive film simultaneously on the P—GaN and N—GaN layers; forming P—GaN and N—GaN transparent, electrically conductive electrodes by lift-off; forming bonding pad pattern for the P—GaN and N—GaN electrodes by photolithography process; simultaneously forming thereon bonding pad regions for the P—GaN and N—GaN electrodes by stepped electron beam evaporation; forming an antireflection film pattern by photolithography process; forming an antireflection film; thinning and polishing the backside of the substrate, then forming a reflector thereon; and completin

Abstract: This invention describes a radiation-emitting semiconductor component based on GaN, whose semiconductor body is made up of a stack of different GaN semiconductor layers (1). The semiconductor body has a first principal surface (3) and a second principal surface (4), with the radiation produced being emitted through the first principal surface (3) and with a reflector (6) being produced on the second principal surface (4). The invention also describes a production method for a semiconductor component pursuant to the invention. An interlayer (9) is first applied to a substrate (8), and a plurality of GaN layers (1) that constitute the semiconductor body of the component are then applied to this. The substrate (8) and the interlayer (9) are then detached and a reflector (6) is produced on a principal surface of the semiconductor body.

Abstract: A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer, the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by ion implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution.

Abstract: According to an exemplary embodiment, a PHEMT (pseudomorphic high electron mobility transistor) structure includes a conductive channel layer. The PHEMT structure further includes at least one doped layer situated over the conductive channel layer. The at least one doped layer can include a heavily doped layer situated over a lightly doped layer. The PHEMT structure further includes a recessed ohmic contact situated on the conductive channel layer, where the recessed ohmic contact is situated in a source/drain region of the PHEMT structure, and where the recessed ohmic contact extends below the at least one doped layer. According to this exemplary embodiment, the recessed ohmic contact is bonded to the conductive channel layer. The recessed ohmic contact is situated adjacent to the at least one doped layer. The PHEMT structure further includes a spacer layer situated between the at least one doped layer and the conductive channel layer.

Abstract: When a p-layer 4 composed of GaN is maintained at ordinary temperature and TNO is sputtered thereon by an RF magnetron sputtering method, a laminated TNO layer 5 is in an amorphous state. Then, there is included a step of thermally treating the amorphous TNO layer in a reduced-pressure atmosphere where hydrogen gas is substantially absent to thereby crystallize the TNO layer. At the sputtering, an inert gas is passed through together with oxygen gas, and volume % of the oxygen gas contained in the gas passed through is 0.10 to 0.15%. In this regard, oxygen partial pressure is 5×10?3 Pa or lower. The temperature of the thermal treatment is 500° C. for about 1 hour.

Abstract: A gallium nitride semiconductor LED includes a substrate for growing a GaN semiconductor material, an n-type GaN clad layer formed on the substrate and doped with Al, an active layer having a quantum well structure formed on the n-type GaN clad layer, and a p-type GaN clad layer formed on the active layer.

Abstract: A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film 2? with mesh structure in which micro voids are provided on a starting substrate 1, and growing a III group nitride semiconductor crystal layer 3 via the metal film or metal nitride film 2?.

Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.

Abstract: A radiation-emitting semiconductor chip having an absorbent brightness setting layer between a connection region and a current injection region and/or, as seen from the connection region, outside the current injection region on a front-side radiation coupling-out area of the semiconductor layer sequence. The brightness setting layer absorbs in a targeted manner part of the radiation generated in the semiconductor layer sequence. In another embodiment, a partly insulating brightness setting layer is arranged between the connection region and the active layer.

Abstract: A Group III-V compound semiconductor includes, at least, a substrate, a buffer layer of the general formula InuGavAlwN (wherein, 0?u?1, 0?v?1, 0?w?1, u+v+w=1) and a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN (wherein, 0?x?1, 0?y?1, 0?z?1, x+y+z=1), in this order, wherein the buffer layer has a thickness of at least about 5 ? and not more than about 90 ?. A method is provided for producing the Group III-V compound semiconductor, including forming a buffer layer of the general formula InuGavAlwN on a substrate to give a thickness of at least about 5 ? and not more than about 90 ? at temperatures lower than the growing temperature of the compound semiconductor crystal layer before growing the compound semiconductor crystal layer, and then growing a Group III-V compound semiconductor crystal layer of the general formula InxGayAlzN on the buffer layer.

Abstract: The invention is to provide a process for industrially advantageously producing InP fine particles having a nano-meter size efficiently in a short period of time and an InP fine particle dispersion, and there are provided a process for the production of InP fine particles by reacting an In raw material containing two or more In compounds with a P raw material containing at least one P compound in a solvent wherein the process uses, as said two or more In compounds, at least one first In compound having a group that reacts with a functional group of P compound having a P atom adjacent to an In atom to be eliminated with the functional group in the formation of an In-P bond and at least one second In compound having a lower electron density of In atom in the compound than said first In compound and Lewis base solvent as said solvent, and InP fine particles obtained by the process.

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract: A method of forming an electronic device can include forming a metallic layer over a side of a workpiece including a substrate, a differential etch layer, and a semiconductor layer. The differential etch layer may lie between the substrate and the semiconductor layer, and the semiconductor layer may lie along the side of the workpiece. The process can further include selectively removing at least a majority of the differential etch layer from between the substrate and the semiconductor layer, and separating the semiconductor layer and the metallic layer from the substrate. The selective removal can be performed using a wet etching, dry etching, or electrochemical technique. In a particular embodiment, the same plating bath may be used for plating the metallic layer and selectively removing the differential etch layer.

Abstract: A process for producing a group III nitride compound semiconductor light emitting device, the group III nitride compound semiconductor light emitting device and a lamp, having excellent producability and excellent light emitting characteristics are provided. Such a process for producing a group III nitride semiconductor light emitting device is a process for producing a group III nitride semiconductor light emitting device having a semiconductor layer 20 constituted by laminating an n-type semiconductor layer, a light-emitting layer 15 and a p-type semiconductor layer 16.

Abstract: A semiconductor device which displays an oscillating voltage due to the creation of charge domains which includes a plurality of semiconductor layers and at least two electrodes spaced from one another in the direction of the layers, an upper of which has a composition and/or dimensions predetermined so that a charge therein balances a depletion from a surface charge of the upper layer on application of a potential difference across said electrodes. The electrodes may be in contact solely with the upper layer. A method of manufacturing the device is also provided.

Abstract: A method of preparing an array of conducting or semi-conducting nanowires may include forming a vicinal surface of stepped atomic terraces on a substrate, and depositing a fractional layer of dopant material to form nanostripes having a width less than the width of the atomic terraces. Diffusion of the atoms of the dopant nanostripes into the substrate may form the nanowires.