Abstract: A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first metal film and the substrate and the interface between the second metal film and the substrate both form a Schottky contact. Next, laser light is irradiated from above the upper surface of the substrate only onto the first metal film on the substrate after the diameter of the top end of the laser light has been reduced. Thus, since the metal-semiconductor interface between the first metal film and the substrate is turned into an alloy owing to the energy of the laser light without heating the entire substrate, an ohmic contact can be formed in the interface between the first metal film and the substrate. As a result, an ohmic electrode can be constituted by the first metal film.

Abstract: A GaN group compound semiconductor device includes an electrode structure provided on a p-GaN group compound semiconductor layer, the electrode structure including: a first layer formed on the p-GaN group compound semiconductor layer, the first layer including a compound including a first metal element and Ga; and a second layer formed on the first layer, the second layer including the first metal element. The first layer contains substantially no nitrogen.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Abstract: It is intended to realize an ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics. Provided on an n.sup.+ -type GaAs substrate is an ohmic electrode in which an n.sup.++ -type regrown GaAs layer regrown from the n.sup.+ -type GaAs substrate and a NiGe film containing precipitates composed of .alpha.'-AuGa are sequentially stacked. The ohmic electrode may be fabricated by sequentially stacking a Ni film, Au film and Ge film on the n.sup.+ -type GaAs substrate, then patterning these films by, for example, lift-off, and thereafter annealing the structure at a temperature of 400.about.750.degree. C. for several seconds to several minutes.

Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.

Abstract: The electrode structure of the invention includes a p-type Al.sub.x Ga.sub.y In.sub.1-x-y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y.ltoreq.1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Abstract: A complementary heterojunction field effect transistor (CHFET) in which the channels for the p-FET device and the n-FET device forming the complementary FET are formed from gallium antimonide (GaSb) or indium antimonide (InSb). An n-type HFET structure is grown, for example, by molecular beam epitaxy (MBE) in order to obtain the highest electron or hole mobility. The complementary p-type HFET is formed by p-type doping of a cap layer thereby eliminating the need for two implants for channel doping. In order to reduce the complexity of the process for making the CHFET, a common gold germanium alloy contact is used for both the p and n-type channel devices, thereby eliminating the need for separate ohmic contacts, resulting in a substantial reduction in the number of mask levels and, thus, complexity in fabricating the device.

Abstract: A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

Abstract: The present invention is directed to a technique for manufacturing semiconductor devices in which p type GaN is formed on a substrate and semi-insulating AlN is formed on the P type GaN with n type GaN formed on the p type GaN and partially below the AlN. Highly efficient high power and high voltage semiconductor devices are formed through this technique having better or similar properties to silicon type semiconductors.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.

Abstract: A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.

Abstract: A surface of a compound semiconductor having at least gallium (Ga) and nitride (N) forms a target for sputtering with inert gas, so that oxide and other attachments are removed therefrom. The sputtering the surface is carried out until a disruption layer is formed which has atomically disordered and bumpy arrangement. Following the sputtering process, metal deposition by sputtering and alloying are carried out under vacuum in the same chamber used for the sputtering processes. As a result, the contact resistance between the surface layer and the deposited electrode layer is decreased.

Abstract: A fabrication method of a compound semiconductor FET that enables to produce source/drain electrodes and a gate electrode at any positions flexibly without increase of the number of necessary process steps. First, a compound semiconductor substructure having on its surface first regions on which source/drain electrodes are formed respectively and a second region on which a gate electrode is formed is prepared. A patterned mask film is then formed on the surface of the substructure. The mask film has first windows for the source/drain electrodes and a second window for the gate electrode. A conductor film is selectively formed on the surface of the substructure using the patterned mask film as a mask. The conductor film contains first parts placed on the first regions through the respective first windows of the mask film and second part placed on the second region through the second window of the mask film.

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: A method of fabricating a bipolar transistor includes successively growing a collector layer, a base layer, and a crystalline mask layer on a semiconductor substrate; forming an opening in the crystalline mask layer to expose a portion of the base layer; growing an emitter layer on the crystalline mask layer and on the base layer exposed in the opening of the mask layer; forming an emitter electrode on the emitter layer; removing part of the emitter layer using the emitter electrode as a mask; removing the crystalline mask layer; forming a first resist pattern for formation of base electrodes; forming base electrodes using the first resist pattern and the emitter electrode as masks; removing the first resist pattern; forming a second resist pattern for formation of collector electrodes covering base electrodes and the emitter electrode; using the second resist pattern as a mask, removing portions of the base layer and the collector layer; and forming collector electrodes in contact with the collector layer.

Abstract: A solution of hydrogen peroxide ?H.sub.2 O.sub.2 !, citric acid ?HOC(CH.sub.2 COOH).sub.2 COOH.H.sub.2 O!, and a salt of citric acid such as potassium citrate ?HOC(CH.sub.2 COOK).sub.2 COOK.H.sub.2 O!, and hydrogen peroxide ?H.sub.2 O.sub.2 !, in a proper pH range, selectively etches GaAs-containing Group III-V compounds in the presence of other Group III-V compounds. As an illustration, Al.sub.y Ga.sub.1-y As is selectively etched in the presence of Al.sub.x Ga.sub.1-x As (0.ltoreq.y<0.2 & x>0.2) when the pH range of the etchant solution is between approximately 3 and 6. The etchant solution described herein may be utilized in the fabrication of, for example, high-frequency transistors exhibiting improved saturated current (I.sub.dss) and threshold voltage (V.sub.th) uniformity.