Iii-v Compound Semiconductor Patents (Class 438/604)
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Patent number: 6784074Abstract: A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material forming a defect-free layer.Type: GrantFiled: June 6, 2003Date of Patent: August 31, 2004Assignee: NSC-Nanosemiconductor GmbHInventors: Vitaly Shchukin, Nikolai Ledentsov
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Patent number: 6784085Abstract: A high deposition rate sputter method is utilized to produce bulk, single-crystal, low-defect density Group III nitride materials suitable for microelectronic and optoelectronic devices and as substrates for subsequent epitaxy, and to produce highly oriented polycrystalline windows. A template material having an epitaxial-initiating growth surface is provided. A Group III metal target is sputtered in a plasma-enhanced environment using a sputtering apparatus comprising a non-thermionic electron/plasma injector assembly, thereby to producing a Group III metal source vapor. The Group III metal source vapor is combined with a nitrogen-containing gas to produce a reactant vapor species comprising Group III metal and nitrogen. The reactant vapor species is deposited on the growth surface to produce a single-crystal MIIIN layer thereon. The template material is removed, thereby providing a free-standing, single-crystal MIIIN article having a diameter of approximately 0.Type: GrantFiled: November 30, 2001Date of Patent: August 31, 2004Assignee: North Carolina State UniversityInventors: Jerome J. Cuomo, N. Mark Williams, Andrew David Hanser, Eric Porter Carlson, Darin Taze Thomas
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Publication number: 20040159851Abstract: A superlattice contact structure for light emitting devices includes a plurality of contiguous p-type Group III nitride layers. The contact structure may be formed of p-type indium nitride, aluminum indium nitride, or indium gallium nitride. Also disclosed is a light emitting device that incorporates the disclosed contact structures.Type: ApplicationFiled: February 13, 2003Publication date: August 19, 2004Inventors: John Adam Edmond, Kathleen Marie Doverspike, Michael John Bergmann, Hua-Shuang Kong
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Patent number: 6777315Abstract: A method of controlling the resistivity of gallium nitride is disclosed. The method incorporates an MBE system and utilizes solid source gallium, gaseous source nitrogen and solid source Buckminster Fullerene C60 as a carbon dopant for the GaN film. A desired, predetermined GaN film resistivity can be created during the growth process by selecting the temperature of the effusion cell containing the C60 within a predetermined range so as to impart the desired resistivity in the GaN film.Type: GrantFiled: May 1, 2003Date of Patent: August 17, 2004Assignee: The United States of America as represented by the Secretary of the Air ForceInventor: Joseph E. Van Nostrand
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Patent number: 6774025Abstract: After a p seat electrode is laminated on a light-transmissive electrode, the two electrodes are heated at a relatively low temperature to thereby remove gas (degassing) from between the two electrodes. Then, the two electrodes are alloyed with each other at a high temperature.Type: GrantFiled: June 5, 2002Date of Patent: August 10, 2004Assignee: Toyoda Gosei Co., Ltd.Inventor: Toshiya Uemura
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Patent number: 6774449Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.Type: GrantFiled: September 18, 2000Date of Patent: August 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
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Patent number: 6767830Abstract: A volatile solid-source novel antimony precursor, Br2SbCH3, that may be utilized in semiconductor processing chambers for depositing antimony on a substrate by deposition methods, e.g., chemical vapor deposition, ion implantation, molecular beam epitaxy, diffusion and rapid thermal processing. The novel antimony compound of the invention is synthesized by combining tribromide antimony with trimethylantimony under heating conditions that form a Br2SbCH3 crystalline product.Type: GrantFiled: August 7, 2002Date of Patent: July 27, 2004Assignee: Advanced Technology Materials, Inc.Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum, Michael A. Todd, Niamh McMahon
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Publication number: 20040142550Abstract: A method for producing a III-V group compound semiconductor layer comprises the steps of: forming a first III-V group compound semiconductor layer on a substrate in a reaction chamber; and supplying a III group material gas to the reaction chamber before or after the step of forming the first III-V group compound semiconductor layer to prevent re-evaporation of the III group gas in the reaction chamber.Type: ApplicationFiled: January 7, 2004Publication date: July 22, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Junichi Nakamura, Kazuaki Sasaki
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Patent number: 6764870Abstract: A gallium nitride type semiconductor laser device includes: a substrate; and a layered structure formed on the substrate. The layered structure at least includes an active layer of a nitride type semiconductor material which is interposed between a pair of nitride type semiconductor layers each functioning as a cladding layer or a guide layer. A current is injected into a stripe region in the layered structure having a width smaller than a width of the active layer. The width of the stripe region is in a range between about 0.2 &mgr;m and about 1.8 &mgr;m.Type: GrantFiled: August 13, 2002Date of Patent: July 20, 2004Assignee: Sharp Kabushiki KaishaInventor: Toshiyuki Okumura
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Patent number: 6762069Abstract: A method for manufacturing light-emitting device on non-transparent substrate includes the steps of forming a semiconductor epitaxial layer, a first conductive layer, a reflecting layer and a first conduction layer on a first substrate, and forming second conduction layer on a second substrate. Afterward, the first conduction layer and the second conduction layer is bounded by thermal pressing. The first substrate is then removed and a second conductive layer is formed to complete a light-emitting device. The light-emitting device can be incorporated with wetting layer and blocking layer to prevent inner diffusion and enhance external quantum efficiency.Type: GrantFiled: November 19, 2002Date of Patent: July 13, 2004Assignee: United Epitaxy Company, Ltd.Inventors: Chung-Kuei Huang, Chih-Sung Chang, Tzer-Perng Chen, Kuang-Neng Yang
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Publication number: 20040130025Abstract: A GaN layer is formed on a sapphire substrate through an AlN buffer layer and doped with Mg to prepare a laminate (referred to as “GaN substrate”). A metal (Pt and Ni) electrode 50 nm thick is formed on the GaN substrate by (1) vapor deposition after the GaN substrate is heated to a temperature of 300° C. or by (2) vapor deposition while the GaN substrate is left at room temperature. (3) The electrode obtained in (2) is heated to 300° C. in a nitrogen atmosphere. The contact resistance of the electrode obtained in (1) is lower by two or three digits than that of the electrode obtained in (2) or (3). That is, the electric characteristic of the electrode obtained in (1) is improved greatly.Type: ApplicationFiled: October 29, 2003Publication date: July 8, 2004Applicant: Toyoda Gosei Co., Ltd.Inventors: Ippei Fujimoto, Tsutomu Sekine, Miki Moriyama, Masanori Murakami, Naoki Shibata
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Patent number: 6759139Abstract: A nitride-based semiconductor element enabling formation of a nitride-based semiconductor layer having low dislocation density, consisting of a material different from that of an underlayer, on the underlayer with a small thickness is obtained. This nitride-based semiconductor element comprises a plurality of mask layers formed at a prescribed interval to be in contact with the upper surface of the underlayer while partially exposing the underlayer and the nitride-based semiconductor layer, formed on the upper surface of the underlayer and the mask layers, consisting of the material different from that of the underlayer. The minimum distance between adjacent mask layers is smaller than the width of an exposed part of the underlayer located between the adjacent mask layers.Type: GrantFiled: February 25, 2002Date of Patent: July 6, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tatsuya Kunisato, Nobuhiko Hayashi, Hiroki Ohbo, Masayuki Hata, Tsutomu Yamaguchi
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Patent number: 6753273Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a quantum well disposed between adjacent layers of the device; and providing a layer of quantum dots disposed in one of the adjacent layers, and spaced from the quantum well, whereby carriers can tunnel in either direction between the quantum well and the quantum dots.Type: GrantFiled: July 31, 2002Date of Patent: June 22, 2004Assignees: The Board of Trustees of The University of Illinois, The Board of Regents, The University of Texas SystemInventors: Nick Holonyak, Jr., Russell Dupuis
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Publication number: 20040115917Abstract: A first group III nitride compound layer, which is formed on a substrate by a method not using metal organic compounds as raw materials, is heated in an atmosphere of a mixture gas containing a hydrogen or nitrogen gas and an ammonia gas, so that the crystallinity of a second group III nitride compound semiconductor layer formed on the first group III nitride compound layer is improved. When the first group III nitride compound layer is formed on a substrate by a sputtering method, the thickness of the first group III nitride compound layer is set to be in a range of from 50 Å to 3000 Å.Type: ApplicationFiled: December 3, 2003Publication date: June 17, 2004Applicant: Toyoda Gosei Co., Ltd.Inventors: Naoki Shibata, Jun Ito, Toshiaki Chiyo, Shizuyo Asami, Hiroshi Watanabe, Masanobu Senda, Shinya Asami
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Patent number: 6746948Abstract: An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III-V nitride semiconductor with oxygen atoms.Type: GrantFiled: September 16, 2002Date of Patent: June 8, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daisuke Ueda, Shinichi Takigawa
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Patent number: 6743702Abstract: A highly reliable semiconductor laser device having a low operating voltage is obtained by increasing adhesive force of the overall electrode layer to a nitride-based semiconductor layer without deteriorating a low contact property. This nitride-based semiconductor laser device comprises a nitride-based semiconductor layer formed on an active layer and an electrode layer formed on the nitride-based semiconductor layer, while the electrode layer includes a first electrode layer containing a material having strong adhesive force to the nitride-based semiconductor layer and a second electrode layer, formed on the first electrode layer, having weaker adhesive force to the nitride-based semiconductor layer than the first electrode layer for reducing contact resistance of the electrode layer with respect to the nitride-based semiconductor layer.Type: GrantFiled: January 30, 2002Date of Patent: June 1, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Takenori Goto, Yasuhiko Nomura, Tsutomu Yamaguchi, Kiyoshi Oota
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Patent number: 6734033Abstract: A light emitting diode is disclosed. The diode includes a silicon carbide substrate having a first conductivity type, a first gallium nitride layer above the SiC substrate having the same conductivity type as the substrate, a superlattice on the GaN layer formed of a plurality of repeating sets of alternating layers selected from among GaN, InGaN, and AlInGaN, a second GaN layer on the superlattice having the same conductivity type as the first GaN layer, a multiple quantum well on the second GaN layer, a third GaN layer on the multiple quantum well, a contact structure on the third GaN layer having the opposite conductivity type from the substrate and the first GaN layer, an ohmic contact to the SiC substrate, and an ohmic contact to the contact structure.Type: GrantFiled: June 10, 2003Date of Patent: May 11, 2004Assignee: Cree, Inc.Inventors: David Todd Emerson, Amber Christine Abare, Michael John Bergmann
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Patent number: 6727167Abstract: A method of making a transparent electrode for a light-emitting diode includes depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal, the mask having at least one opening so that the first region is covered by the mask and a second region is aligned with the at least one opening in the mask. The method also includes removing metal aligned with the at least one opening in the mask in the second region to form the first electrode overlying the first region of the semiconductor structure and so as to reveal the top surface of the semiconductor structure in the second region.Type: GrantFiled: October 12, 2001Date of Patent: April 27, 2004Assignee: Emcore CorporationInventor: Mark Gottfried
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Patent number: 6706542Abstract: The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.Type: GrantFiled: August 25, 2000Date of Patent: March 16, 2004Assignee: TriQuint Technology Holding Co.Inventors: Michael Geva, Yuliya Anatolyevna Akulova, Abdallah Ougazzaden
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Patent number: 6706620Abstract: A lower region having a composition of Alx1Gax2Inx3N (x1+x2+x3=1, 0.5≦x1≦1.0) is formed through epitaxial growth by a CVD method, and subsequently, an upper region having a composition of Aly1Gay2Iny3N (y1+y2+y3=1, 0≦y1≦x1−0.1) is formed through epitaxial growth by a CVD method. A boundary face divides a given III nitride film into the lower region and the upper region and the lower and upper regions have an Al content difference of 10 atomic percent or more.Type: GrantFiled: February 13, 2002Date of Patent: March 16, 2004Assignee: NGK Insulators, Ltd.Inventors: Tomohiko Shibata, Mitsuhiro Tanaka, Keiichiro Asai, Osamu Oda
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Patent number: 6703293Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.Type: GrantFiled: July 11, 2002Date of Patent: March 9, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Douglas J. Tweet, Sheng Teng Hsu, Jer-shen Maa, Jong-Jan Lee
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Patent number: 6699778Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.Type: GrantFiled: January 18, 2002Date of Patent: March 2, 2004Assignee: Infineon Technologies AGInventors: Bernd Borchert, Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
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Patent number: 6682968Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: January 27, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6653215Abstract: A contact for n-type III-V semiconductor such as GaN and related nitride-based semiconductors is formed by depositing Al,Ti,Pt and Au in that order on the n-type semiconductor and annealing the resulting stack, desirably at about 400-600° C. for about 1-10 minutes. The resulting contact provides a low-resistance, ohmic contact to the semiconductor and excellent bonding to gold leads.Type: GrantFiled: October 5, 2001Date of Patent: November 25, 2003Assignee: Emcore CorporationInventors: Michael G. Brown, Ivan Eliashevich, Keng Ouyang, Hari Venugopalan
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Publication number: 20030205721Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.Type: ApplicationFiled: March 21, 2001Publication date: November 6, 2003Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
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Patent number: 6635559Abstract: The present invention provides methods and apparatus for creating insulating layers in Group III-V compound semiconductor structures having aluminum oxide with a substantially stoichiometric compositions. Such insulating layers find applications in a variety of semiconductor devices. For example, in one aspect, the invention provides vertical insulating layers separating two devices, such as photodiodes, formed on a semiconductor substrate from one another. In another aspect, the invention can provide such insulating layers as buried horizontal insulating layers of semiconductor devices.Type: GrantFiled: September 6, 2001Date of Patent: October 21, 2003Assignee: Spire CorporationInventors: Anton C. Greenwald, Nader Montazernezam Kalkhoran
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Patent number: 6620641Abstract: A GaN compound semiconductor laser includes an AlGaN buried layer which buries opposite sides of a ridge stripe portion formed on a p-type AlGaN cladding layer. The AlGaN buried layer is made by first patterning an upper part of the p-type AlGaN cladding layer and a p-type GaN contact layer into a ridge stripe configuration by using a SiO2 film as an etching mask, then growing the AlGaN buried layer non-selectively on the entire substrate surface to bury both sides of the ridge stripe portion under the existence of the SiO2 film on the ridge stripe portion, and thereafter selectively removing the AlGaN buried layer from above the ridge stripe portion by etching using the SiO2 film as an etching stop layer. Thus, the GaN compound semiconductor laser is stabilized in the transverse mode, intensified in output power, and improved in lifetime.Type: GrantFiled: June 17, 2002Date of Patent: September 16, 2003Assignee: Sony CorporationInventors: Takashi Yamaguchi, Toshimasa Kobayashi, Satoru Kijima, Takashi Kobayashi, Tsunenori Asatsuma, Takeharu Asano, Tomonori Hino
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Patent number: 6617235Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.Type: GrantFiled: March 29, 1996Date of Patent: September 9, 2003Assignee: Sumitomo Chemical Company, LimitedInventors: Yasushi Iyechika, Yoshinobu Ono, Tomoyuki Takada
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Patent number: 6593213Abstract: Systems and methods are described for synthesis of films, coatings or layers using electrostatic fields. A method includes applying an electrostatic field across a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.Type: GrantFiled: September 20, 2001Date of Patent: July 15, 2003Assignee: Heliovolt CorporationInventor: Billy J. Stanbery
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Publication number: 20030129820Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.Type: ApplicationFiled: October 16, 2002Publication date: July 10, 2003Inventors: Wladyslaw Walukiewicz, Kin M. Yu
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Patent number: 6586328Abstract: The metallization method of the invention uses an oxide-forming metal layer to improve adhesion and getter surface contamination or oxides. A high work function metal is then formed on the oxide-forming layer. An anneal is conducted to diffuse the high work function on metal through the oxide-forming layer. One or more metal cap layers may top the high work function metal to protect the high work function metal.Type: GrantFiled: June 5, 2000Date of Patent: July 1, 2003Assignee: The Board of Trustees of the University of IllinoisInventors: Ilesanmi Adesida, Ling Zhou
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Patent number: 6577006Abstract: An undoped GaN buffer layer, an n-type GaN layer and a p-type GaN layer are successively formed on a sapphire substrate, and a partial region from the p-type GaN layer to the n-type GaN layer is removed, to expose the n-type GaN layer. Ti films having a thickness of 3 to 100 Å and Pt films are successively formed on the p-type GaN layer and on the exposed upper surfaces of the n-type GaN layer. Consequently, a p electrode in ohmic contact with the p-type GaN layer and an n electrode in ohmic contact with the n-type GaN layer are formed without being alloyed by heat treatment.Type: GrantFiled: December 28, 1999Date of Patent: June 10, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Kiyoshi Oota, Nobuhiko Hayashi
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Patent number: 6573117Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.Type: GrantFiled: January 24, 2002Date of Patent: June 3, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Masanori Murakami, Yasuo Koide, Jun Ito
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Patent number: 6573194Abstract: An integrated circuit having an interconnect layer (104) that comprises a first barrier layer (106) and an aluminum-based layer (108) overlying the first barrier layer (106). An aluminum-nitride layer (112) is located on the surface of the aluminum-based layer (108). AlN layer (112) is formed by converting a native aluminum-oxide layer to AlN using a plasma with H2 and N2 supplied independently rather than supplied together in the form of ammonia.Type: GrantFiled: August 2, 2001Date of Patent: June 3, 2003Assignee: Texas Instruments IncorporatedInventors: Keith J. Brankner, Wei-Yan Shih
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Patent number: 6562646Abstract: A method for manufacturing a light-emitting device which using group III nitride group semiconductors and a quantum well structure, comprising forming a well layer (e.g. an InGaN layer), forming a cap layer on the well layer, the cap layer having almost the same compositions as the well layer at a temperature similar to that at which the well layer was formed. Further, and the cap layer is formed at a crystal growth rate which is faster than the crystal growth rate of the well layer and removing the cap layer using a thermal cracking (or decomposition) process during the temperature ramp up associated with the formation of the next group III nitride compound semiconductor layer. After the cap layer is removed, the group III nitride compound semiconductor layer is formed on the exposed well layer.Type: GrantFiled: May 24, 2001Date of Patent: May 13, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Hiroshi Watanabe, Naoki Shibata
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Patent number: 6562644Abstract: A semiconductor substrate comprises a semiconductor layer comprising a group III nitride as a main component. A scattering portion for scattering an incident beam of light incident on one plane of the semiconductor layer is provided on another plane or inside of the semiconductor layer.Type: GrantFiled: August 6, 2001Date of Patent: May 13, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Ishida, Masahiro Ogawa, Masaya Mannoh, Masaaki Yuri
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Patent number: 6555457Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.Type: GrantFiled: April 7, 2000Date of Patent: April 29, 2003Assignee: Triquint Technology Holding Co.Inventors: Gustav E. Derkits, Jr., William R. Heffner, Padman Parayanthal, Patrick J. Carroll, Ranjani C. Muthiah
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Patent number: 6552256Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.Type: GrantFiled: March 6, 2001Date of Patent: April 22, 2003Assignee: The Regents of the University of CaliforniaInventors: Ali Shakouri, Christopher J. LaBounty, John E. Bowers
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Patent number: 6541799Abstract: A Group-III nitride semiconductor light-emitting diode having an electrically conducting silicon (Si) single crystal substrate having on an upper surface thereof at least a light-emitting part having a pn-heterojunction structure composed of a Group-III nitride semiconductor, which light-emitting part is stacked via an intermediate layer composed of a metal or a semiconductor, the single crystal substrate having a back surface electrode on a back surface thereof, a surface electrode on an upper surface of the light-emitting part and a perforated part formed by eliminating the Si single crystal substrate in a region exclusive of the back surface electrode on the back surface of the single crystal substrate and a method of manufacturing thereof are disclosed.Type: GrantFiled: February 19, 2002Date of Patent: April 1, 2003Assignee: Showa Denko K.K.Inventor: Takashi Udagawa
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Patent number: 6531383Abstract: The invention provides a method for manufacturing a gallium nitride-based III-V group compound semiconductor device, which comprises the following steps: forming a semiconductor stacked structure over a substrate, wherein the semiconductor stacked structure comprises an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; etching the semiconductor stacked structure to expose a part of the n-type semiconductor layer; forming a first electrode on the n-type semiconductor layer, wherein the first electrode comprises an ohmic contact layer, a barrier layer, and a pad layer; performing an annealing process to lower the contact resistance between the first electrode and the n-type semiconductor layer and activate the p-type semiconductor layer at the same time; and forming a second electrode on the p-type semiconductor layer.Type: GrantFiled: September 27, 2000Date of Patent: March 11, 2003Assignee: Opto Tech CorporationInventor: Ching-ting Lee
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Publication number: 20030038294Abstract: A nitride semiconductor laser device of high reliability such that the width of contact between a p-side ohmic electrode and a p-type contact layer is precisely controlled. The device comprises a substrate, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer. All the layers are formed in order on the substrate. A ridge part including the uppermost layer of the p-type nitride semiconductor layer of the p-type nitride semiconductor layer i.e., a p-type contact layer is formed in the p-type nitride semiconductor layer. A p-side ohmic electrode is formed on the p-type contact layer of the top of the ridge part. A first insulating film having an opening over the top of the ridge part covers the side of the ridge part and the portion near the side of the ridge part. The p-side ohmic electrode is in contact with the p-type contact layer through the opening. A second insulating film is formed on the first insulating film.Type: ApplicationFiled: August 15, 2002Publication date: February 27, 2003Inventor: Masahiko Sano
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Patent number: 6518159Abstract: An object of the present invention is provide an InGaAlP-based semiconductor layer of a good crystal quality at a higher temperature up to a re-evaporating temperature by MBE process. A buffer layer made of GaAs and a buffer layer made of GaInP are formed by MBE (molecular beam epitaxy) process on a GaAs substrate having a facet, which is to be a main facet, inclined by &thgr; in [011] direction from (100) facet. Then semiconductor layers are formed by MBE process so as to include cladding layers having a bandgap Egc and an AlGaInP active layer having a bandgap Ega which is adjusted by an amount of III-group element to be represented by Ega<Egc. The semiconductor laser device has a ridge stripe extending in [01-1] direction.Type: GrantFiled: October 19, 2000Date of Patent: February 11, 2003Assignee: Sharp Kabushiki KaishaInventor: Atsuo Tsunoda
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Publication number: 20030003704Abstract: An underlayer made of a III-V semiconductor compound is formed on a given substrate, and a CrSb compound is epitaxially grown on the underlayer by means of MBE method to fabricate a zinc blende type CrSb compound.Type: ApplicationFiled: June 18, 2002Publication date: January 2, 2003Applicant: TOHOKU UNIVERSITYInventors: Hideo Ohno, Fumihiro Matsukura
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Patent number: 6500747Abstract: A method of manufacturing a semiconductor substrate is provided. The method includes a first step of forming a rugged portion in a GaN substrate, and a second step of forming a GaN thin film on the GaN substrate at a lateral growth rate fast enough to cover the GaN thin film vertically grown with the GaN thin film laterally grown, so that the rugged portion is covered with the GaN thin film.Type: GrantFiled: October 12, 2001Date of Patent: December 31, 2002Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Won-seok Lee, Ok-hyun Nam, Cheol-soo Sone
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Patent number: 6500689Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.Type: GrantFiled: March 29, 2001Date of Patent: December 31, 2002Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Masanori Murakami, Yasuo Koide, Jun Ito
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Publication number: 20020197841Abstract: An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity.Type: ApplicationFiled: June 4, 2002Publication date: December 26, 2002Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
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Publication number: 20020197825Abstract: To provide a semiconductor substrate of a group III nitride with low defect density and little warp, this invention provides a process comprising such steps of:Type: ApplicationFiled: March 26, 2002Publication date: December 26, 2002Inventors: Akira Usui, Masatomo Shibata, Yuichi Oshima
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Publication number: 20020182840Abstract: Method for deoxidizing and passivating, by sulfidation, a surface of a III-V compound semiconductor material undergo strong oxidation in the presence of oxygen, wherein the surface to be passivated is immersed in a dilute aqueous solution containing sulfide ions with a concentration of between about 10−1M and 10−7M.Type: ApplicationFiled: May 30, 2002Publication date: December 5, 2002Inventors: Dominique Lorans, Bruno Canava, Arnaud Etcheberry, Michel Herlem, Jacky Vigneron
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Publication number: 20020182839Abstract: A method for fabricating a Group III nitride semiconductor substrate according to the present invention includes the steps of: (a) preparing a substrate; (b) forming, on the substrate, a first semiconductor layer composed of a Group III nitride semiconductor; (c) forming, on the first semiconductor layer, a heat diffusion suppressing layer lower in thermal conductivity than the first semiconductor layer; (d) forming, on the heat diffusion suppressing layer, a second semiconductor layer composed of a Group III nitride semiconductor; and (e) irradiating the first semiconductor layer through the substrate with a light beam transmitted by the substrate and absorbed by the first semiconductor layer to decompose the first semiconductor layer.Type: ApplicationFiled: April 10, 2002Publication date: December 5, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masahiro Ogawa, Masahiro Ishida, Satoshi Tamura, Shinichi Takigawa
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Patent number: 6486050Abstract: A method for manufacturing III-nitride semiconductor devices is disclosed. The method employs oxidation and sulfurated treatment to reduce the specific contact resistance between metal and p-type III-nitride semiconductors. The method includes surface treatment of p-type III-nitride semiconductors using (NH4)2Sx solution to remove the native oxide from their surface; evaporating metal layer onto the surface-treated p-type III-nitride semiconductors; and then alloy processing the metals and the p-type III-nitride semiconductor with thermal alloy treatment. The method may further include a pre-oxidation step prior to the sulfurated treatment. In this way, ohmic contact can be formed between the metal layer and the p-type III-nitride semiconductors.Type: GrantFiled: May 31, 2002Date of Patent: November 26, 2002Assignee: Opto Tech CorporationInventor: Ching-ting Lee