Abstract: A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds.

Abstract: A GaAs substrate is reduced to a thickness of no more than 30 &mgr;m, preferably no more than 10 &mgr;m, by grinding. The substrate thus has the characteristics of a film, which prevents breakage of the substrate. A metallization can be provided on the rear of the substrate. The thermal characteristics are improved, because the heat can be transferred to the rear side of the substrate more effectively. Because of the smaller dimensions and good heat dissipation, smaller housings can be utilized. Extremely small holes (micro via holes) are etched into the substrate and provided with via hole fillers.

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Mixed technology structures are provided in which a microprocessor is formed entirely in a monocrystalline compound semiconductor material layer overlying the silicon substrate.

Abstract: A composite semiconductor including silicon and compound semiconductor, and having a silicate layer for promoting layer-by-layer monocrystalline growth. Silicon may be introduced to react with the monocrystalline oxide layer to form the silicate layer. During the fabrication process, the thickness of the amorphous oxide layer may be increased by suitable methods, such as annealing or oxygen diffusion.

Abstract: A photodetector comprising a gallium nitride substrate, at least one active layer disposed on the substrate, and a conductive contact structure affixed to the active layer and, in some embodiments, the substrate. The invention includes photodetectors having metal-semiconductor-metal structures, P-i-N structures, and Schottky-barrier structures. The active layers may comprise Ga1-x-yAlxInyN1-z-wPzAsw, or, preferably, Ga1-xAlxN. The gallium nitride substrate comprises a single crystal gallium nitride wafer and has a dislocation density of less than about 105 cm−2. A method of making the photodetector is also disclosed.

Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.

Abstract: Composite semiconductor structures and methods are provided for communications systems, specifically, those utilizing RF signals. Antenna switches, and amplifiers in receiver and transmitter sections of the communications systems are shown that are fabricated within a compound semiconductor layer of a composite semiconductor structure is integrated with support circuitry in a non-compound semiconductor substrate. Support circuitry that may be integrated include negative voltage generation circuitry, drain current protection circuitry, and voltage regulation circuitry.

Abstract: Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of a first conductive type formed in a part of a compound semiconductor substrate having a semi-insulating layer. The semiconductor laminated structure includes at least an active layer including a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed. A source electrode is formed on the semiconductor laminated structure, being electrically connected to the charge absorption layer.

Abstract: The electrode structure of the invention includes a p-type AlxGayIn1−x−yN (0≦x≦1, 0≦y≦1, x+y≦1) semiconductor layer and an electrode layer formed on the semiconductor layer. In the electrode structure, the electrode layer contains a mixture of a metal nitride and a metal hydride.

Abstract: A main surface of a base substrate of sapphire is selectively formed an irregular region on the main surface. Then, a semiconductor layer of gallium nitride is grown to fill recessed portions in the irregular region of the base substrate and make the upper surface even. Then, a laser beam is irradiated upon the interface between the semiconductor layer and the irregular region of the base substrate to separate the semiconductor layer from the base substrate. As a result, a nitride semiconductor substrate is produced from the semiconductor layer.

Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.

Abstract: A method of fabricating a MOSEFT device, which is suitable for fabricating an III-V group semiconductor device. A substrate comprises a buffer layer and a channel layer, wherein silicon oxide is formed on the channel layer by a liquid phase deposition method (LPD) to control the parameters of growth solution. A silicon oxide insulating layer that is formed on the channel layer has a thickness of approximately 40 Å, wherein the silicon oxide insulating layer is used as a gate oxide layer. A source, a drain and a gate are formed on the gate oxide layer. The LPD process is performed in a temperature range from room temperature to 60° C. Thus, the low temperature of the LPD technique will not lead to a negative heat effect on other fabrications or on the wafer, therefore the low temperature will not cause thermal stress, dopant redistribution, dopant diffusion or material interaction, for example.

Abstract: A method for fabricating a quantum dot infrared photodetector by using molecular beam epitaxy is provided. The method includes steps of growing a first gallium arsenide layer as a buffer layer on a gallium arsenide substrate, growing a first undoped aluminum gallium arsenide layer as a blocking layer on the first gallium arsenide layer, growing a quantum dot structure layer on the first undoped aluminum gallium arsenide layer at a specific temperature, and growing a second gallium arsenide layer as a contact layer on the quantum dot structure layer.

Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.

Abstract: An electrode of a metal, which is one of Group IV and VI elements, is deposited on an n-type InxAlyGa1−x−yN layer. Alternatively, after an electrode material of carbon, germanium), selenium, rhodium, tellurium, iridium, zirconium, hafnium, copper, titanium nitride, tungsten nitride, molybdenum or titanium silicide, is deposited on an n-type InxAlyGa1−x−yN layer or a p-type InxAlyGa1−x−yN layer, an impurity for increasing the carrier concentration of the semiconductor layer is ion-implanted, and the annealing is carried out. Thus, it is possible to provide a light emitting semiconductor device, which has a low contact resistance and a sufficient bond strength to the InxAlyGa1−x−yN layer while maintaining the crystallinity of the InxAlyGa1−x−yN layer.

Abstract: In a semiconductor device such as GaN semiconductor laser having an electrode formed on a nitride III-V compound semiconductor layer containing at least Ga, such as GaN layer, at least a part of the electrode in contact with the nitride III-V compound semiconductor layer is made of a &ggr;-GaNi alloy or a &ggr;′-GaNi alloy. The electrode is made by first stacking the &ggr;-GaNi alloy layer or &ggr;′-GaNi alloy layer, or its component elements, on the nitride III-V compound semiconductor layer, and then annealing it at a temperature not lower than 680° C., or by stacking any of them on the nitride-compound III-V compound semiconductor layer heated to a temperature not lower than 680° C. At least a part of the electrode in contact with the nitride III-V compound smiconductor layer may be made of an alloy of Ga and at least one kind of element selected from the group consisting of Pt, Ag, Pd, Mg, Hf, Al, Cr, Ti, Mo, W, Zr, Si and Ge.

Abstract: The semiconductor light emitting element of the present invention includes: a compound semiconductor substrate having a first conductivity type; a light emitting layer; a compound semiconductor interface layer having a second conductivity type and not containing Al; and a current diffusion layer having the second conductivity type and being made of a compound semiconductor not containing Al.

Abstract: A light emitting diode (LED) is disclosed. An emitted light can be prevented from being absorbed by a substrate by using a bragg reflector layer with high reflectivity. The present invention provides a bragg reflector layer comprising a plurality of high aluminum-contained AlGaAs/AlGaInP layers or high aluminumcontained AlGaAs/low aluminum-contained AlGaInP layers formed on the substrate before the epitaxial structure of the light emitting diode being formed. Since the high aluminum-contained AlGaAs is oxidized and formed an oxide of a lower refraction index, the reflectivity and high reflection zones of the oxidized bragg reflector layer are much larger. According to the electrical insulation characteristic of the oxide, the bragg reflector layer can limit the current within the oxidized regions of high aluminum-contained AlGaAs layer. Therefore, the aforementioned light emitting diode structure has a higher brightness than the conventional light emitting diode.

Abstract: Compliant substrates include a compliant single crystal layer formed on an amorphous buffer layer, which is formed on a single crystal base layer. The compliant single crystal layer can be used as a template to support the growth of one or more lattice mismatched layers on the compliant substrate. Various electronic and optoelectronic devices including, for example, photodetectors, long-wavelength semiconductor light-emitting devices, short-wavelength semiconductor light-emitting devices, optical modulators and transistors, can be formed on the compliant substrates. The compliant substrates can be produced by epitaxially forming an intermediate single crystal layer, that can be treated to convert it to an amorphous layer, between two single crystal layers, and treating the intermediate single crystal layer to form an amorphous buffer layer.

Abstract: Multi-metallic films are prepared from multi-metallic mixtures of metalloamide compounds. The mixtures are subjected to vaporization to form a multi-metallic vapor having defined and controllable stoichiometry. The multi-metallic vapor is then transferred to a chemical vapor deposition chamber, with or without the presence of a reactant gas, to form the multi-metallic film. Multi-metallic nitride, oxide, sulfide, boride, silicide, germanide, phosphide, arsenide, selenide, telluride, etc. films may be prepared by appropriate choice of metalloamide compounds and reactant gas(es).

Abstract: The subject invention pertains to a method and device for producing large area single crystalline III-V nitride compound semiconductor substrates with a composition AlxInyGa1-x-y N (where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1). In a specific embodiment, GaN substrates, with low dislocation densities (˜107 cm2) can be produced. These crystalline III-V substrates can be used to fabricate lasers and transistors. Large area free standing single crystals of III-V compounds, for example GaN, can be produced in accordance with the subject invention. By utilizing the rapid growth rates afforded by hydride vapor phase epitaxy (HVPE) and growing on lattice matching orthorhombic structure oxide substrates, good quality III-V crystals can be grown. Examples of oxide substrates include LiGaO2, LiAlO2, MgAlScO4, Al2MgO4, and LiNdO2. The subject invention relates to a method and apparatus, for the deposition of III-V compounds, which can alternate between MOVPE and HVPE, combining the advantages of both.

Abstract: A material with reduced surface defects includes a defect filter layer on an underlying material. The defect filter reduces dislocations and defects present in an underlying material. The defect filter include islands of one material formed on the underlying material and a continuous layer of a second material over the islands. The pair of layers is repeated a plurality of times to reduce the number of defects emanating from the underlying material.

Abstract: A method of forming a low temperature metal bond includes the step of providing a donor substrate, such as a crystallographically oriented donor substrate, including a sapphire donor substrate or a MgO donors substrate. The donor substrate may also be quartz or fused silica. A thin film is grown on a surface of the donor substrate. The thin film may be an oxide, nitride or Perovskite. The invention may be implemented using nitride thin films, including AlN, GaN, InN, and all of their solid solutions, alloys, and multi-layers. An acceptor substrate is then produced. The acceptor substrate may be Si, GaAs, polymers, such as polyimide, or stainless steel for use in microrobotics. A multi-layer metal bond interface for positioning between the thin film and the acceptor substrate is then selected.

Abstract: A nitride based III-V compound semiconductor doped with a p-type impurity is formed on a substrate made from sapphire. The substrate is then placed between a pair of RF electrodes, and a radio frequency field is applied between the RF electrodes. With this operation, electrons present in the compound semiconductor attack the bonding between the p-type impurity and hydrogen, to cut the bonding. The hydrogen atoms thus dissociated are released from the compound semiconductor, to thereby activate the p-type impurity. In this case, it is not required to heat the compound semiconductor by a heater or the like.

Abstract: A first III-V semiconductor wafer is bonded to a second III-V semiconductor wafer, e.g. by thermal fusion. The {110} crystal plane of the III-V semiconductor wafer is displaced angularly relative to the {110} crystal plane of the second III-V semiconductor wafer. Because of this, the tendency of the bonded wafer to break is reduced and many backside processes can be moved to front side and results in a robust device manufacturing process.

Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.

Abstract: A method of fabricating on ohmic metal electrode. The p-type ohmic metal electrode according to the present invention employs Ru and RuOx as the cover layer in lieu of conventional Au, in order to effectively prevent penetration by contaminants in the air, such as oxygen, carbon, and H2O, and to form a stable metal-Ga intermetallic phase at the junction between the contact layer and the nitride compound semiconductor. The n-type ohmic metal electrode according to the present invention employs Ru as the diffusion barrier in lieu of conventional Ni or Pt, in order to effectively form a metal-nitride phase such as titanium nitride that contributes to superior ohmic characteristics during the heating process, without destruction of the junction. According to the present invention, it is possible to fabricate devices having superior electrical, optical, and thermal characteristics compared with conventional devices.

Abstract: There is provided a hetero-junction field effect transistor including (a) a first semiconductor layer composed of InP, (b) a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a smaller electron affinity than that of the first semiconductor layer, (c) a third semiconductor layer formed on the second semiconductor layer, the third semiconductor layer having a greater electron affinity than that of the second semiconductor layer, and being formed at a surface thereof with an opening, the third semiconductor layer being composed of InP, (d) source and drain electrodes formed on the third semiconductor layer, and (e) a gate electrode formed on the second semiconductor layer in the opening of the third semiconductor layer. In accordance with the hetero-junction field effect transistor, it is possible to enhance noise characteristic and high power characteristic.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: When a device using GaN semiconductors is made on a hard and chemically stable single-crystal substrate such as sapphire substrate or SiC substrate, a semiconductor device and its manufacturing method ensure high-power output or high-frequency operation of the device by thinning the substrate or making a via hole in the substrate. When a light emitting device using GaN semiconductors is made on a non-conductive single-crystal substrate such as sapphire substrate, the semiconductor device and its manufacturing method reduce the operation voltage of the light emitting device by making a via hole to the substrate. More specifically, after making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less.

Abstract: Method for forming a Schottky contact in a semiconductor device includes a step of preparing an n type GaN group compound semiconductor layer, such as AlxGa1-xN and InxGa1-xN. At least one metal layer including a ruthenium component layer is formed on the n type GaN group compound semiconductor layer as a rectifying junction metal. The rectifying junction metal may be used as a gate of a field effect transistor, or an electrode of a Schottky diode. The ruthenium oxide has a low cost, is stable to heat and chemical, and has excellent electric characteristics. The application of the ruthenium oxide to the rectifying junction metal enhances performances, such as UV ray detection, of electronic devices and optical devices operable at an elevated temperature.

Abstract: The present invention proposes a method of producing a gallium nitride-based III-V Group compound semiconductor device. First, beryllium ions are diffused into the p-type layer of gallium nitride to increase hole mobility. Contacts are then added in subsequent procedures, thereby forming contacts having low-impedance ohmic contact layers.

Abstract: A high electron mobility transistor comprises a GaN-based electron accumulation layer formed on a substrate, an electron supply layer formed on the electron accumulation layer, a source electrode and a drain electrode formed on the electron supply layer and spaced from each other, a gate electrode formed on the electron supply layer between the source and drain electrodes, and a hole absorption electrode formed on the electron accumulation layer so as to be substantially spaced from the electron supply layer. Since the hole absorption electrode is formed on the electron absorption layer in order to prevent holes generated by impact ionization from being accumulated on the electron accumulation layer, a kink phenomenon is prevented. Good drain-current/voltage characteristics are therefore obtained. A high power/high electron mobility transistor is provided with a high power-added efficiency and good linearity.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: Provided is a method and apparatus for the production of a semiconductor device, the method and the apparatus producing a high quality and highly functional semiconductor device efficiently at low temperatures in a short time and also a high quality and highly functional semiconductor device produced by the method and apparatus. The semiconductor device is produced by forming a film of a nitride compound on a substrate having heat resistance at 600° C. or less, wherein the nitride compound includes one or more elements selected from group IIIA elements of the periodic table and a nitrogen atom and produces photoluminescence at the band edges at room temperature.

Abstract: Embodiments of the present invention pendeoepitaxially grow sidewalls of posts in an underlying gallium nitride layer that itself is on a sapphire substrate, at high temperatures between about 1000° C. and about 1100° C. and preferably at about 1100° to reduce vertical growth of gallium nitride on the trench floor from interfering with the pendeoepitaxial growth of the gallium nitride sidewalls of the posts. Thus, widely available sapphire substrates may be used for pendeoepitaxial of gallium nitride, to thereby allow reduced cost and/or wider applications for gallium nitride devices. More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor.

Abstract: A structure includes a metal nitride film of the form MN, where M is selected from the group consisting of Ga, In, AlGa, AlIn, and AlGaIn. The structure has at least one electrically conductive metal region that is formed within and from the metal nitride film by a thermal process driven by absorption of light having a predetermined wavelength. Single films comprised of AlN are also within the scope of this invention, wherein an Al trace or interconnect is formed by laser radiation of wavelength 248 nm so as to contact circuitry that exists under the film. Multilayered stacks of films are also within the scope of the teachings of this invention.

Abstract: A p-contact that comprises a contact layer of a p-type Group III-nitride semiconductor having an exposed surface and an electrode layer of palladium (Pd) located on the exposed surface of the contact layer. The p-contact is made by providing a p-type Group III-nitride semiconductor contact layer having an exposed surface, and depositing an electrode layer of palladium on the exposed surface of the contact layer. Preferably, the p-contact is annealed for a prolonged annealing time after the electrode layer is deposited, and the exposed surface of the contact layer is etched using hydrofluoric acid (HF) before depositing the electrode layer.

Abstract: A method for manufacturing a group III-V compound semiconductor represented by the general formula InxGayAlzN (where x+y+z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1) by metalorganic vapor phase epitaxy method is provided. The group III-V compound semiconductor has a semiconductor layer consisting of a p-type dopant-nondoped layer, and a semiconductor layer including a p-type dopant-doped layer. In the method, a reactor for growing the semiconductor layer consisting of a p-type dopant-nondoped layer and a reactor for doping a p-type dopant are mutually different.

Abstract: An integrated circuit chip (10) includes a substrate (12), a plurality of transistors (16) provided in the substrate (12), a circuit pattern (14) provided on a top surface of the substrate (12) and a metal layer (42) comprising at least two metals in substantially eutectic proportions provided on a bottom surface of the substrate, the bottom surface of the metal layer (42) being exposed. The integrated circuit chip (10) can be attached to a farther substrate, e.g., a housing, using automated attachment techniques. The chip (10) can be attached to the housing by picking up the integrated circuit chip (10) with the metal layer (42) provided on the bottom surface thereof and placing the integrated circuit chip (10) onto a housing so the bottom surface of the integrated circuit chip (10) faces the housing with the metal layer (42) there between; and then heating the metal layer (42) to a temperature above its eutectic temperature to melt the metal layer and attach the integrated circuit chip (10) to the housing.

Abstract: The subject invention pertains to a method and device for producing large area single crystalline III-V nitride compound semiconductor substrates with a composition AlxInyGal-x-y N (where O≦x≦1, 0≦y≦1, and 0≦x+y≦1). In a specific embodiment, GaN substrates, with low dislocation densities (˜107 cm2) can be produced. These crystalline III-V substrates can be used to fabricate lasers and transistors. Large area free standing single crystals of III-V compounds, for example GaN, can be produced in accordance with the subject invention. By utilizing the rapid growth rates afforded by hydride vapor phase epitaxy (HVPE) and growing on lattice matching orthorhombic structure oxide substrates, good quality III-V crystals can be grown. Examples of oxide substrates include LiGaO2, LiAlO2, MgAlScO4, Al2MgO4, and LiNdO2. The subject invention relates to a method and apparatus, for the deposition of III-V compounds, which can alternate between MOVPE and HVPE, combining the advantages of both.

Abstract: A semi-insulating bulk single crystal of silicon carbide is disclosed that has a resistivity of at least 5000 &OHgr;-cm at room temperature and a concentration of deep level trapping elements that is below the amounts that will affect the resistivity of the crystal, preferably below detectable levels. A method of forming the crystal is also disclosed, along with some resulting devices that take advantage of the microwave frequency capabilities of devices formed using substrates according to the invention.

Abstract: A method of forming a cobalt germanosilicide film is described. According to the present invention a silicon germanium alloy is formed on a substrate. A cobalt film is then formed on the silicon germanium alloy. The substrate is then heated to a temperature of greater than 850° C. for a period of time less than 20 seconds to form a cobalt germanium silicide film.

Abstract: A first surface layer made of compound semiconductor material is defined in a surface area of a substrate. A first intermediate layer is formed on the surface layer, the first intermediate layer being made of compound material having Ga as a III group element and S as a VI element and having a thickness of at least two monolayers or thicker. A first electrode is formed on the first intermediate layer, being electrically connected to the first surface layer with an ohmic contact.

Abstract: As will be described in more detail hereinafter, there is disclosed herein a titanium nitride diffusion barrier layer and associated method for use in non-silicon semiconductor technologies. In one aspect of the invention, a semiconductor device includes a non-silicon active surface. The improvement comprises an ohmic contact serving to form an external electrical connection to the non-silicon active surface in which the ohmic contact includes at least one layer consisting essentially of titanium nitride. In another aspect of the invention, a semiconductor ridge waveguide laser is disclosed which includes a semiconductor substrate and an active layer disposed on the substrate. A cladding layer is supported partially on the substrate and partially on the active layer. The cladding layer includes a ridge portion disposed in a confronting relationship with the active region.

Abstract: The present invention relates to methods for controlling the etching rate of CoSi.sub.2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schottky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.

Abstract: Methods are disclosed for forming Group III--arsenide-nitride semiconductor materials. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V crystals varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V crystals can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.

Abstract: An electrode for a Group III nitride compound semiconductor having p-type conduction that has a double layer structure. The first metal electrode layer comprising, for example, nickel (Ni) and the second metal electrode layer comprising, for example, gold (Au). The Ni layer is formed on the Group III nitride compound semiconductor having p-type conduction, and the Au layer is formed on the Ni layer. Heat treatment changes or reverses the distribution of the elements Ni and Au. Namely, Au is distributed deeper into the Group III nitride compound semiconductor than is Ni. As a result, the resistivity of the electrode is lowered and its ohmic characteristics are improved as well as its adhesive strength.

Abstract: A method for making a magnetoresistive sensing device including depositing an ultrathin active film responsive to changes in magnetic field energy onto a compliant layer of periodic table group III-V semiconductor material on a semiconductor substrate wafer, the compliant layer being capable of retaining strain energy resulting from the layering semiconductor materials with different lattice constants. This method produces a battery operable ultrathin device highly sensitive to changes in magnetic field flux.