Abstract: III-nitride material structures including silicon substrates, as well as methods associated with the same, are described. Parasitic losses in the structures may be significantly reduced which is reflected in performance improvements. Devices (such as RF devices) formed of structures of the invention may have higher output power, power gain and efficiency, amongst other advantages.

Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.

Abstract: A structure including at least one layer of germanium formed on a surface of a ceramic substrate is provided. The layer of germanium has a thickness of not larger than 10 microns and includes grains having grain size of at least 0.05 mm. A structure including at least one layer of germanium formed on a surface of a ceramic substrate and having at least one capping layer formed on a surface of the layer of germanium is also provided. In addition, a method of forming a thin film germanium structure is provided including forming at least one layer of germanium on a surface of a ceramic substrate, then forming at least one capping layer on a surface of the layer of germanium, followed by heating and then cooling the layer of germanium.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another.

Abstract: The invention, called hypercontacting, achieves a very high level of activated doping at an exposed surface region of a compound semiconductor. This enables production of low resistance ohmic contacts by creating a heavily doped region near the contact. Such region lowers the contact's tunneling barrier by decreasing the extent of the depletion region at the contact, thereby reducing resistance.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A fabrication method of VCSEL is used to form a contact electrode on a VCSEL in a resonance cavity. A heavily doped layer is formed in a resonance cavity where the light intensity is the weakest. A Bragg reflector is etched while the etching stop point being above the heavily doped layer. Dopants are doped to form a high-carrier-concentration ohmic channel as a connection between an electrode and the heavily doped layer. Thereby, a contact electrode is formed on the VCSEL structure in the resonance cavity without the need of high etching precision.

Abstract: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.

Abstract: The present invention relates to a process for producing an epitaxial layer of gallium nitride (GaN) as well as to the epitaxial layers of gallium nitride (GaN) which can be obtained by said process. Such a process makes it possible to obtain gallium nitride layers of excellent quality by (i) forming on a surface of a substrate, a film of a silicon nitride of between 5 to 20 monolayers, functioning as a micro-mask, (ii) depositing a continuous gallium nitride layer on the silicon nitride film at a temperature ranging from 400 to 600° C., (iii) after depositing the gallium nitride layer, annealing the gallium nitride layer at a temperature ranging from 950 to 1120° C. and (iv) performing an epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride.

Abstract: Provided is a method of manufacturing compound single crystals by epitaxially growing a compound single crystal layer differing from the substrate in which the planar defects generated in the crystal that is epitaxially grown are reduced. The method of manufacturing compound single crystals in which a compound single crystalline layer differing from a compound single crystalline substrate is epitaxially grown on the surface of said substrate. Plural undulations extending in a single direction are present on at least a portion of the surface of said substrate, and in that said undulations are provided in such a manner that as said compound single crystalline layer grows, the defects that grow meet each other.

Abstract: A method for manufacturing a group III nitride compound semiconductor device includes irradiating a surface of a wafer with ultraviolet rays to thereby clean a resist residue from the surface of the wafer, the surface including a group III nitride compound semiconductor. The ultraviolet rays cause a reaction of oxygen molecules to form stimulated oxygen atoms having a strong oxidative power at the surface.

Abstract: The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into an electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength.

Abstract: A method of manufacturing a semiconductor device having a field effect transistor with improved current driving performance (increase of drain current) includes the steps of ion implanting a group IV element from the main surface to the inside of a silicon layer serving as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer serving as a semiconductor substrate so as to form a semiconductor region which is aligned with the gate electrode.

Abstract: A p-type ohmic electrode in a gallium nitride based(GaN based) optical device and a fabrication method thereof. The p-type ohmic electrode in a GaN based optical device is fabricated using a rutile structure transition metal layer, such as an Ru, Ir or Os layer, or an oxide layer thereof, or using a double layer comprised of an Ru layer as a base layer and an Ni layer, an ITO layer or an AuO layer on the Ru layer. Thus, the p-type ohmic electrode is good in light transmittance and is thermally stable while having low contact resistance with the p-GaN layer.

Abstract: Methods of preparing Group IVA and Group VIA organometallic compounds, particularly Group IVA organometallic compounds, are provided. Such manufacturing methods employ an amine and/or phosphine catalyst in a transalkylation step and may be performed in a batch, semi-continuous or continuous manner.

Abstract: The active region of a long-wavelength light emitting device is made by providing an organometallic vapor phase epitaxy (OMVPE) reactor, placing a substrate wafer capable of supporting growth of indium gallium arsenide nitride in the reactor, supplying a Group III–V precursor mixture comprising an arsenic precursor, a nitrogen precursor, a gallium precursor, an indium precursor and a carrier gas to the reactor and pressurizing the reactor to a sub-atmospheric elevated growth pressure no higher than that at which a layer of indium gallium arsenide layer having a nitrogen fraction commensurate with light emission at a wavelength longer than 1.2 ?m is deposited over the substrate wafer.

Abstract: A method for manufacturing a GaN-based light-emitting diode (LED) is provided with the following steps of: providing a substrate; forming a GaN semiconductor epitaxy layer on the substrate, the GaN semiconductor epitaxy layer further including an n-type GaN contact layer, a light-emitting layer and a p-type GaN contact layer; forming a digital penetration layer on the p-type GaN contact layer; using a multi-step dry etching method to etch the digital penetration layer, the p-type GaN contact layer, the light-emitting layer to form an n-metal forming area, etching terminating at the light-emitting layer; forming a first ohmic contact electrode on the digital penetration layer for a p-type ohmic contact layer and a second ohmic contact electrode on the n-metal forming area for an n-type ohmic contact layer; and finally, forming pads on both first and second ohmic contact electrodes.

Abstract: A method of forming a high-power, high-frequency device in wide bandgap semiconductor materials with reduced junction temperature, higher power density during operation and improved reliability at a rated power density is disclosed, along with resulting semiconductor structures and devices. The method includes adding a layer of diamond to a silicon carbide wafer to increase the thermal conductivity of the resulting composite wafer, thereafter reducing the thickness of the silicon carbide portion of the composite wafer while retaining sufficient thickness of silicon carbide to support epitaxial growth thereon, preparing the silicon carbide surface of the composite wafer for epitaxial growth thereon, and adding a Group III nitride heterostructure to the prepared silicon carbide face of the wafer.

Abstract: A semiconductor device having a silicon single crystal substrate and a boron phosphide semiconductor layer containing boron and phosphorus as constituent elements on a surface of the silicon single crystal substrate is disclosed. The surface of the silicon single crystal substrate is a {111} crystal plane inclined at an angle of 5.0° to 9.0° toward a <110> crystal azimuth.

Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x?0.011 and x?450 ?m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H?70×10?4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos?1(1?HCZ), where C (cm?1) is the proportionality constant when the radius of curvature of the substrate ? (cm) is expressed as 1/?=CZ.

Abstract: A flip-chip LED device (10) includes a plurality of group III-nitride semiconductor layers (22) defining a p/n junction and including a top p-type group III-nitride layer (28), and a p-contact (30, 30?, 30?) for flip-chip bonding the top p-type group III-nitride layer. The p-contact includes an aluminum layer (32) disposed on the top p-type group III-nitride layer (28), and an interface layer (40, 66, 72, 80) disposed between the aluminum layer and the top p-type group III-nitride layer. The interface layer reduces a contact resistance between the aluminum layer (32) and the top p-type group III-nitride layer (28). The interface layer comprises one or more group III-nitride layers.

Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.

Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.

Abstract: The present invention provides a method for growing group-III nitride semiconductor heteroepitaxial structures on a silicon (111) substrate by using a coincidently matched multiple-layer buffer that can be grown on the Si(111) substrate. The coincidently matched multiple-layer buffer comprises a single-crystal silicon nitride (Si3N4) layer that is formed in a controlled manner by introducing reactive nitrogen plasma or ammonia to the Si(111) substrate at a suitably high temperature. Then, an AlN buffer layer or other group-III nitride buffer layer is grown epitaxially on the single-crystal silicon nitride layer. Thereafter, the GaN epitaxial layer or group-III semiconductor heteroepitaxial structure can be grown on the coincidently matched multiple-layer buffer.

Abstract: A method of fabricating a nitride semiconductor includes the steps of forming a nitride semiconductor doped with a p-type impurity, treating the surface of the nitride semiconductor in an atmosphere containing active oxygen to remove carbon remaining on the surface and form an oxide film thereon, and activating the p-type impurity to turn the conductive type of the nitride semiconductor into a p-type. Since carbon remaining on the surface of the nitride semiconductor is removed and the oxide film is formed thereon, the surface of the nitride semiconductor is prevented from being deteriorated by the activating treatment and the rate of activating the p-type impurity is enhanced. As a result, it is possible to reduce the contact resistance of the nitride semiconductor with an electrode and, hence, the variation in characteristics of the nitride semiconductor.

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013?1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface.

Abstract: Disclosed are methods of preparing monoalkyl Group VA metal dihalide compounds in high yield and high purity by the reaction of a Group VA metal trihalide with an organo lithium reagent or a compound of the formula RnM1X3?n, where R is an alkyl, M1 is a Group IIIA metal, X is a halogen and n is an integer fro 1 to 3. Such monoalkyl Group VA metal dihalide compounds are substantially free of oxygenated impurities, ethereal solvents and metallic impurities. Monoalkyl Group VA metal dihydride compounds can be easily produced in high yield and high purity by reducing such monoalkyl Group VA metal dihalide compounds.

Abstract: A GaN light emitting diode for flip-chip bonding, with sufficient bonding area, optimized electrode arrangement, and improved brightness and reliability, includes n-electrodes and a p-electrode which are formed as stripes. The n-electrodes are positioned at equal distances from the p-electrode and arranged in parallel, thus the electric current is not concentrated into a predetermined portion, but uniformly flows through the light emitting diode without reducing a light emitting area.

Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050° C. or less.

Abstract: In the process for producing low-defect semiconductor layers based on III-V nitride semiconductor material, a substrate (1) made from a material which is not based on III-V nitride semiconductors is provided, and then a mask layer (2) is applied to the substrate in order to form unmasked regions (2c) and masked regions (2a, 2b) on the substrate. Then, starting from the unmasked regions (2c) of the substrate (1), the III-V nitride semiconductor layer (3) is grown. To avoid the formation of stress-induced cracks during the cooling phase from the growth temperature to room temperature, the mask layer (2) is formed on the substrate (1) in such a manner that some of the masked regions (2b) are wide enough to prevent the III-V nitride semiconductor layer (3) from growing together over these wide masked regions (2b), whereas the III-V nitride semiconductor layer does grow together only over the other, narrow masked regions (2a).

Abstract: A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.

Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0?u, v, w?1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0?x, y, z?1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.

Abstract: A layered article and method for forming the same includes a single crystal silicon substrate, a silicon oxynitride layer (SixNyOz) disposed on the silicon substrate, and a single crystal GaN layer disposed on the oxynitride layer. The silicon oxynitride layer can be formed by nitridation of a native oxide layer. One or more integrated electronic circuits and/or integrated optical or optoelectronic devices can be built on the article.

Abstract: The method of the invention for producing a Group III nitride compound semiconductor, employing an etchable substrate which is produced from a material other than the Group III nitride compound semiconductor, includes stacking one or more layers of the Group III nitride compound semiconductor on one face of the substrate and etching the other face of the substrate while stacking one or more semiconductor layers or after completion of stacking one or more semiconductor layers, to thereby reduce the thickness of most of the substrate. The apparatus of present invention for producing a semiconductor through vapor phase growth, contains a substrate for vapor-phase-growing the semiconductor; a source-supplying system for supplying a source for vapor phase growth of the semiconductor; and an etchant-supplying system, wherein the source-supplying system and the etchant-supplying system are isolated through placement of the substrate.

Abstract: An electrode structure on a p-type III group nitride semiconductor layer includes first, second and third electrode layers successively stacked on the semiconductor layer. The first electrode layer includes at least one selected from a first metal group of Ti, Hf, Zr, V, Nb, Ta, Cr, W and Sc. The second electrode layer includes at least one selected from a second metal group of Ni, Pd and Co. The third electrode layer includes Au.

Abstract: A method for fabricating a p-n heterojunction device is provided, the device being preferably comprised of an n-type GaN layer co-doped with silicon and zinc and a p-type AlGaN layer. The device may also include a p-type GaN capping layer. The device can be grown on any of a variety of different base substrates, the base substrate comprised of either a single substrate or a single substrate and an intermediary layer. The device can be grown directly onto the surface of the substrate without the inclusion of a low temperature buffer layer.

Abstract: According to a preferred embodiment of the present invention, there is provided a novel and optimal semiconductor light emitting device comprising a substrate, an n layer disposed co-extensively on the substrate, an n++ layer disposed non-extensively and flush on one side of the n layer. Furthermore, a p+ layer is disposed co-extensively on the n++ layer of the LED according to the invention, with a p layer further disposed co-extensively on the p+ layer. A p cladding layer is disposed co-extensively on the p layer. A multiple quantum well (MQW) layer is disposed co-extensively on the p cladding layer, and an n cladding layer is further disposed co-extensively on the MQW layer. A second n layer is disposed co-extensively on the n cladding layer. An n+ layer is disposed co-extensively on the second n layer of the LED according to the invention.

Abstract: In a semiconductor device, particles are removed from the surface of a gold conductive layer before an intermediate insulating layer of an amino silane compound is formed. An organic insulating layer is formed on the intermediate insulating layer. As a result, adhesion strength between the conductive layer and the intermediate insulating layer can be improved.

Abstract: An underlayer made of a III-V semiconductor compound is formed on a given substrate, and a CrSb compound is epitaxially grown on the underlayer by means of MBE method to fabricate a zinc blend type CrSb compound.

Abstract: The object of the invention is to provide a semiconductor device having a nitride-based hetero-structure in which an epitaxial nitride film has a uniformly flat surface at a single molecule level, and a method of easily fabricating such a device. The object of the invention is achieved by providing a semiconductor device comprising a sapphire substrate whose c-surface is modified to be nitride-surfaced, GaN buffer layer, N polarity GaN layer, N polarity AlN layer, N polarity InN/InGaN multi-layered device structure, Al polarity AlN layer, and GaN cap layer.

Abstract: A process and related product in which ohmic contacts are formed in High Electron Mobility Transistors (HEMTs) employing compound substrates such as gallium nitride. An improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts are described. This novel two-step process consists of depositing a plurality of layers having compounds of Group III V elements on a substrate; patterning and depositing a first photoresist on one of the layers; etching recessed areas into this layer; depositing ohmic metals on the recessed areas; removing the first photoresist; patterning and depositing a second photoresist, smaller in profile than the first photoresist, on the layer; depositing more ohmic metal on the layer allowing for complete coverage of the recessed areas; removing the second photoresist, and annealing the semiconductor structure.

Abstract: A method for fabricating a light-emitting semiconductor device including a III-Nitride quantum well layer includes selecting a facet orientation of the quantum well layer to control a field strength of a piezoelectric field and/or a field strength of a spontaneous electric field in the quantum well layer, and growing the quantum well layer with the selected facet orientation. The facet orientation may be selected to reduce the magnitude of a piezoelectric field and/or the magnitude of a spontaneous electric field, for example. The facet orientation may also be selected to control or reduce the magnitude of the combined piezoelectric and spontaneous electric field strength.

Abstract: Disclosed herein is a technique for forming a high quality ohmic contact utilizable in the fabrication of short-wavelength light emitting diodes (LEDs) emitting blue and green visible light and ultraviolet light, and laser diodes (LDs) using a gallium nitride (GaN) semiconductor.

Abstract: A nitride semiconductor laser device using a group III nitride semiconductor also as a substrate offers excellent operation characteristics and a long laser oscillation life. In a layered structure of a group III nitride semiconductor formed on a GaN substrate, a laser optical waveguide region is formed elsewhere than right above a dislocation-concentrated region extending so as to vertically penetrate the substrate, and electrodes are formed on the top surface of the layered structure and on the bottom surface of the substrate elsewhere than right above or below the dislocation-concentrated region. In a portion of the top surface of the layered structure and in a portion of the bottom surface of the substrate right above and below the dislocation-concentrated region, dielectric layers may be formed to prevent the electrodes from making contact with those regions.

Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: An AlN buffer layer 2; a silicon (Si)-doped GaN high-carrier-concentration n+ layer 3; an Si-doped n-type Al0.07Ga0.93N n-cladding layer 4; an Si-doped n-type GaN n-guide layer 5; an active layer 6 having a multiple quantum well (MQW) structure, and including a Ga0.9In0.1N well layer 61 (thickness: about 2 nm) and a Ga0.97In0.03N barrier layer 62 (thickness: about 4 nm), the layers 61 and 62 being laminated alternately; an Mg-doped GaN p-guide layer 7; an Mg-doped Al0.07Ga0.93N p-cladding layer 8; and an Mg-doped GaN p-contact layer 9 are successively formed on a sapphire substrate. A p-electrode 10 is formed of a film of titanium nitride (TiN) or tantalum nitride (TaN) (thickness: 50 nm). The contact resistance of this electrode is reduced through heat treatment.

Abstract: A metal-semiconductor junction comprising a wiring metal layer and a semiconductor layer. To reduce the contact resistance of the junction, a region doped with an n- or p-type impurity and having a high carrier concentration of 1021 cm−3 or more is provided in a near-surface part of the semiconductor layer (at a distance of 10 nm or less from the metal layer. The high-carrier concentration region is composed of n- or p-type impurity layers and IV-group semiconductor layers that have been alternately deposited upon another by means of, for example, vapor-phase growth.

Abstract: After a p-seat electrode-forming layer is laminated onto a light-transmissive electrode-forming layer, a first heating step and a second heating step are carried out for alloying the two layers. In the first heating step, heat treatment is performed at a relatively low temperature in an atmosphere containing oxygen. In the second heating step, heat treatment is performed at a relatively high temperature in an atmosphere not containing oxygen.