Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.

Abstract: A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Abstract: A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package.

Abstract: In one aspect, there is provided a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and has a contact support pillar opening formed therein. Contact support pillars that comprise a conductive metal and have a metal extension are located within the opening of the passivation layer.

Abstract: Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polymide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Abstract: A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure.

Abstract: Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers.

Abstract: A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm.

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A method of forming a stackable protruding via package including enclosing an electronic component and electrically conductive first traces on a first surface of a substrate in a package body. Protruding via apertures are formed through the package body to expose the first traces. The protruding via apertures are filled with solder to form electrically conductive vias in direct physical and electrical contact with the first traces. Via extension bumps are attached to first surfaces of the vias. The vias and the via extension bumps are reflowed to form protruding vias. The protruding vias extend from the first traces through the package body and protrude above a principal surface of the package body. The protruding vias enable electrical connection of the stackable protruding via package to a larger substrate such as a printed circuit motherboard. Further, the protruding vias in accordance with one embodiment are formed with a minimum pitch.

Abstract: Generally, the subject matter disclosed herein relates to repairing anomalous stiff pillar bumps that may be detected above a metallization system of a semiconductor chip or wafer. One illustrative method disclosed herein includes, among other things, forming a pillar bump above a metallization system of a semiconductor chip, and forming a plurality of notches in the pillar bump, wherein the plurality of notches are adapted to adjust a flexibility of the pillar bump when the pillar bump is exposed to a lateral force.

Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

Abstract: A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Abstract: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.

Abstract: A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract: A semiconductor device includes a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. The semiconductor device further includes a cap layer over a top surface of the conductive post. A method of forming a semiconductor device includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn). The method further includes forming a cap layer on a top surface of the conductive post.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing a lead-frame having an inner portion and a bottom cover directly on a bottom surface of the inner portion; forming an insulation cover directly on the lead-frame with the insulation cover having a connection opening; connecting an integrated circuit die to the lead-frame through the connection opening with the integrated circuit die over the insulation cover; forming a top encapsulation directly on the insulation cover; forming a routing layer having a conductive land directly on the bottom cover by shaping the lead-frame; and forming a bottom encapsulation directly on the conductive land with the bottom cover exposed from the bottom encapsulation.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A method of manufacturing an electronic component, which includes arranging a plurality of first electrode pads on a first substrate, and a plurality of second electrode pads on a second substrate, so that the first and second electrode pads correspond to each other. The method further includes forming a plurality of solder bumps on the second electrode pads and putting the first substrate over the second substrate. The first and second substrates are shifted in parallel to each other, in a horizontal direction, while the solder bumps are melting, so that the solder bumps are stretched in a slant direction to cause the solder bumps to be solidified into hourglass-shapes.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a carrier top side; mounting an integrated circuit over the carrier top side; attaching a bottom attachment directly on the integrated circuit; dragging a sandwich connector from the bottom attachment, the sandwich connector having a connector diameter; and attaching a top attachment directly on the sandwich connector, the top attachment wider than the bottom attachment.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies.

Abstract: A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

Abstract: An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer over the contact pad. A first via in the first passivation layer, wherein the first via has more than four sides, and wherein the first via extends to the contact pad.

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m.

Abstract: A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.

Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.

Abstract: A structure for minimizing resistance between a semi-insulating x-ray detector crystal and an electrically conducting substrate. Electrical contact pads are disposed on the detector crystal and on the substrate with an electrical interconnect between the contact pads formed from a conductive adhesive and washed solder in electrical and mechanical communication with the pads.

Abstract: A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: A template wafer fabrication process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A mounting structure of an electronic component includes a plurality of joining portions that join a plurality of first electrode terminals on the electronic component to a plurality of second electrode terminals on a circuit board. The joining portions each include a first projecting electrode formed on the first electrode terminal, a second projecting electrode formed on the second electrode terminal, and a solder portion that joins the first projecting electrode to the second projecting electrode. The end face of the first projecting electrode is larger in area than the end face of the second projecting electrode, and at least a part of the second electrode terminals exposed from the circuit board has a larger area than the bottom of the second projecting electrode.

Abstract: A method of electrical connection between a series of hard conductive points and corresponding pads arranged on a one face of a first component, and a series of buried ductile conductive bumps and corresponding pads arranged on one face of a second component. The method comprises forming said series of hard conductive points on said face of the first component; forming said series of buried ductile conducting bumps on said face of the second component; inserting said series of hard conductive points in said series of buried ductile conducting bumps at an ambient temperature; and directly sealing the first and second components together.

Abstract: In flip chip attach of electronic components, underfill is filled between the component and the substrate to alleviate, for example, thermal stress. In electronic component mounting using copper pillars conducted so far, filler contained in the underfill may cause separation in the process of heating and curing the resin. Disclosed is plating the surfaces of the copper pillars with solder. Mobilization of the filler charged in the underfill due to electric fields produced by local cells that are developed upon contact between dissimilar metals, is suppressed, and occurrence of crack at connection portions is obviated. Thus, connection reliability is increased.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract: A semiconductor device includes a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. The semiconductor device further includes a cap layer over a top surface of the conductive post. A method of forming a semiconductor device includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn). The method further includes forming a cap layer on a top surface of the conductive post.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.