Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: A method of forming a micromechanical structure, wherein at least one micromechanical structural layer is provided above a substrate. The micromechanical structural layer is sustained between a lower sacrificial silicon layer and an upper sacrificial silicon layer, wherein a metal silicide layer is formed between the lower and upper sacrificial silicon layers to increase interface adhesion therebetween. The upper sacrificial silicon layer, the metal silicide layer and the lower sacrificial silicon layer are then removed to release the micromechanical structural layer.

Abstract: By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming conductive surface irregularities during the further processing. Consequently, yield loss effects caused by leakage paths or short circuits in the first metallization layer may be significantly reduced.

Abstract: A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material situated on the substrate assembly of the semiconductor wafer. At least one barrier layer is deposited within the recess. A seed layer helping to promote nucleation, deposition, and growth of a material that will be used to fill up the recess is then deposited on the barrier layer. An electrically conductive layer is then formed upon the seed layer. An energy absorbing layer will then be formed upon the conductor layer, where the energy absorbing layer has a greater thermal absorption capacity than that of the electrically conductive layer. The energy absorbing layer is heated, with or without an applied heightened pressure, to cause the conductor layer to flow so as to fill voids that have formed within the dielectric structure.

Abstract: A semiconductor device has a first interlayer insulating film formed on a substrate, having a first interconnection buried therein, and having a depressed portion and an insulating barrier film formed on the first interlayer insulating film. A second interlayer insulating film is formed to fill in the depressed portion, cover the upper surface of the insulating barrier film, and have a second interconnection buried therein.

Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

Abstract: Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.

Abstract: A method of copper metallization includes providing a patterned substrate containing a via and a trench, and performing an integrated process on the patterned substrate. The integrated process includes depositing a first metal-containing layer over the patterned substrate, removing by sputter etching the first metal-containing layer from the bottom of the via and at least partially removing the first metal-containing layer from the bottom of the trench, depositing a conformal Ru layer onto the sputter etched first metal-containing layer, depositing a Cu alloying metal layer onto the conformal Ru layer, and plating Cu over the patterned substrate. According to one embodiment, the method can further include depositing a second metal-containing layer onto the sputter etched first metal-containing layer prior to depositing the conformal Ru layer. According to another embodiment, a Cu alloying metal may be deposited onto the plated Cu and the plated Cu annealed.

Abstract: A four-layer structured hard mask composed of a SiC film, a first SiO2 film, a SiC film, and a second SiO2 film is formed on a porous silica film as an interlayer insulating film. Then, the second SiO2 film is etched with a resist mask. Subsequently, the SiC film is etched with the second SiO2 film. Thereafter, the first SiO2 film is etched with the SiC film. Subsequently, the SiC film is etched with the SiC film. Then, by etching the porous silica film with the SiC film, a wiring trench is formed. At this time, a selection ratio between the SiC film and the porous silica film is large, so that deformation of the SiC film rarely occurs, which prevents leakage caused by the deformation.

Abstract: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

Abstract: Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.

Abstract: An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating layer comprises a first opening in a region of the first conductor track of the wiring level and a second opening in a region of the second conductor track of the wiring level and a contact bridge composed of a second conductive material, wherein the contact bridge is connected to the first conductor track in a region of the first opening and is connected to the second conductor track in a region of the second opening.

Abstract: A semiconductor device manufacturing method wherein a metal suicide layer is formed via an in-situ process. The method includes forming a gate electrode on a semiconductor substrate; forming an insulation side wall at either lateral surface of the gate electrode; forming a source/drain region in a surface of the semiconductor substrate at either side of the gate electrode; forming a metal layer on the surface of the semiconductor substrate including the gate electrode; performing a plasma treatment on the metal layer; forming a capping material layer on the metal layer; performing an annealing process upon the semiconductor substrate, to form a metal silicide layer on the surface of the semiconductor substrate at positions corresponding to the gate electrode and the source/drain region; and removing the capping material layer and the metal layer remained without reaction with the gate electrode and the semiconductor substrate.

Abstract: A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper wiring, wherein the copper wiring includes an additive for improving adhesion between the copper wiring and the insulating layer, and a profile of the additive has a gradient in which a concentration is gradually reduced as it goes from the top surface of the copper wiring toward the inside thereof, and has the highest concentration on the top surface of the copper wiring.

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

Abstract: A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a second interconnection layer of gold provided as an uppermost interconnection layer on the interlevel insulation film; and a barrier layer provided between the first interconnection layer and the second interconnection layer in an interlevel connection opening formed in the interlevel insulation film. The barrier layer includes a first sublayer provided in contact with the first interconnection layer to reduce a contact resistance, a second sublayer provided in contact with the second interconnection layer to improve a bonding strength, and a third sublayer provided between the first sublayer and the second sublayer. The first sublayer, the second sublayer and the third sublayer are, for example, a first tantalum sublayer, a second tantalum sublayer and a tantalum nitride sublayer, respectively.

Abstract: A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: An adhesion layer composed of a titanium film and a titanium nitride film is formed by CVD on the inner wall of a contact hole formed in a multilayer film composed of an interlayer insulating film, a silicon nitride film, and a silicon dioxide film. Then, a conductive film made of tungsten or polysilicon is filled by CVD in the contact hole and the respective portions of the conductive film and the adhesion layer which are located over the silicon dioxide film are removed by CMP. Subsequently, the silicon dioxide film is removed by an etch-back method or a CMP method so that the silicon nitride film is exposed. This can prevent the delamination of the adhesion layer from the silicon nitride film as a hydrogen barrier film and also prevent the formation of a scratch in the silicon nitride film.

Abstract: The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A buffer layer is formed between the gate and the substrate, and/or formed between the gate and the gate insulating layer. The buffer layer comprises TaSix, TaSixNy, TiSix, TiSixNy, WSix, WSixNy, or WCxNy. A semiconductor layer is formed on the gate insulating layer. A source and a drain are formed on a portion of the semiconductor layer. The gate is covered by the buffer layer.

Abstract: A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

Abstract: A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

Abstract: A hybrid ionized physical vapor deposition technique to form liner films for vias, trenches, and other structures of integrated circuits. The techniques involves depositing liner materials within a via, hole, trench, or other structure in a neutral state, using, for example, physical vapor deposition. The liner materials deposited in this step have an ionization ratio of less than ten percent, and no bias potential is applied to an underlying substrate. The technique also involves depositing liner materials in ionized form in the same via using ionized physical vapor deposition. The liner materials deposited in this step have an ionization ratio far more than ten percent, and an optional bias potential may be applied to the underlying substrate. After liner film is formed, any other suitable actions or processing steps may take place including building additional metallization and dielectric layers and vias or trenches to produce a multi-level interconnect system.

Abstract: A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual damascene interconnection includes a lower metal interconnection film, an intermetal insulating film having a via hole and a trench and formed on the lower metal interconnection film, first and second insulative spacer films formed on sidewalls of the via hole and the trench, respectively, a barrier metal layer covering the first and second insulative spacer films and the lower metal interconnection film in the via hole and the trench, and an upper metal interconnection film formed on the barrier metal layer, the via hole and the trench being filled with the upper metal interconnection film.

Abstract: A method of forming a conductive pattern on a substrate. The method comprising providing a substrate carrying a conductive layer; forming a first portion of the conductive pattern by exposing the conductive layer to a laser and controlling the laser to remove conductive material around the edge(s) of desired conductive region(s) of the first portion; and laying down an etch resistant material on the conductive layer, the etch resistant material defining a second portion of the conductive pattern, removing conductive material from those areas of the second portion not covered by the etch resistant material, and then removing the etch resistant material.

Abstract: A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal layer. Also a method and apparatus for forming a via through a dielectric to reveal metal at the base of the via, depositing a transition metal layer, and depositing a first metal layer on the transition metal layer. Additionally, a method and apparatus for depositing a transition metal layer on an exposed metal surface, and depositing a layer thereover selected from the group consisting of a capping layer and a low dielectric constant layer.

Abstract: Embodiments of the invention provide a relatively hydrophilic layer in a low k dielectric layer. The hydrophilic layer may be formed by exposing the dielectric layer to light having enough energy to break Si—C and C—C bonds but not enough to break Si—O bonds.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: A process for making semiconductor structures uses a decoupled plasma source to produce a highly selective plasma etchant to form a structure with a thin adhesive layer and overlaying conductive layer. The preferred plasma is formed from chlorine and oxygen feed gases. The highly conductive semiconductor structure has a thickness less than about 3000 ?, preferably less than about 2600 ?, and incorporates an adhesive layer that is preferably less than about 100 ? thick. Despite the reduced profile and topography of the structure, it is more conductive than prior structures, and provides a robust device.

Abstract: A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a thickness of less than six hundred angstroms. The method further includes annealing the layer of iridium, forming a dielectric layer on the layer of iridium, and forming a conductive layer on the dielectric layer.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Abstract: A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.

Abstract: A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on a substrate and impurity ions are implanted into the surface of the substrate to form source/drain regions (diffusion layers: 1A, 1B) on both sides of the gate electrode. Also, impurity ions are implanted to control the resistance value of the resistive interconnection. Next, a sidewall film is formed to cover the resistive interconnection. Then a heat treatment is performed to activate the source/drain regions (diffusion layers: 1A, 1B).

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.

Abstract: A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited from a gas mixture comprising an organosilicon compound and an oxidizing gas in the presence of RF power in a chamber. The RF power and a flow of the organosilicon compound and the oxidizing gas are continued in the chamber after the deposition of the low dielectric constant film at flow rates sufficient to deposit an oxide rich cap on the low dielectric constant film.

Abstract: One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing one or more seed layers, which method includes steps of: (a) depositing by an ALD technique at least an initial portion of a substantially conformal seed layer on the field and inside surfaces of the at least one opening, wherein said at least one opening has a width of less than about 0.

Abstract: Atomic layers can be formed by introducing a tantalum amine derivative reactant onto a substrate, wherein the tantalum amine derivative has a formula: Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1–C6 alkyl functional group, chemisorbing a portion of the reactant on the substrate, removing non-chemisorbed reactant from the substrate and introducing a reacting gas onto the substrate to form a solid material on the substrate. Thin films comprising tantalum nitride (TaN) are also provided.

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract: A formation method of metal wiring of a semiconductor device is disclosed. According to one example, an example method may include forming a metal wire on a pre metal dielectric (“PMD”) on a semiconductor substrate; patterning and sintering the metal wire; forming an insulating layer on the metal wire and the PMD; and forming a via hole in the insulating layer. The example method may further include forming a barrier metal layer made of multiple metal layers on inner wall of the via hole and upper surface of the insulating layer using physical vapor deposition and chemical vapor deposition; filling up inside the via hole by forming a metallic material on the metal layer; and forming a metallic material via by chemical mechanical polishing of the metallic material and the barrier metal layer until the insulating layer is exposed.

Abstract: The present invention describes the use of polybenzoxazoles (PBOs) for adhesively bonding articles or materials, especially components used in the semiconductor industry, such as chips and wafers, a process for adhesively bonding materials, especially chips and wafers, chip and/or wafer stacks produced by the process, and adhesive compositions which comprise the polybenzoxazoles of the formula (I).

Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Abstract: An electrical device is disclosed. The electrical device includes a substrate, and a self-assembled molecular layer on the substrate. The self-assembled molecular layer comprises a plurality of molecules, each molecule comprising a first end proximate to the substrate and a second end comprising sulfur distal to the substrate. A copper layer is on the self-assembled molecular layer.

Abstract: Some embodiments disclose a low temperature semiconductor packaging apparatus and method. An apparatus generally comprises a heat spreader, a silicon die, and a thermal interface material disposed between the heat spreader and the silicon die comprising a plurality of metals capable of forming a transient liquid phase bond. A method generally comprises attaching a silicon die to a substrate, depositing a thermal interface material on at least one of the silicon die and a heat spreader, and attaching the heat spreader to the silicon die, wherein the thermal interface material comprises a plurality of metals capable of forming a transient liquid phase bond. Other embodiments are also described and claimed.

Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material.