Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A method for etching an organic dielectric material layer includes depositing an inorganic barrier layer on the organic dielectric material layer, and depositing an inorganic masking layer on the inorganic barrier layer. A masking resin layer is deposited on the inorganic masking layer. The method further includes patterning the masking resin layer and etching through the inorganic masking layer to expose the inorganic barrier layer. Remaining portions of the masking resin layer are removed, and the exposed inorganic barrier layer is etched to expose the organic dielectric material layer. The method further includes removing remaining portions of the inorganic masking layer, and etching the exposed organic dielectric material layer while using the inorganic barrier layer as a mask.

Abstract: A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their adjacent dielectric layers (18 and 22) are positioned in the stack (13) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack (13). Etch processing is then used to position the layers (16) and (20) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.

Abstract: A method of forming a through-hole or a recess in a silicon substrate, having a conductor pattern formed on one side thereof by irradiating a laser beam to the silicon substrate, comprising the steps of: forming a protective film for protecting the conductor pattern on the one side of the silicon substrate, forming, on the entire surface of the silicon substrate inclusive of the top of the protective film, a metal plating film adhered to the protective film, irradiating a laser beam onto a predetermined position of the silicon substrate covered with the protective film and with the metal plating film, to form a through-hole or a recess in the silicon substrate, peeling off the metal plating film and removing debris, on the metal plating film around the open periphery of the through-hole or the recess, which has been deposited thereon during the formation of the thorough-hole or the recess by the laser beam irradiation, and removing a deposit, on the inner wall of the thorough-hole or the recess, which has bee

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a silicon layer on the surface of the contact hole, and forming a selective conductive plug in the contact hole having the silicon layer.

Abstract: The method of manufacturing a semiconductor device according to the present invention has a step of forming a first layer-insulating film to be adhered to a diffused layer formed on the surface of a semiconductor substrate or to a lower wiring formed on the semiconductor substrate, using a first dielectric, a step of disposing mutually parallel upper wirings on the first layer-insulating film and forming a protective film composed of a second dielectric having an etching rate smaller than that of the first dielectric on the top face and side faces of the upper wirings, and a step of forming a contact hole penetrating the first layer-insulating film and reaching the diffused layer or the lower wiring by a dry etching that uses the protective insulating film as a part of an etching mask.

Abstract: In a semiconductor device having a wire structure, the thickness of a first insulation film substantially corresponds to the depth of a contact hole. A surface of a second insulation film serves as a bottom face of a wire groove. Regarding the contact hole, only a side wall portion intersecting a direction of the wire groove has a substantial taper angle. This configuration can be attained under conditions where an etching selectivity of the first insulation film to the second insulation film is set to be slightly lower and a portion of the second insulation film where a opening edge of an opening portion is exposed is slightly etched during etching process of the wire groove. With a semiconductor device having this structure, a conductive material embedding characteristic can be enhanced, while preventing possibility of short-circuit even when an interval between wires is reduced.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a hole, thereafter, the etching rate decreases. Accordingly even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

Abstract: A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material.

Abstract: A method of fabricating a semiconductor device is advantageous in preventing occurrence of an erroneous short-circuit and a withstand voltage failure in a connection hole and preventing occurrence of a failure at the time of burying a connection hole with a metal. A silicon carbo-nitride film is formed on a conductor or an interconnection of a Damascene structure formed on a silicon substrate (S1), the silicon carbo-nitride film is taken as a side wall or an interlayer insulating film (S2), a silicon oxide film is formed on the silicon carbo-nitride film (S3), the upper side silicon oxide film is etched using the lower side silicon carbo-nitride film as an etching stopper layer (S4), and a connection hole is formed (S5).

Abstract: A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed.

Abstract: A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450° C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity.

Abstract: A method of forming a metal line in a semiconductor device comprises forming a damascene pattern, forming a diffusion barrier layer, depositing a copper precursor by a spin-on process, forming a thin copper film by a baking process, filling the damascene pattern by a hydrogen reduction annealing process and a force filling process, and then forming a copper line by a chemical mechanical polish method. As such, the method forms a copper line without forming a seed layer by simultaneously performing a hydrogen reduction annealing process and a force filling process, by introducing a spin-on process. Therefore, the method can simplify the process, reduce the manufacturing cost, and easily form a copper line.

Abstract: A dynamic random access memory (DRAM) device includes a stacked capacitor including a storage electrode, a dielectric film and a cell plate. In a preferred embodiment, the storage electrode contacts with a diffusion region of a substrate through a contact hole. The storage electrode has a first fin which has a first uniform portion with a width greater than the width of the contact hole, and a second uniform portion serving as a side wall, which is formed around an inner-wall of the first uniform portion defining the first opening, so that a second opening defined by the second uniform portion, has a width which is substantially identical to the width of the contact hole. The use of the second uniform portion to form the stacked capacitor allows for a reduction in the size of the contact hole relative to the conventional DRAM devices, and therefore allows for a reduction in the overall size of the DRAM device of the present invention, relative to conventional DRAM devices.

Abstract: A method of manufacturing a semiconductor structure, including etching an opening in a hard mask layer including a trench pattern width a first portion having a first width and a second portion being an oversized trench portion having a second width greater than a width of the first portion, the second portion being formed over a predetermined via location. Also including are steps of depositing a resist and patterning a via pattern in the predetermined via location, etching a via corresponding to the via pattern through the resist and at least partially through a dielectric layer, and etching an oversized trench portion corresponding to a second portion opening in the hard mask.

Abstract: A method of fabricating copper damascene. In this invention, only crystalline copper metal layer is formed inside the damascene trench and only amorphous copper metal layer is formed outside the damascene trench. During stacking the copper metal layer, copper metal stacks up to form crystalline copper metal with good lattice packing according to the position of the copper seed layer. Conversely, amorphous copper metal is formed in positions where no copper seed layer exists. Since the amorphous copper metal is softer than the crystalline copper metal, lower pressure and the ordinary slurry are used in chemical mechanical polishing to remove amorphous copper metal layer outside the damascene trench, in order to form a flat-surfaced copper damascene structure.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: The invention relates to a process for making a copper connection with a copper connection element in an integrated circuit comprising a damascene structure, with the connection element being covered successively with an encapsulation layer and at least one layer of dielectric material with a very low dielectric constant. The process includes the steps of etching the layer of dielectric material until the encapsulation layer is reached in order to obtain a connection hole opposite the connection element. A protective layer is then formed on the walls of the connection hole, with the protective layer preventing contamination of the dielectric layer from diffusion of copper. The protective and encapsulation layers are then etched at the bottom of the connection hole in such a way as to reveal the connection element. The connection hole is then filled with copper.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Abstract: The present invention provides a method to prevent short of contact and metal lines. The method is applied in a substrate formed with a number of contact windows. The method is comprised of: (a) forming a first conductive layer in the contact windows without filling up the contact windows; (b) forming liners in the contact windows to reduce the openings of the contact windows; (c) forming liner trenches in the contact windows; and (d) forming a second conduction layer on top of the first conductive layer in the contact windows. According to this invention, shorts between contact windows and metal lines is effectively prevented. Therefore, the product yield is greatly improved.

Abstract: A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.

Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction between the titanium film and the silicon substrate such that the titanium film is subjected to silicide reaction with the thickness 4 nm to 48 nm or, more preferably, with the thickness of 8 nm to 34 nm. In the instance where the contact hole is filled with doped polycrystal silicon material, the titanium film is deposited to be in contact with the polycrystal silicon in the contact hole. The silicon substrate/silicon body may have at least a MISFET formed thereon in which case the contact hole is formed to expose an active region of the MISFET, as one example.

Abstract: A method of forming spaces between polysilicon lines can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a polysilicon layer and are separated by a first width, forming amorphous carbon spacers along lateral side walls of the patterned structures, etching apertures into the polysilicon layer not covered by the amorphous carbon spacers and the patterned structures where the apertures in the polysilicon layer between adjacent patterned structures have a second width, and ashing away the amorphous carbon spacers and the patterned structures. The second width is less than the first width.

Abstract: In a water rinsing process performed after the surface of a substrate has been cleaned using a cleaning solution, a first spinning process, in which water is supplied to the surface of the substrate while the substrate is rotated at a first rotation speed, and a second spinning process, in which the substrate is rotated at a second rotation speed that is higher than the first rotation speed, are repeatedly performed alternately.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second conductor are formed on the surface of the semiconductor substrate. The first conductor and the second conductor are encapsulated with a first encapsulation and a second encapsulation, respectively. The first encapsulation and the second encapsulation contain titanium oxide, boron nitride, silicon carbide, magnesium oxide or carbon. The first encapsulation and the second encapsulation are suitable as a self-aligning etch mask for etching a self-aligned contact hole between the first conductor and the second conductor.

Abstract: Disclosed is a dual damascene process for a semiconductor device with two low dielectric constant layers in a stack thereof, in which a via hole and a trench connecting with the via hole are formed respectively in the dielectric layers and a conductor is filled in the via hole and the trench to connect with a conductive region below the via hole after a barrier layer between the via hole and the conductive region is removed. A liner is deposited on the sidewalls of the dielectric layers in the via hole and the trench before the removal of the barrier layer to prevent particles of the conductive region such as copper from sputtering up to the dielectric layers when removing the barrier layer. An etch-stop layer inserted between the dielectric layers is pulled back to be spaced from the via hole with a distance to improve the trench-to-via alignment.

Abstract: A method for forming a contact window with low resistance. The method at least includes the following steps. First of all, a dielectric layer is formed over a substrate, in which the substrate having a contact region where the metal contact will be formed thereon. Then, a first barrier layer is deposited over the dielectric layer, and a patterned photoresist is formed to defined a contact hole. Next, the first barrier layer and the dielectric layer are etched to expose portion of the substrate by using the photoresist as a mask thereby a contact hole is formed in the dielectric layer, wherein the exposed substrate has a conductive region. Then, a second conformal barrier layer is deposited on the first barrier layer and in the contact hole, the second conformal barrier layer is etched to exposed the conductive region to form a spacer on sidewalls of in the contact hole. Finally, the contact region opening is filled with a metal layer to complete electrical connections.

Abstract: A method of making a semiconductor device includes the steps of etching, with a resist pattern (3) used as a mask, a contact pattern (4) in at least one interlayer insulation film (2) made on a silicon substrate (1); forming on the contact pattern an insulation film (5) containing silicon as a main component; and oxidizing by heat treatment the insulation film to provide an oxide film (6) including a side wall oxide film on an inside wall of the contact pattern.

Abstract: An amount of a semiconductor substrate cut due to etching in the bottom of a contact hole formed by the SAC technique is reduced. Silicon oxide films are dry etched under the conditions of increasing the etching selective ratio of the silicon oxide films to an insulating film. Then, the conditions are changed to those increasing the etching selective ratio of the insulating film to the silicon oxide films and the insulating film is etched by a predetermined amount.

Abstract: The invention relates to a three-dimensional circuit configuration in which semiconductor chips are configured one above the other and in which the semiconductor chips are electrically connected together. In this arrangement, conductive channels are produced between mutually opposite surfaces of the semiconductor chips by thermomigrating a conductive material.

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.

Abstract: A method of forming a pattern for a semiconductor device without using a photolithography technique is disclosed, wherein the method includes forming a sacrificial layer on a semiconductor substrate, forming a sacrificial layer pattern by patterning the sacrificial layer, forming a conformal layer on a resultant structure after forming the sacrificial layer pattern, and forming the layer pattern by anisotropically etching the conformal layer.

Abstract: A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, and depositing an anti-reflective material in the opening at an optimal thickness. The optimal thickness is determined by minimizing a standard deviation of reflectivity of the anti-reflective material. After etching the first dielectric layer, the anti-reflective material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.

Abstract: The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.

Abstract: A method of forming a damascene structure. A porous dielectric layer is formed over a substrate. The porous dielectric layer is patterned to form an opening that exposes a portion of the substrate. A conformal low dielectric constant layer is formed over the substrate and the exposed surface of the opening. A portion of the low dielectric constant material is removed to form spacers on the sidewalls of the porous dielectric layer. A conformal barrier layer and a conductive layer are sequentially formed over the opening. Excess conductive material and barrier material outside the opening above the dielectric layer are removed to form a damascene structure.

Abstract: A new method of fabricating self-aligned, anti-via interconnects has been achieved. A semiconductor substrate is provided. A metal layer is deposited overlying the semiconductor substrate. The metal layer may comprise a composite stack of two metal layers. The metal layers may additionally be separated by an etch stopping layer. An anti-reflective coating layer is deposited overlying the metal layer. The metal layer is etched through to form connective lines. The metal layer is then etched partially through to form vias. The partial etching through may be accomplished by timed etching or by use of the optional etching stop layer. A dielectric layer is deposited overlying the vias, the connective lines and the semiconductor substrate. The dielectric layer may comprise a low-k material. The dielectric layer is polished down to complete the self-aligned, anti-via interconnects in the manufacture of the integrated circuit device.

Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on said semiconductor body then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate. An etch stop layer is deposited adjacent said insulating layer followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer but retains the substantially rectangular lateral spacer profile of the first insulating layer.

Abstract: Methods for creating one or more structures in a micromachined device. In one arrangement, the methods include the steps of providing a substrate, forming upstanding nonconductive mold walls on the substrate so that first and second wells are formed, the second well being wider than the first well. The method further includes applying a first material to the surface of the wells so that the first well fills with the first material before the second well, and removing the first material from the second well while leaving a portion in the first well.

Abstract: A method of forming contact plugs of a semiconductor device is provided. Bit lines are formed over a semiconductor substrate in which a predetermined lower layer is formed and a cell area and a core area are defined. An interlayer dielectric layer is formed over the semiconductor substrate over which the bit lines are formed. The interlayer dielectric layer is wet etched until the interlayer dielectric layer is recessed from the upper surfaces of the bit lines to a predetermined depth. A dielectric layer for forming spacers is formed over the semiconductor substrate, the dielectric layer having a step difference formed due to the wet etching of the interlayer dielectric layer. The dielectric layer in the core area is left and the dielectric layer in the cell area is etched by an anisotropic method to form spacers of the dielectric layer in the cell area. The interlayer dielectric layer is etched using the spacers and the dielectric layer as a mask to form contact holes.

Abstract: First, a photoresist layer is formed on the substrate, wherein the photoresist layer has a plug-like structure. Then, an oxide layer is deposited on the plug-like structure. The oxide layer is etched to expose a portion of the plug-like structure. The plug-like structure is removed to formed a hole. Next, a conformal layer is deposited on the oxide layer and hole. Finally, the conformal oxide layer is etched, then the width of hole is smaller then original hole.

Abstract: A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor.