Abstract: A method for fabricating a semiconductor device is disclosed. A spacer is formed on the sidewall of the contact hole in which a storage node contact plug is buried. An etch barrier film and an insulating film are sequentially formed after the formation of the storage node contact plug. The insulating film and the etch barrier film are sequentially etched to form an opening part. Then a storage node is formed within the opening part which has been formed by an etching. Then prominences are formed on the surface of the storage node.

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide lining film is deposited on a top surface and sidewalls of the gate conductor stacks. A sacrificing layer is deposited on the silicon dioxide lining film. The sacrificing layer is then polished to expose the top surface of the gate conductor stacks. A spin-on-glass (SOG) film is then coated on the sacrificing layer. A resist pattern masking the bit line contact forming area is formed on the SOG film. The un-masked SOG film, sacrificing layer and silicon dioxide lining film are etched away. A silicon nitride thin film is deposited on the remaining SOG film. A BPSG layer is deposited on the silicon nitride thin film and is then polished to expose the SOG layer.

Abstract: This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.

Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: In one embodiment, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate, using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures and second insulating spacers are formed on the first insulating spacers. Thereafter, impurity ions at a high dose are implanted into the semiconductor substrate, using the first and second insulating spacers as a mask. Then, the second insulating spacers are removed. Therefore, contact resistance and characteristics of the transistors can be improved by adjusting an effective channel length and contact areas.

Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.

Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: When the occurrence of the bowing is controlled through the etching conditions, a change in etching conditions causes the bowing. Another problem is a requirement of the larger-sized apparatus for the substrate with a larger diameter in order to allow a whole substrate being subjected equally to the conditions under which no bowing occurs.

Abstract: A step for forming a wiring on a semiconductor substrate, a step for forming a first silicon oxide film on the semiconductor substrate having the wiring, and a step for forming an interlayer insulating film composed of a material bearing a low specific inductive capacity on the first silicon oxide film are sequentially executed to form a multilayered wiring. The interlayer insulating film is formed to have a smaller thickness relative to a step of the first silicon oxide film, so as not to extend beyond the step of the first silicon oxide film.

Abstract: The present invention comprises the steps of forming a connection hole in an interlayer insulating film including an organic insulating film; forming an inorganic film covering on an upper surface of the interlayer insulating film and an inner surface of the connection hole; forming an organic film for filling inside the connection hole on an inorganic film; removing the organic film inside the connection hole so as to leave a part of the organic film at a bottom of the connection hole; forming a wiring trench connecting to the connection hole in the interlayer insulating film; removing the organic film inside the connection hole; removing the inorganic film; and forming a trench wiring by filling a conductive material in the wiring trench and inside the connection hole and forming a plug continuing from the trench wiring.

Abstract: A method for contact profile improvement is described. The contact window is formed over a substrate having at least one element. A first oxide layer is formed on the substrate. A borophosphosilicate glass layer is formed on the first oxide layer and the borophosphosilicate glass layer is treated by a planarization process. The contact window is formed in the first oxide layer and the borophosphosilicate glass layer. The element on the substrate is exposed therein. A second oxide layer is formed on the borophosphosilicate glass layer, the sidewall and the bottom of the contact window, with overhangs formed at an opening of the contact window. A spacer on the sidewall of the contact window is formed by etching the second oxide layer to further expose the surface of the borophosphosilicate glass layer. Finally, a native oxide on the bottom of the contact window is removed by a wet etching process and the etching selectivity between the native oxide and the spacer is smaller than 1.

Abstract: A method for forming a contact opening is provided. After forming transistors on a substrate, a stacked resist layer including a resist layer without a silicon element and a resist layer with a silicon element covers the transistors and the substrate. The stacked resist layer is defined to cover a region of a contact opening to be formed as a mask. A selective growth process, such as a liquid phase oxide deposition (LPOD), is carried out to form a selective silicon oxide layer on the silicon-containing surface and fills the space between the stacked resist layer. After the stacked resist layer is removed, a contact opening is formed in the silicon oxide layer and a step of the etching process is eliminated.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: To provide a chemical amplification type positive photoresist composition suited to resist patterning of a substrate presenting surface step differences, a method for manufacturing the semiconductor device employing this composition, and a semiconductor substrate. In a method for manufacturing a semiconductor device, a resist film is formed using a chemical amplification type positive photoresist composition, comprised of a base resin and a basic compound added to the base resin at a rate of 1 to 100 mmol to 100 g of the base resin, on a substrate halving surface step differences and into which the organic removing solution is deposited or oozed, and a predetermined area of the resist film is exposed to light to form a resist pattern.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: A composite sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The composite sacrificial material includes a polymeric or oligomeric matrix with filler material mixed therein. The filler material may be particulate matter that may be used to modify one or more properties of the composite sacrificial material during semiconductor processing.

Abstract: A method for treating a dielectric material using hydrocarbon plasma is described, which allows for thinner films of barrier material to be used to form a robust barrier.

Abstract: A portion, positioned at an opening portion of a resist, of an anti-reflection film is etched using an etching gas containing a substituted hydrocarbon with a halogen. At the time of etching of the anti-reflection film, a carbon component of the substituted hydrocarbon with a halogen is formed as a carbonaceous deposit on side walls, less irradiated with ions, of the opening portion of the resist, and on side walls of an opening portion, formed by etching, of the anti-reflection film. The deposit acts as a side wall blocking film, to suppress lateral extension of the opening portion of the resist and the opening portion of the anti-reflection film by etching, thus allowing anisotropic etching of the anti-reflection film. With this etching method, it is possible to etch the anti-reflection film with a resist taken as a mask while suppressing a variation in pattern dimension.

Abstract: A metal interconnection for an integrated circuit device is fabricated by forming a trench in an integrated circuit substrate and a via hole beneath a portion of the trench. The trench includes a trench sidewall and the via hole includes a sacrificial film therein. A buffer layer is formed on the trench sidewall. At least some of the sacrificial film is removed from the via hole by etching the sacrificial film through the trench that includes the buffer layer on the trench sidewall. The metal interconnection is formed in the via hole from which at least some of the sacrificial film has been removed, and in the trench. The buffer layer may use material having etch selectivity to an etchant which is used when removing the sacrificial film, to thereby protect the trench sidewall when removing the sacrificial film.

Abstract: A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second conductor are formed on the surface of the semiconductor substrate. The first conductor and the second conductor are encapsulated with a first encapsulation and a second encapsulation, respectively. The first encapsulation and the second encapsulation contain titanium oxide, boron nitride, silicon carbide, magnesium oxide or carbon. The first encapsulation and the second encapsulation are suitable as a self-aligning etch mask for etching a self-aligned contact hole between the first conductor and the second conductor.

Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a mask to form in the insulating film an opening at which part of the surface of the conductive pattern is exposed; forming an antioxidant layer on the part of surface of the conductive pattern exposed while removing the resist pattern; and depositing a conductive film on the conductive pattern from which the antioxidant layer has been removed.

Abstract: The present invention provides a method for forming a metal line of a semiconductor device comprising the steps of: forming a via plug on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed; forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug; depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed; forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and forming a metal line by burying the trench with a conductive material.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well.

Abstract: A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).

Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

Abstract: A method for forming an interlayer insulating film includes the steps of forming an underlying insulating film on a substrate; forming a film containing B (boron), C (carbon) and H2O) on the underlying insulating film by plasma enhanced chemical vapor deposition using a source gas containing an Si—C—O—H compound, an oxidative gas and a compound containing B (boron); releasing C (carbon) and H2O in the film from the film by annealing the film, and thereby forming a porous SiO2 film containing B (boron); and subjecting to the porous SiO2 film containing B (boron) to H (hydrogen) plasma treatment, and then forming a cover insulating film.

Abstract: A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Abstract: A silicon nitride film for storing electric charge is formed on a semiconductor substrate while placing a tunnel oxide film in between, and the silicon nitride film is then subjected to hydrogen plasma treatment so as to effectively erase unnecessary charge stored therein during various process steps in fabrication of the semiconductor memory device, to thereby stabilize the threshold voltage (Vth) of the semiconductor memory device.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: A method for reworking a metal particulate contaminated semiconductor wafer process surface following a metal dry etchback process including providing a semiconductor wafer including a dielectric insulating layer having anisotropically etched openings lined with a first barrier/adhesion layer formed according to a blanket deposition process and an overlying metal layer formed according to a blanket deposition process filling the anisotropically etched openings; dry etching in an etchback process to remove the metal layer to form a process surface revealing at least a portion of the first barrier/adhesion layer; performing a chemical mechanical polishing (CMP) process to rework the process surface to remove a remaining portion of the metal layer including the first barrier/adhesion layer to endpoint detection of the dielectric insulating layer; and, blanket depositing a second barrier/adhesion layer over the dielectric insulating layer.

Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.

Abstract: A method of forming a copper wiring in a semiconductor device. The method can prevent an increase of a dielectric constant of a low dielectric constant film and making bad deposition of a copper anti-diffusion film, due to infiltration of an organic solvent, an etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generating when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process. In order accomplish these purpose, a CFXHY polymer layer is changed to a SiCH film using SiH4 plasma without removing the polymer layer formed at the side of the damascene pattern. Therefore, infiltration of an organic solvent or an etch gas can be prevented due to the SiCH film having a condensed film quality and a good mechanical strength.

Abstract: A method for manufacturing a semiconductor device in which a MOS transistor having a reduction in a leakage current is obtained without unnecessarily damaging an integration of the transistor. After MOS transistor structures having a first sidewall are formed, an interlayer dielectric film is formed over a whole surface. A silicon nitride film is deposited on the interlayer dielectric film. Next, trenches are formed in only a memory cell region through the interlayer dielectric film and the silicon nitride film, such that a side-face of the sidewall is exposed. Another silicon nitride film is deposited along internal walls of the trenches, and a part of the another silicon nitride film formed along the internal walls of the trenches is then removed by etching. Thus, another sidewall acting as a second sidewall is formed adjacently to the first sidewall in the memory cell region.

Abstract: A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in contact with the lower side of the gate electrode side walls, and upper side wall spacers that are composed of silicon nitride films and are in contact with the upper side of the gate electrodes side walls. As a result thereof, a distance is formed between the substrate and the interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurrence of poor contact.

Abstract: A method of producing a semiconductor device includes, in order to electrically connect a lower layer wiring and an upper layer wiring opposite to each other with an interlayer insulation film intervening between them, a step of forming a via-hole, which exposes the lower layer wiring upward from the lower layer wiring through the interlayer insulation film, a step of forming a protective film for preventing erosion, and a step of forming a plug for electrically connecting the lower layer wiring to the upper layer wiring, wherein the protective film is formed by a CVD process in order to cover a residue having stuck to the inner wall of the hole concerned during forming the via-hole.

Abstract: A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

Abstract: The present invention provides a semiconductor contact structure and a method of forming the same. An interlayer dielectric is patterned to form a contact hole that exposes a predetermined region of conductive material on a semiconductor substrate. A recess is formed in the conductive material exposed by the contact hole and undercuts the walls that define the sides of the contact hole such that the recess is wider than the contact hole. A contact plug fills the recess as well as the contact hole. The contact plug is maintained in position stably atop the underlying conductive material because the lower part of the contact plug is wider than the upper part of the contact plug. Accordingly, the contact plug will not fall over even if the interlayer dielectric reflows during a subsequent process.

Abstract: A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

Abstract: A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad having an extension and electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO2 film (insulating film), a via hole provided in the SiO2 film on the extension of the electrode pad, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole, said through hole having a diameter larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.