Abstract: Multiple metallization layers in a partially fabricated integrated circuit are formed in a single process step. As a place-holder for the later-deposited metallization layers, sacrificial material is deposited in the integrated circuit at desired locations at various fabrication levels over a substrate. The sacrificial material is then removed to form a contiguous open volume spanning multiple fabrication levels. A conductor is then deposited in the open volume to form multiple metallization layers in a single step.

Abstract: This invention provides a semiconductor device that can ensure that stress on the nitride film is not increased or is reduced, and that can prevent an increase in interconnection capacity. The semiconductor device comprises a underlayer, a base oxide film that is formed on this underlayer, a nitride film pattern with a hole pattern that is provided on this base oxide film, holes that penetrate the base oxide film, an upper oxide film provided on the base oxide film to cover the nitride film pattern, wiring grooves provided through the upper oxide film in which part of the nitride film pattern including the hole pattern is exposed, and wiring metal that fills the holes and wiring grooves. The nitride film pattern is formed with such a shape and size that surrounds the outside of the wiring grooves and is separate from neighbouring nitride film patterns.

Abstract: A wiring of a semiconductor device and a method of manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate followed by a first insulation material which is deposited on the first conductive layer to form a first insulation layer. Then, a CMP process is implemented to form the first insulation layer. A second insulation layer is formed by depositing a second insulation material on the first insulation layer in order to cover a scratch formed on the first insulation layer after implementing the CMP process. A first etching pattern is formed by etching the second insulation layer to a thickness less than a thickness of the second insulation layer. Thereafter, a conductive material is deposited on the etching pattern and then a planarizing process is implemented to form a conductive pattern having a damascene shape.

Abstract: In accordance with the objectives of the invention a new method and structure is provided for the creation of multiple overlying layers of interconnect metal. A channel is reserved for the creation of via interconnects, no vias are placed on metal lines. The metal lines are stacked and parallel, whereby a space is provided between lines that is reserved for the creation of vias for layer interconnection. This structure can be repeated, the vias are placed on the therefore reserved channel, interconnections are provided to the interconnect traces.

Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

Abstract: In order to reduce micro scratches which tend to occur during chemical-mechanical polishing, a polishing slurry is diluted with deionized water immediately before it is supplied in a gap between a polishing pad and the surface of a wafer to be polished. By diluting the polishing slurry with deionized water to increase its volume, the concentration of coagulated particles contained in the polishing slurry can be lowered. For a mixture ratio of the polishing slurry and deionized water, about 1 (polishing slurry): 1–1.2 (deionized water) is used, and the concentration of silica contained in the diluted polishing slurry is adjusted to about 3–9 weight %, preferably about 4–8 weight %, and more preferably about 8 weight %.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: The present invention relates to a Fine Pitch flip chip substrate. A black oxide dam is made on the metal circuit between bump pads to replace the conventional solder resist so that the bump pads will not be buried in the solder resist. A small via is drilled by laser drilling and plated filled with copper to be used as the connection between the circuits. By this way, the density and the flexibility of routing could be improved. A mesh pattern can be made in the limited space to increase the stiffness of the substrate.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings.

Abstract: An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Abstract: The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Abstract: A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer properties. A third non electrically conductive layer is formed on the second layer. A via hole is etched through the third layer, thereby exposing a portion of the second layer at the bottom of the via hole. The exposed portion of the second layer at the bottom of the via hole is redistributed so that at least a portion of the second layer is removed from the bottom of the via hole and deposited on lower portions of the sidewalls of the via hole. A fourth electrically conductive layer is formed within the via hole to form the electrically conductive via.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy. The invention described in the disclosure provides for advantages including formation of three-dimensional structures without resort to external wiring.

Abstract: A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs.

Abstract: A low k porous dielectric film is described wherein the exposed surface or surfaces of the film are substantially non-porous. A densification method is described for treating such exposed surfaces to render porous surfaces non-porous.

Abstract: A semiconductor device and method of manufacturing the same are disclosed. A conductive structure, spacers and a dielectric layer are formed on a substrate. Thereafter, a portion of the cap layer, a portion of the spacers and a portion of the dielectric layer of the conductive structure are removed to form a funnel-shaped opening. The shoulder section of the conductive layer exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed inside the funnel-shaped opening. Another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed over the substrate.

Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

Abstract: A method for forming a semiconductor device having improved characteristics and reliability by forming a hard mask layer on a bit line to prevent degradation of characteristics of the device in a self-alignment contact process of a storage electrode is disclosed. The hard mask layer utilizes over-hang formed at the upper portion of the bit line so as to provide sufficient protection for the bit line in the subsequent etching processes.

Abstract: A process for fabricating a dual damascene structure of copper has been developed. This process uses a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, thus preventing recessed nitride during the resist stripping process.

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract: The present invention provides methods of fabricating floating gate transistors. One method includes forming laterally spaced source and drain regions to define a channel therebetween, forming a first floating gate portion above the channel region, the first floating gate portion extending in a general horizontal direction, forming spacers over the first floating gate portion to define an exposed region on the first floating gate portion, forming a contact coupled to the first floating gate portion at the exposed region, the contact extending vertically above the first portion, forming a second floating gate portion coupled to the contact, the second floating gate portion extending in a general vertical direction, and forming a control gate adjacent to the second portion.

Abstract: A method of forming an intermetal dielectric (IMD) layer. At least one metal wire is formed on a substrate. A filling oxide layer is formed on the substrate and the metal wire. The surface of the filling oxide layer is smoothed. A first silicon-rich oxide layer is formed on the filling oxide layer, where the refractive index (RI) of the first silicon-rich oxide layer is 1.6˜1.64. A second silicon-rich oxide layer is formed on the first silicon-rich oxide layer, where the refractive index of the second silicon-rich oxide layer is 1.49˜1.55. According to the present method, the diffusion of mobile hydrogen ions is blocked by manufacture with dual silicon-rich oxide layers.

Abstract: Semiconductor devices and methods to form a contact of a semiconductor device are disclosed. An example method to form a contact includes forming an insulating layer on a substrate; etching the insulating layer to form a contact hole; depositing a silicon layer on sidewalls and an undersurface of the contact hole; forming a silicon spacer on the sidewalls of the contact hole by etching the silicon layer; transforming the silicon spacer to a silicon nitride spacer; depositing a diffusion barrier on the silicon nitride spacer; and filling the contact hole with tungsten. Because the silicon nitride spacer formed on the sidewalls of the contact hole can serve as a leakage current blocking layer, the yield and the reliability of the semiconductor devices manufactured by this example process are enhanced.

Abstract: A method of forming a dual-layer resist and application thereof. With respect to the method of forming a dual-layer resist, first, a patterned first resist layer is formed on a substrate. Next, the first resist layer is cured so that the first resist layer does not dissolve in a resist solvent. Finally, a patterned second resist layer is formed on the cured first resist layer. The method of forming a dual-layer resist can be applied to mask ROM coding, hole formation and a dual damascene structure.

Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Abstract: The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a first low dielectric constant insulating film over a semiconductor substrate, forming a photoresist pattern on the first low dielectric constant insulating film, etching the first low dielectric constant insulating film to form a concave portion therein, using the photoresist pattern, burying a conductive film in the concave portion after the photoresist pattern is removed, removing an altered layer formed on a sidewall of the concave portion of the first low dielectric constant insulating film after the conductive film is buried, the altered layer being formed when the photoresist pattern is removed, and forming a second low dielectric constant insulating film so as to fill a gap of the sidewall of the concave portion therewith, the gap resulting from removing the altered layer.

Abstract: A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Abstract: A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.

Abstract: A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

Abstract: A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.

Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Abstract: A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias.

Abstract: A method for forming a metal film including forming a metal barrier layer on a surface of a substrate, on a bottom surface of a recess and on sidewalls of the recess, forming a first metal film on the substrate but not in the recess, treating the first metal film with nitrogen plasma to form an insulation film including nitrogen, forming a second metal film on a portion of the metal barrier layer in the recess, and forming a third metal film on the substrate, the recess and the insulation film.

Abstract: An integrated optical circuit comprising an optical waveguide and an evanescent coupler. The optical waveguide is located on a wafer. The optical waveguide is formed from an upper semiconductor layer of the wafer, a gate oxide layer deposited on the upper semiconductor layer, and a polysilicon layer deposited on the gate oxide layer. The evanescent coupling region is formed at least in part from a gap portion that optically couples light to the upper semiconductor layer of the optical waveguide using the evanescent coupling region. Light can be coupled from outside of the passive optical waveguide device via the evanescent coupling region into the optical waveguide. Alternatively, light can be coupled from the optical waveguide through the evanescent coupling region out of the passive optical waveguide device.

Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.

Abstract: A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).

Abstract: A method for forming a metal interconnect of a semiconductor device defined by a fine trench or via is disclosed. The method includes forming a first interconnect insulating layer on a substrate. A via hole is formed on a predetermined portion of the first interconnect insulating layer. A second interconnect insulating layer is formed on the first interconnect insulating layer. The second interconnect insulating layer is planarized. A hard mask layer is formed on the second interconnect insulating layer. The hard mask layer is patterned to remove selective portions. A trench is formed by etching the second interconnect insulating layer. A metal interconnect is formed in the trench.

Abstract: A method of forming adjacent holes on a semiconductor substrate. The adjacent holes are separated by a fine line structure. The method includes the steps of providing a semiconductor substrate with an insulating layer on the substrate, forming a step-shaped structure, with a first horizontal surface, a second horizontal surface, and a vertical surface, on the surface of the insulating layer, depositing a sacrificial layer with an average thickness, forming a patterned photoresist layer on portions of the first and second horizontal surface, performing an etch-back process to remove the sacrificial layer not covered by the photoresist layer and forming a spacer on the vertical surface, removing the patterned photoresist layer, and using the spacer and the remaining sacrificial layer as a hard mask to remove the insulating layer, thereby forming two adjacent holes.

Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.

Abstract: An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Abstract: A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprise a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate and is etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded in low dielectric material, the coupling capacitance produced therein will be greatly reduced.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.