Abstract: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen.

Abstract: In a method of manufacturing a semiconductor device, a refractory metal film is stacked on a first wiring metal film. An antireflection film is deposited on the refractory metal film. A wiring including the first wiring metal film, the refractory metal film, and the antireflection film is formed, and an interlayer insulating film is formed on the wiring. The interlayer insulating film is etched to form a contact hole so that a surface of the antireflection film corresponds to an uppermost layer of the wiring and an etching by-product is produced on a sidewall of the contact hole. The etching by-product produced on the sidewall of the contact hole is then removed. Thereafter, a portion of the antireflection film located in a bottom portion of the contact hole is removed. A second wiring metal film is then deposited through the contact hole.

Abstract: A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.

Abstract: In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.

Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

Abstract: An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

Abstract: A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.

Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.

Abstract: The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material.

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract: Provided is a circuit board which suppresses abnormal formation of plated layer inside a via, caused by core materials of glass fibers or the like projected from a side wall of the via and which helps to improve the connection reliability of the via. An insulating layer, which is formed of thermoset resin and embedded with glass fibers, is provided between a first wiring layer and a second wiring layer. The glass fibers projected into a via hole side from a side wall of the via hole in different positions are embedded into a via conductor in such a state that the glass fibers are jointed with each other.

Abstract: A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the exposed surface in covered areas of the one or more layers to be patterned and does not cover the exposed surface in bared areas of the one or more layers to be patterned. One or more recesses are formed in the layers to be patterned by at least partially removing the layers to be patterned in the bared areas. The hard-mask layer is ten removed. After removing the hard-mask layer the recess is filled with a filling material.

Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

Abstract: Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so as to cover a sidewall surface of the via-hole and the exposed metal interconnection pattern in conformity with a shape of the via-hole and forming a metal film on the conductive barrier film, wherein there is provided a preprocessing step, after the step of forming the via-hole but before the step of forming the conductive barrier film, of processing the interlayer insulation film including the sidewall surface of the via-hole and a bottom surface of the via-hole, with plasma containing hydrogen having energy not causing sputtering of the metal interconnection pattern.

Abstract: Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the underside of a bond pad on its active surface includes the formation of a blind hole from the back side, application of a passivating layer therein, anisotropically etching to remove passivation material from the blind hole bottom, blanket-depositing at least one conductive layer within the blind hole and over the back side, blanket-depositing a resist in the blind hole and over the back side, planarizing the back side to remove resist and the at least one conductive layer, removing resist from the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.

Abstract: A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.

Abstract: A method of forming a nitrided high-k film by disposing a substrate in a process chamber and forming the nitrided high-k film on the substrate by a) depositing a nitrogen-containing film, and b) depositing an oxygen-containing film, wherein steps a) and b) are performed in any order, any number of times, so as to oxidize at least a portion of the thickness of the nitrogen-containing film. The oxygen-containing film and the nitrogen-containing film contain the same one or more metal elements selected from alkaline earth elements, rare earth elements, and Group IVB elements of the Periodic Table, and optionally aluminum, silicon, or aluminum and silicon. According to one embodiment, the method includes forming a nitrided hafnium based high-k film. The nitrided high-k film can be formed by atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD).

Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.

Abstract: A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper.

Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Abstract: Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time.

Abstract: Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.

Abstract: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.

Abstract: A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.

Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to an improved connection structure for semiconductor devices. A connection structure for a semiconductor device includes: a peanut-shaped opening comprising a narrow area and one or more wide areas, wherein the narrow area is between two of the one or more wide areas; and a conductive plug for filling at least partially the peanut-shaped opening.

Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A method of forming a bit line of a semiconductor device wherein an etch-stop nitride film, a trench oxide film and a hard mask nitride film are formed on a semiconductor substrate. The hard mask nitride film and the trench oxide film are etched to a limited etch thickness of a photo mask. The remaining trench oxide film is etched using the hard mask nitride film as a mask, thus forming a trench. The etch-stop nitride film and the hard mask nitride film are etched on condition that an oxide film has a high selectivity with respect to a nitride film. Accordingly, the loss of a top surface of the trench oxide film can be minimized and a bit line can be formed to have a uniform height. In accordance with the invention, bit line resistance and capacitance variation can be reduced and the reliability of a device can be improved.

Abstract: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.

Abstract: Embodiments of a semiconductor device and a method of fabricating the same may include an insulating layer formed on a substrate and having a predetermined hole, a metal interconnection formed in the hole and protruding relative to the insulating layer, a first barrier extending in a lateral direction of the metal interconnection, a second barrier formed on the metal interconnection, and a metal pad formed on the second barrier.

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses.

Abstract: A wire structure, having: a first insulating layer having a lower layer trench formed in an outer surface thereof; a first diffusion preventing film formed on an inner surface of the lower layer trench; a lower layer wire filled in the lower layer trench over the first diffusion preventing film; an interlayer diffusion preventing film formed on the lower layer wire, the interlayer diffusion preventing film made of a high melt point metal or a high melt point metal compound; a second insulating layer formed over the first insulating layer and the interlayer diffusion preventing film, a second insulating layer having a via hole that penetrates through the second insulating layer and the interlayer diffusion preventing film so as to reach the lower layer wire; a conductive second diffusion preventing film formed on an inner surface of the via hall; a conductor filled in the via hole over the second diffusion preventing film, and an adhering film made of the material that forms the interlayer diffusion preventing

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: A post CMP treating liquid is provided, which includes water, resin particles having, on their surfaces, carboxylic group and sulfonyl group, and a primary particle diameter ranging from 10 to 60 nm, a first surfactant having carboxylic group, a second surfactant having sulfonyl group, and tetramethyl ammonium hydroxide. The resin particles are incorporated at a concentration ranging from 0.01 to 1 wt %. The treating liquid has a pH ranging from 4 to 9, and exhibits a polishing rate both of an insulating film and a conductive film at a rate of 10 nm/min or less.

Abstract: Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one opening within the substrate material. The opening can be characterized by an opening characteristic that includes a depth and an opening width associated with an unknown volume. The method includes a step for providing fill material. Additionally, the method includes a step for processing the fill material to cause a first portion of the fill material to enter the opening and occupy an entirety of the unknown volume associated with the opening characteristic while a second portion of the fill material remains outside of the unknown volume.

Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

Abstract: A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening. A first conductive material is formed over the semiconductor wafer to completely fill the narrower opening and only partially fill the wider opening. The first conductive material is optionally removed from the wider opening using an isotropic etch. A second conductive material is subsequently formed over the semiconductor to completely fill the wider opening.

Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.

Abstract: Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced.

Abstract: Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon.

Abstract: The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate. First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via. The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited. Then, via lithography and via resist pattering are performed. Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched. A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped. As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure.

Abstract: A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film, serving as a capping layer, is formed over the entire surface of a bit line pattern to prevent a tungsten layer, which is a bit line electrode layer, from being oxidized during the high-temperature annealing process. In a process of forming the bit line pattern, over etching is performed to recess a lower interlayer insulating film such that the thickness of the interlayer insulating film to be etched in a subsequent process, that is, a process of etching a storage node contact hole, is reduced. In this way, it is possible to prevent the storage node contact hole from not being opened.

Abstract: A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the sides of the core electrical conductor, embedded portions of the electrically conductive liner in direct physical contact with and extending over the core electrical conductor in regions of the core electrical conductor adjacent to both the top surface and the sides of the core electrical conductor; and an electrically conductive cap in direct physical contact with the top surface of the core electrical conductor that is exposed between the embedded portions of the electrically conductive liner.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under such circumstances, in the present invention, amorphous carbon film 6 is formed on photoresist 4 in which first hole 5 is formed, and using amorphous carbon film 6 as a mask, deep second hole 7 is formed in a etch target material such as underlying SiO2 film 2.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.