Abstract: Methods and an apparatus are described for an integrated circuit within which an electroless Cu plated layer having an oxygen content is formed on the top of a seed layer comprising Cu and Mn. The integrated circuit is then exposed to a sufficient high temperature to cause the self-formation of a MnSiOx barrier layer.

Abstract: A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Abstract: A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.

Abstract: When a mask layer is formed, a first liquid composition containing a mask-layer-forming material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern) to form a first mask layer having a frame shape. A second liquid composition containing a mask-layer-forming material is applied so as to fill a space inside the first mask layer having a frame shape to form a second mask layer. The first mask layer and the second mask layer are formed to be in contact with each other, and the first mask layer is formed to surround the second mask layer. Therefore, the first mask layer and the second mask layer can be used as one continuous mask layer.

Abstract: A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is performed.

Abstract: An electrode for a photoelectric conversion device, a method of preparing the same and a photoelectric conversion device including the same. In one embodiment, an electrode for a photoelectric conversion device includes a transparent conductive layer, a metal electrode layer and an intermediate electrode layer. The transparent conductive layer is formed on a substrate. The metal electrode layer is disposed on the transparent conductive layer to have a pattern. The intermediate electrode layer is interposed between the transparent conductive layer and the metal electrode layer to join the transparent conductive layer and the metal electrode layer. Accordingly, the photoelectric conversion device is enhanced.

Abstract: A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Abstract: Disclosed is a semiconductor device which includes a base substrate; a lower electrode formed on a main surface of the base substrate; and an insulating film formed over the lower electrode and the main surface of the base substrate. The insulating film has a contact hole defined by a wall extending upwardly from the top surface of the lower electrode. The insulating film has a film density distribution in which a film density decreases with increasing distance from the main surface of the base substrate in the thickness direction. A width of the contact hole increases as the film density decreases.

Abstract: A plurality of interconnects is, for example, a plurality of Cu interconnects, extending parallel to each other. Sidewall insulating films are formed at the sidewalls of each of a plurality of interconnects. An air gap is formed between each of a plurality of interconnects, and is located between a plurality of sidewall insulating films. The insulating film is formed on a plurality of interconnects, a plurality of sidewall insulating films, and the air gap. A via passes through the insulating film, and is connected to any of the interconnects. The sidewall insulating film is formed of a material having an etching rate lower than that of the insulating film in the conditions in which the insulating film is etched.

Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.

Abstract: In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided.

Abstract: A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (4, 5) defining the position of the via and metallic line of the upper metallization level; etching the insulating region through the hard mask so as to form a cavity; cleaning the cavity (which forms an undercut at the interface between the hard mask and the insulating region); and completely filling the cavity. The step of completely filling includes at least partially filling the cavity with copper and plugging the undercut. The undercut is plugged by sputtering a plugging material and forming an overlying doped copper layer.

Abstract: Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode, wherein forming the dielectric stack structure includes creating a second region between a first region and a third region of the dielectric stack structure, the second region having a thermal conductivity different than a thermal conductivity of the first region and different than a thermal conductivity of the third region of the dielectric stack. One or more embodiments include forming a via through the first, second, and third regions of the dielectric stack structure, depositing a phase change material in the via, and forming a second electrode on the phase change material.

Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.

Abstract: Methods and compositions for the deposition of ternary oxide films containing ruthenium and an alkali earth metal.

Abstract: A wiring substrate includes a substrate body including a first substrate surface and a second substrate surface, a trench being open toward the first substrate surface, the trench having an inner bottom surface and an inner side surface, a through-hole having a first end communicating with the inner bottom surface of the trench and a second end being open toward the second substrate surface, a first conductive layer having a first surface toward the trench and being filled inside at least a portion of the through-hole from the second end, a second conductive layer covering the first surface and at least a part of the inner bottom surface of the trench, and a third conductive layer covering the second conductive layer and being filled inside the trench.

Abstract: An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Abstract: A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads.

Abstract: Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound.

Abstract: A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of forming a plurality of longitudinal hole-shaped fine pores in the wiring interlayer film in a thickness direction of the wiring interlayer film by etching with a mask including one of nano-particles and material including nano-particles.

Abstract: Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.

Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.

Abstract: A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.

Abstract: A silicon film formation method includes a first film formation operation, an etching operation, and a second film formation operation. In the first film formation operation, a first silicon film is formed to fill the groove of the object to be processed. In the etching operation, an opening of the groove is widened by etching the first silicon film formed in the first film formation operation. In the second film formation operation, a second silicon film is formed on the groove having the opening widened in the etching operation to fill the groove. Accordingly, a silicon film is formed on a groove of an object to be processed having the groove provided thereon.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ?40, usefully ?10 and preferably ?5.

Abstract: A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 ?m to 1.0 ?m. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.

Abstract: A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and one or more polymerizable diluents, the diluents constituting at least 50% by weight of the composition.

Abstract: The present invention relates to an etchant for etching metal wiring, and the metal wiring etchant according to the present invention includes hydrogen peroxide at about 5 wt % to about 15 wt %, an oxidant at about 0.5 wt % to about 5 wt %, a fluoride-based compound at about 0.1 wt % to about 1 wt %, a nitrate-based compound at about 0.5 wt % to about 5 wt %, and a boron-based compound at about 0.05 wt % to about 1 wt %.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: A method for fabricating a semiconductor device includes: (a) forming an interlayer insulating film on a substrate; (b) forming an interconnect in the interlayer insulating film; (c) applying an organic solution to an upper surface of the interconnect and an upper surface of the interlayer insulating film; (d) after (c), applying a silylating solution to the upper surface of the interconnect and the upper surface of the interlayer insulating film; (e) after (d), heating the substrate; and (f) forming a first liner insulating film at least on the upper surface of the interconnect.

Abstract: Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers.

Abstract: A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.

Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

Abstract: Provided are methods of manufacturing semiconductor devices. The methods may include forming a first insulation layer on a semiconductor substrate, forming a groove by selectively etching the first insulation layer, filling the groove with a copper-based conductive layer, depositing a cobalt-based capping layer on the copper-based conductive layer by electroless plating, and cleansing the first insulation layer and the cobalt-based capping layer using a basic cleansing solution.

Abstract: Disclosed is a semiconductor device including: a substrate; a wiring layer formed on the substrate and made of copper or a copper alloy; a copper diffusion barrier film formed on the wiring layer and made of an amorphous carbon film formed by CVD using a processing gas containing a hydrocarbon gas; and a low-k insulating film formed on the copper diffusion barrier film.

Abstract: In the present invention, to keep the conductive paste from flowing, an organic layer is formed on the substrate, following which the conductive paste is printed and fired. An electrode could be formed with a method comprising steps of: applying an organic paste onto one side of a substrate so as to form an organic layer; applying a conductive paste onto the organic layer; and firing the conductive paste so as to form an electrode and burn off the organic layer.

Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.