Abstract: Provided is a heat treatment apparatus in which a heat treatment apparatus in which the thermal efficiency is high, the maintenance expense is low, the throughput is high, the surface roughness of a sample can be reduced, and the discharge uniformity is excellent, although the heat treatment is performed at 1200 ° C. or more. A heat treatment apparatus includes: parallel planar electrodes; a radio-frequency power supply generating plasma by applying radio-frequency power between the parallel planar electrodes; a temperature measuring section measuring the temperature of a heated sample; and a control unit controlling an output of the radio-frequency power supply, wherein at least one of the parallel planar electrodes has a space where the heated sample is installed, therein, and heats the sample in the electrode by the plasma generated between the parallel planar electrodes.

Abstract: A method for producing a micromechanical and/or nanomechanical device includes partial etching of at least one sacrificial layer arranged between a first layer and a substrate, forming at least one cavity in which is arranged at least one portion of the sacrificial layer in contact with the first layer and/or the substrate. The method also includes chemical transformation of at least one wall of the first layer and/or the substrate in the cavity, delimiting at least one stop in the first layer and/or the substrate at the level of the portion of the sacrificial layer. The portion of the sacrificial layer and the chemically transformed wall of the first layer and/or the substrate is also eliminated.

Abstract: A method for fabricating a semiconductor device is described. A substrate is provided having a patterned dielectric layer disposed thereon. A trench is formed in the dielectric layer. The surfaces of the trench are treated with an ammonia-based plasma process. A metal layer is then formed in the trench.

Abstract: Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

Abstract: One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

Abstract: A method of forming a thin film interconnect in which a film is formed by sputtering method using a Cu—Ca alloy target and a thin film interconnect formed by the method, the method comprising: forming a Cu—Ca alloy film by sputtering method using a Cu—Ca alloy target that contains 0.5 atomic % or more and less than 5 atomic % of Ca, and the balance consisting of Cu and unavoidable impurities; and performing heat treatment of the Cu—Ca alloy film at a temperature of 300 to 700° C. in an inert gas atmosphere containing trace amount of oxygen defined by oxygen partial pressure in the range of 10?4 to 10?10 atm.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.

Abstract: It is intended to provide a production method that enables at least one of improvement in transparency, reduction in sheet resistance, homogenization in planar distribution of sheet resistance, and reduction in contact resistance related to a contact layer regarding a transparent conductive oxide film included in a compound semiconductor light-emitting device. A method for producing a compound semiconductor light-emitting device includes depositing on a substrate a compound semiconductor stacked-layer body including a light-emitting layer, depositing a transparent conductive oxide film on the compound semiconductor stacked-layer body, and annealing the transparent conductive oxide film and thereafter cooling the same in a vacuum atmosphere.

Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.

Abstract: A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.

Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

Abstract: The present invention provides a thick-film paste for printing the front-side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal, and a lead-tellurium-oxide dispersed in an organic medium.

Abstract: In a method of manufacturing a semiconductor device, a front end of line (FEOL) process may be performed on a semiconductor substrate to form a semiconductor structure. A back end of line (BEOL) process may be performed on the semiconductor substrate to form a wiring structure electrically connected to the semiconductor structure, thereby formed a semiconductor chip. A hole may be formed through a part of the semiconductor chip. A preliminary plug may have a dimple in the hole. The preliminary plug may be expanded into the dimple by a thermal treatment process to form a plug. Thus, the plug may not have a protrusion protruding from the upper surface of the semiconductor chip, so that the plug may be formed by the single CMP process.

Abstract: According to one embodiment, a semiconductor manufacturing apparatus has a chamber, a microwave generator for generating a microwave, a waveguide for introducing the microwave into the chamber, a stage for mounting a semiconductor substrate, and a cover for covering an outer circumference portion of the stage exposed from the semiconductor substrate. In the semiconductor manufacturing apparatus, the stage is made of a material to be heated by the microwave, and the cover is made of a material through which the microwave penetrates.

Abstract: A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV. A metal based contact is formed in the contact region. The metal based contact has a depth DC which is equal to about DV. The vacancy defects lower the resistance of the metal based contact with the substrate.

Abstract: Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.

Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

Abstract: A device of filling metal in a through-via-hole formed in a semiconductor wafer and a method of filling metal in a through-via-hole using the same are disclosed. A device of filling metal in a through-via-hole formed in a semiconductor wafer includes a jig base comprising a jig configured to fix the wafer having the through-via-hole formed therein; a upper chamber 120 installed on the jig base; a lower chamber installed under the jig base; a heater installed in the upper chamber, the heater configured to apply heat to filling metal placed on the wafer to melt the filling metal; and a vacuum pump configured to generate pressure difference between the upper chamber and the lower chamber by the pressure of the lower chamber reduced by discharging air of the lower chamber 130 outside, only to fill the melted filling metal in the through-via-hole.

Abstract: A process of forming a front-grid electrode on a silicon wafer having an ARC layer, comprising the steps: (1) printing and drying a metal paste A comprising an inorganic content comprising 0.5 to 8 wt.-% of glass frit and having fire-through capability, wherein the metal paste A is printed on the ARC layer to form a bottom set of thin parallel finger lines, (2) printing and drying a metal paste B comprising an inorganic content comprising 0.2 to 3 wt.-% of glass frit over the bottom set of finger lines, wherein the metal paste B is printed in a grid pattern which comprises (i) thin parallel finger lines forming a top set of finger lines superimposing the bottom set of finger lines and (ii) busbars intersecting the finger lines at right angle, and (3) firing the double-printed silicon wafer, wherein the inorganic content of metal paste B contains less glass frit plus optionally present other inorganic additives than the inorganic content of metal paste A.

Abstract: Provided is a Cu electrical interconnection film forming method, wherein an adhesive layer (base film) having improved adhesiveness with a Cu electrical interconnection film is used, in a semiconductor device manufacturing process. After forming a barrier film on a substrate whereupon a hole or the like is formed, a PVD-Co film or a CVD-Co film or an ALD-Co film is formed on the barrier film. Then, after filling up or burying the hole or the like, which has the Co film formed on the surface, with a CVD-Cu film or a PVD-Cu film, heat treatment is performed at a temperature of 350° C. or below, and the Cu electrical interconnection film is formed.

Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Abstract: A conductive thick-film paste composition is useful in forming conductive structures on the front side of a solar cell or other like device. The paste composition has a source of electrically conductive metal, such as silver powder, one or more glass components, and an optional zinc-containing additive, which are dispersed in an organic medium containing a surfactant.

Abstract: A conductive paste composition contains a source of an electrically conductive metal, a fusible material, a synthetic clay additive, and an optional etchant additive, dispersed in an organic medium. An article such as a photovoltaic cell is formed by a process having the steps of deposition of the paste composition on a semiconductor substrate by a process such as screen printing and firing the paste to remove the organic medium and sinter the metal and fusible material. The synthetic clay additive aids in establishing a low resistance electrical contact between the front side metallization and underlying semiconductor substrate during firing.

Abstract: A lead-free conductive paste composition contains a source of an electrically conductive metal, a fusible material, an optional additive, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the lead-free paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and fusible material.

Abstract: A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost.

Abstract: Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method of fabricating single-crystalline metal silicide nanowires for anti-reflective electrodes for photovoltaics is provided that includes exposing a surface of a metal foil to oxygen or hydrogen at an elevated temperature, and growing metal silicide nanowires on the metal foil surface by flowing a silane gas mixture over the metal foil surface at the elevated temperature, where spontaneous growth of the metal silicide nanowires occur on the metal foil surface, where the metal silicide nanowires are post treated for use as an electrode in a photovoltaic cell or used directly as the electrode in the photovoltaic cell.

Abstract: A method of forming a non-volatile memory device includes providing a substrate having a surface and forming a first dielectric overlying the surface, forming a first wiring comprising aluminum material over the first dielectric, forming a silicon material over the aluminum material to form an intermix region consuming a portion of the silicon material and aluminum material, annealing to formation a first alloy from the intermix region, forming a p+ impurity polycrystalline silicon over the first alloy material, forming a first wiring structure from at least a portion of the first wiring, forming a resistive switching element comprising an amorphous silicon material formed over the p+ polycrystalline silicon, and forming a second wiring structure comprising at least a metal material over the resistive switching element.

Abstract: A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e.g., photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.

Abstract: Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of the n-type compound semiconductor layer, and an n-type electrode formed on a second region separated from the first region of the n-type compound semiconductor layer, wherein the p-type electrode comprises first and second electrodes, each electrode having different resistance and reflectance.

Abstract: A method for producing an electrical feedthrough in a substrate includes: forming a first printed conductor on a first side of a substrate which electrically connects a first contact area of the substrate on the first side; forming a second printed conductor on a second side of a substrate which electrically connects a second contact area of the substrate on the second side; forming an annular trench in the substrate, a substrate punch being formed which extends from the first contact area to the second contact area; and selectively depositing an electrically conductive layer on an inner surface of the annular trench, the substrate punch being coated with an electrically conductive layer and remaining electrically insulated from the surrounding substrate due to the annular trench.

Abstract: The invention provides a method of manufacturing a semiconductor device, capable of forming, on a silicon layer, a nickel mono-silicide layer having a low resistance value and a desirable flatness. The method includes depositing a platinum-containing nickel layer that covers the silicon layer formed on the substrate, and that has crystallinity lower in a portion thereof close to the silicon layer than in a portion remote from the silicon layer, and forming a nickel mono-silicide layer at the interface between the silicon layer and the platinum-containing nickel layer by heating the substrate.

Abstract: A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Abstract: In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.

Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.

Abstract: The method comprises affixing a thin sheet of crystal (8) onto metal (6) of same type as the sheet but amorphous or of small grain size, deposited in trenches of a substrate (1) to form interconnect lines for example. Annealing progressively imposes the crystalline structure of the sheet onto the lines. When the crystal (8) is removed, highly conductive crystalline lines are obtained since the grains thereof have been greatly enlarged.

Abstract: The present invention relates to a method for enhancing uniformity of metal oxide coatings formed by Atomic Layer Deposition (ALD) or ALD-type processes. Layers are formed using alternating pulses of metal halide and oxygen-containing precursors, preferably water, and purging when necessary. An introduction of modificator pulses following the pulses of the oxygen-containing precursor affects positively on layer uniformity, which commonly exhibits gradients, particularly in applications with closely arranged substrates. In particular, improvement in layer thickness uniformity is obtained. According to the invention, alcohols having one to three carbon atoms can be used as the modificator.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: In one embodiment, a method of opening a passageway to a cavity includes providing a donor portion, forming a heating element adjacent to the donor portion, forming a first sacrificial slab abutting the donor portion, wherein the donor portion and the sacrificial slab are a shrinkable pair, forming a first cavity, a portion of the first cavity bounded by the first sacrificial slab, generating heat with the heating element, forming a first reduced volume slab from the first sacrificial slab using the generated heat and the donor portion, and forming a passageway to the first cavity by forming the first reduced volume slab.

Abstract: Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

Abstract: Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer.

Abstract: A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.

Abstract: A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.