Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a halogen and carbon containing gas source. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

Abstract: A contact hole, after hole etching, is subjected to light etching using a process gas containing a fluorocarbon-based gas and oxygen, with the oxygen being enriched, under condition without applying bias. Then, reaction products (5) having C—F bond and adhered to an interior of a hole (3) are removed using plasma treatment. After that, deposits (4) that have been left at a hole bottom are removed by wet processing. Then, a conductive material is buried in the hole to form a contact plug (7).

Abstract: A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent from each other, the micro-electro-mechanical structures have an exposed portion on the surface of the insulation layer, and the exposed portion is provided with through holes or stacked metal-via layers correspondingly to the predetermined etching spaces of the micro-electro-mechanical structures, the above predetermined etching spaces and the stacked metal-via layers only penetrate the insulation layer; forming a photoresist with an opening on the upper surface of the exposed portion, and the opening of the photoresist is located outside all the through holes or the stacked metal-via layers; subsequently, conducting etching to realize the suspension of t

Abstract: A method and system for adjusting and controlling the plasma uniformity in a plasma processing system is described. The plasma processing system includes an electron source electrode to which direct current (DC) power is coupled in order to generate a ballistic electron beam during the etching of the substrate. A ring electrode, provided about a periphery of the substrate and opposite the electron source electrode, is utilized to create a ring hollow cathode plasma to affect changes in the distribution of plasma density.

Abstract: A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.

Abstract: Semiconductor wafers are cut from a crystal and subjected to a series of processing steps in which material is removed from a front side and a rear side of the semiconductor wafers, comprising the following processing steps: a mechanical processing step, an etching step in which the semiconductor wafers are oxidized and material is removed from the front side of the wafers with the aid of a gaseous etchant containing hydrofluoric acid at a temperature of 20 to 70° C., and a polishing step in which the front side of the semiconductor wafer is polished, the processing steps in which the front side of the semiconductor wafer is polished causing material removal which does not amount to more than 5 ?m in total.

Abstract: The present invention provides a method of etching features in a substrate. The method comprising the steps of placing the substrate on a substrate support in a vacuum chamber. An alternatingly and repeating process is performed on the substrate until a predetermined trench depth and a predetermined sidewall angle are achieved. One part of the process is a deposition step which is carried out by introducing at least one polymer containing gas into the vacuum chamber. A plasma is ignited from the polymer containing gas which is then used to deposit a polymer on the substrate. The other part of the alternatingly and repeating process is an etching step which is carried out by introducing an etchant containing gas, a polymer containing gas and a scavenger containing gas into the vacuum chamber. A plasma is ignited from the etchant containing gas, the polymer containing gas and the scavenger containing gas which is then used to etch the substrate.

Abstract: A method. A combination is provided of a block copolymer and additional material. The copolymer includes a first block of a first polymer covalently bonded to a second block of a second polymer. The additional material is miscible with the first polymer. The first polymer includes polystyrene and the second polymer includes poly(ethylene oxide). A first layer including polydimethylglutarimide is adhered onto a surface of a substrate including a dielectric coated silicon wafer. A film is formed of the combination directly onto a surface of the first layer. Nanostructures of the additional material self-assemble within the first polymer block. The film and the first layer are simultaneously etched. The nanostructures have an etch rate lower than an etch rate of the block copolymer and lower than an etch rate of the first layer. Portions of the film are removed. Features remain on the surface of the first layer.

Abstract: An acoustic device includes a transducer formed on a first surface of a substrate and an acoustic horn formed in the substrate by a dry-etching process through an opposing second surface of the substrate. The acoustic horn is positioned to amplify sound waves from the transducer and defines a non-linear cross-sectional profile.

Abstract: A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: {(SiO1.5—Y—SiO1.5)x(R3SiO1.5)y(XSiO1.5)z}(OH)e(OR6)f??(1).

Abstract: There is provided a method of mounting one conductive ball on each of a plurality of connection pads on a substrate. The method includes: (a) providing a pre-alignment base including: a support layer formed to allow a flux to pass therethrough; and an alignment layer provided on the support layer and having pockets for containing the conductive ball; (b) applying a paste containing the conductive balls dispersed in the flux onto the alignment layer such that each of the pockets receives one of the conductive balls together with the flux; (c) aligning the pre-alignment base with the substrate such that each of the pockets corresponds to one of the connections pads; and (d) transferring the paste contained in each of the pockets onto the connection pads, thereby mounting the conductive balls along with the flux on the connection pads.

Abstract: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

Abstract: A system for semiconductor wafer manufacturing, comprises a chamber process path for processing the wafer, and a device operable to remove particles from the wafer by electrostatic and electromagnetic methodologies wherein the device is installed in the chamber process path.

Abstract: Elemental fluorine and carbonyl fluoride are suitable etchants for producing microelectromechanical devices (“MEMS”). They are preferably applied as mixtures with nitrogen and argon. If applied in Bosch-type process, C4F6 is a highly suitable passivating gas.

Abstract: A semiconductor package includes a rewiring substrate and a semiconductor chip. The semiconductor chip includes: a first face with an active surface including integrated circuit devices and chip contact pads, a second face lying in a plane essentially parallel to the first face and side faces. Each side face of the semiconductor chip lies in a plane essentially perpendicular to the first and second faces. At least one edge between two mutually essentially perpendicular faces of the semiconductor chip includes a surface.

Abstract: A surface processing method includes supporting a wafer in a vacuum chamber and generating a plasma in a confined portion of the chamber over only a selected portion of the wafer to thereby perform a surface processing treatment (e.g., an ashing process) on the selected portion of the wafer. While the plasma is being generated, the wafer and the confined portion of the chamber are displaced with respect to one another to thereby perform the surface processing treatment on a second selected portion of the wafer.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: In one embodiment of the present invention, a halogen-free plasma etch processes is used to define a feature in a multi-layered masking stack including an amorphous carbon layer. In a particular embodiment, oxygen (O2), nitrogen (N2), and carbon monoxide (CO) are utilized to etch the amorphous carbon layer to form a mask capable of producing sub-100 nm features in a substrate film having a reduced line edge roughness value. In another embodiment, the present invention employs an O2 plasma pretreatment preceding the halogen-free amorphous carbon etch to first form an oxidized silicon region in a patterned photoresist layer to increase the selectivity of the amorphous carbon etch relative to a patterned photoresist layer containing unoxidized silicon.

Abstract: An etching method in a semiconductor device includes forming a nitride-based first hard mask layer over a target etch layer, forming a carbon-based second hard mask pattern over the first hard mask layer, etching the first hard mask layer using the second hard mask pattern as an etch barrier to form a first hard mask pattern, cleaning a resultant structure including the first hard mask pattern, and etching the target etch layer using the second hard mask pattern as an etch barrier.

Abstract: An oxygen-free hydrogen plasma ashing process particularly useful for low-k dielectric materials based on hydrogenated silicon oxycarbide materials. The main ashing step includes exposing a previously etched dielectric layer to a plasma of hydrogen and optional nitrogen, a larger amount of water vapor, and a yet larger amount of argon or helium. Especially for porous low-k dielectrics, the main ashing plasma additionally contains a hydrocarbon gas such as methane. The main ashing may be preceded by a short surface treatment by a plasma of a hydrogen-containing reducing gas such as hydrogen and optional nitrogen.

Abstract: A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

Abstract: The present invention provides a plasma processing apparatus or a plasma processing method that can etch a multilayer film structure for constituting a gate structure with high accuracy and high efficiency. A plasma processing method of, on processing a sample on a sample stage 112 in a depressurized discharge room 117, etching a multilayer film (including a high-k and a metal gate) at 0.1 Pa or less and with the sample stage 112 temperature-regulated by using a pressure gauge 133 to be used for pressure regulation and connected to the processing room and a main pump for exhaustion 130.

Abstract: Described herein are exemplary methods and apparatuses for etching a nitride layer disposed above a substrate to form trenches without micro-trenching in accordance with one embodiment. The method includes forming openings in a resist layer and one or more dielectric layers. The dielectric layers may be disposed on a hard mask layer (e.g., nitride, polysilicon). Next, the method includes etching openings in the hard mask layer disposed above a substrate layer without micro-trenching. The etching occurs in a process chamber during a main etch with a first process gas mixture having a fluorocarbon gas, a hydrofluorocarbon gas, and an oxygenating gas. Next, the method includes etching openings partially into the substrate without micro-trenching with a second process gas mixture during an over etch having the fluorocarbon gas, the hydrofluorocarbon gas, and the oxygenating gas.

Abstract: The present invention provides a residue-removing solution for use after a dry process, the residue-removing solution being capable of preventing minute cracks on a Cu surface, which has heretofore been unresolved with known polymer-removing solutions; and a method for manufacturing semiconductor devices using the residue-removing solution. More specifically, the invention relates to a residue-removing solution for removing residues present on semiconductor substrates after dry etching and/or ashing, the solution containing water and at least one component selected from the group consisting of (a) a keto acid, (b) a keto acid salt, and (c) an aldehyde acid salt; and a method for removing residues using the residue-removing solution.

Abstract: A susceptor configured to be coupled to a material processing system is described. The susceptor comprises a substrate support comprising a central portion and an edge portion, wherein the central portion has a support surface configured to receive and support a substrate, and the edge portion extends beyond a peripheral edge of the substrate. The susceptor further comprises an edge reflector coupled to the edge portion of the substrate support and configured to partially or fully shield the peripheral edge of the substrate from radiative exchange with an outer region of the material processing system.

Abstract: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.

Abstract: A method of fabricating patterns of a semiconductor device includes the steps of forming first sacrificial layer patterns over a pattern target layer; forming first spacers on sidewalls of the first sacrificial layer patterns; forming a second sacrificial layer pattern over the first sacrificial layer patterns and the first spacers such that at least one of the first spacers is exposed by the second sacrificial layer pattern; forming a dual spacer by forming a second spacer on the exposed first spacer; removing the second sacrificial layer pattern and the first sacrificial layer patterns; and forming a first pattern having a first pitch defined by the first spacers and a second pattern having a second pitch defined by the dual spacer by etching an exposed portion of the pattern target layer using the first spacers and the dual spacer as etching masks.

Abstract: A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.

Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.

Abstract: The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F2 gas, an XeF2 gas, and a ClF3 gas, to the substrate; and after the etching of the silicon oxide film and the etching of the silicon, heating and removing the condensation layer from the substrate.

Abstract: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the film deposited during the first etching has been removed to an extent that further exposure to the etchant may remove the liner and expose underlying structures. Accordingly, the etching is stopped upon detection of distinctive reaction products and the next deposition in the deposition/etching/deposition process is begun.

Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.

Abstract: A method for removing a damaged dielectric material following an etch process, an ashing process, or a wet cleaning process is described. A dry, non-plasma removal process is implemented to remove a thin layer of damaged material on a feature following formation of the feature. The dry, non-plasma removal process includes a chemical treatment of the damaged material, followed by a thermal treatment of the chemically treated surface layer. The two steps, chemical and thermal treatment, can be repeated.

Abstract: A plasma etching method includes the step of: etching a silicon layer of a target object by using a plasma generated from a processing gas containing a fluorocarbon gas, a hydrofluorocarbon gas, a rare gas and an O2 gas and by employing a patterned resist film as a mask. The target object includes the silicon layer whose main component is silicon and the patterned resist film formed over the silicon layer.

Abstract: An etching gas for etching an oxide film formed on a substrate, includes a main gas composed of an unsaturated fluorocarbon-based gas; and an additive gas composed of a straight-chain saturated fluorocarbon-based gas expressed by CXF(2X+2) (x represents a natural number of 5 or larger). The additive gas is C5F12 gas, C6F14 gas or C7F16 gas. Another etching gas includes a main gas composed of an unsaturated fluorocarbon-based gas; and an additive gas composed of a cyclic saturated fluorocarbon-based gas expressed by CXF2X (X represents a natural number of 5 or larger). In this case, the additive gas is C5F10 gas or C6F12 gas.

Abstract: The invention involves a method of processing a workpiece on workpiece support pedestal in a plasma reactor chamber in accordance with user-selected values of plural (i.e., N) plasma parameters by controlling plural chamber parameters. The plasma parameters may be selected from of a group including ion density, wafer voltage, etch rate, wafer current and possibly other plasma parameters. The chamber parameters may be selected from a group including source power, bias power, chamber pressure, magnet coil current of different coils, gas flow rate in different gas injection zones, gas species composition in different gas injection zones, and possibly other chamber parameters. The method begins with a first step carried out for each one of the selected plasma parameters.

Abstract: A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed.

Abstract: A method of manufacturing a semiconductor device includes a process of removing, by dry etching, an insulating layer which is formed on the top surface of a Ni-containing silicide layer to thereby at least partially expose the Ni-containing silicide layer; and a process of cleaning the exposed portion of the Ni-containing silicide layer using reduced water having a reductive function.

Abstract: Methods for etching quartz are provided herein. In one embodiment, a method of etching quartz includes providing a film stack on a substrate support disposed in a processing chamber, the film stack having a quartz layer partially exposed through a patterned layer; and etching the quartz layer of the film stack in a multi-step process including a first step of etching the quartz layer utilizing a first process gas comprising at least one fluorocarbon process gas and a chlorine-containing process gas; and a second step of etching the quartz layer utilizing a second process gas comprising at least one fluorocarbon process gas.

Abstract: Additional variants of the method of etching structures into an etching body, in particular recesses in a silicon body that are laterally defined in a precise manner by an etching mask, using a plasma, is described. In addition, the use of this method in the introduction of structures, in particular trenches having a high aspect ratio, into a dielectric layer or a dielectric base body and in a layer of silicon is described, isotropic underetching and/or isotropic, sacrificial-layer etching, in particular using fluorine radicals or a highly oxidizing fluorine compound such as ClF3, being performed after the production of the structures in at least some areas in the case of the layer made of silicon.

Abstract: [Object] To provide a processing method capable of removing an oxide film adhering on a Si layer from the Si layer without adversely affecting parts other than the oxide film and capable of surely forming a SiGe layer with good film quality without roughening the crystal structure of a surface of the Si layer from which the oxide film has been removed, and to provide a recording medium. [Means for Solving the Problems] A processing method for removing an oxide film growing on a surface of a Si layer, and forming a SiGe layer on the surface of the exposed Si layer includes: supplying gas containing a halogen element and basic gas to the surface of the Si layer, and causing the oxide film growing on the surface of the Si layer to chemically react with the gas containing the halogen element and the basic gas to turn the oxide film into a reaction product; removing the reaction product by heating; and thereafter forming the SiGe layer on the surface of the exposed Si layer.

Abstract: A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

Abstract: A system and a method to remove a layer of high-k dielectric material during the manufacturing of an integrated circuit. In one embodiment of the invention, an etch reactant is employed to form volatile etch products when reacted with high-k layers. Alternately, high-k layers can be anisotropically etched of in accordance with a patterned photoresist or hard mask, where a hyperthermal beam of neutral atoms is used to aid in the reaction of an etch reactant with a high-k layer. Alternately, a hyperthermal beam of neutral atoms or a plasma treatment can used to modify a high-k layer, and subsequently etch the modified high-k layer utilizing an etch reactant that reacts with the modified high-k layer. In still another embodiment of the invention, the hyperthermal beam of neutral atoms is used to etch a high-k layer through physical bombardment of the high-k layer.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.

Abstract: A method for forming a CMOS image sensor (CIS) in accordance with embodiments includes sequentially forming a first photoresist and a blocking layer over a semiconductor substrate where a logic section including a photodiode may be formed. A micro lens array pattern may be formed by coating a second photoresist over top of the formed blocking layer, patterning the second photoresist, and then etching the blocking layer by using the patterned second photoresist as a mask. The first photoresist may be patterned by performing isotropic etching using the micro lens array pattern as a mask. A micro lens array may be formed by filling a material having a refractivity higher than that of the first PR in the patterned portion of the first photoresist. The sensitivity of the CIS can be optimized by maximizing the fill factor while maintaining the spherical surface of the lens by fabricating a micro lens array using anisotropic etching.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate, forming a second hard mask layer pattern over the first hard mask layer, forming a spacer on a sidewall of the second hard mask layer pattern, selectively etching the first hard mask layer by using the spacer and the second hard mask layer pattern as an etching mask to form a first hard mask layer pattern, forming a first insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer pattern and the underlying first hard mask layer pattern to form a third hard mask layer pattern, removing the first insulating film and the spacer, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask to form a fine pattern.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.