Abstract: A manufacturing method of a semiconductor device is provided to manufacture an increased number of semiconductor devices per single substrate such as, e.g., a wafer while obviating damages like those caused by conventional dicing method. The manufacturing method comprises steps of performing a first etching process to etch a separation area on a front surface of a substrate, arranging a supporter on a back surface of the first substrate to prevent semiconductor devices from coming apart, coating with a thin film a non-etching area including a sidewall of the etched separation area and excluding a bottom of the etched separation area on the front surface of the first substrate, and performing a second etching process to etch the first substrate from the front surface through an area not coated by the thin film to divide the substrate into multiple semiconductor devices.

Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.

Abstract: A processing system is disclosed for conducting various processes on substrates, such as semiconductor wafers by varying the exposure to a chemical ambient. The processing system includes a processing region having an inlet and an outlet for flowing fluids through the chamber. The outlet is in communication with a conductance valve that is positioned in between the processing region outlet and a vacuum exhaust channel. The conductance valve rapidly oscillates or rotates between open and closed positions for controlling conductance through the processing region. This feature is coupled with the ability to rapidly pulse chemical species through the processing region while simultaneously controlling the pressure in the processing region. Of particular advantage, the conductance valve is capable of transitioning the processing region through pressure transitions of as great as 100:1 while chemical species are flowed through the processing region using equally fast control valves in a synchronous pulsed fashion.

Abstract: In a film formation method for a semiconductor process, a target substrate having a target surface with a natural oxide film is loaded into a reaction chamber, while setting the reaction chamber at a load temperature lower than a threshold temperature at which the natural oxide film starts being stabilized. Then, the natural oxide film is removed by etching, while supplying an etching gas containing chlorine without containing fluorine, and setting the reaction chamber at an etching pressure and an etching temperature lower than the threshold temperature. Then, the reaction chamber is purged. Then, a thin film is formed on the target surface by CVD, while supplying a film formation gas, and setting the reaction chamber at a film formation temperature.

Abstract: In an apparatus and method of vapor etching, a sample (S) to be etched is located in a main chamber (107) from which the atmosphere inside is evacuated. Etching gas is input into the main chamber (107) for a first period of time. Thereafter, the etching gas is evacuated from the main chamber (107) and cooling/purging gas is input into the main chamber for a second interval of time. Thereafter, the cooling/purging gas is evacuated from the main chamber (107). Desirably, the steps of inputting the etching gas into the main chamber (107) for the first period of time, evacuating the etching gas from the main chamber, inputting the cooling/purging gas into the main chamber (107) for the second period of time, and evacuating the cooling/purging gas from the main chamber are repeated until samples have been etched to a desired extent.

Abstract: A method for removing a mask layer and reducing damage to a patterned dielectric layer is described. The method comprises disposing a substrate in a plasma processing system, wherein the substrate has a dielectric layer formed thereon and a mask layer overlying the dielectric layer. A pattern is formed in the mask layer and a feature formed in the dielectric layer corresponding to the pattern as a result of an etching process used to transfer the pattern in the mask layer to the dielectric layer. The feature includes a sidewall with a first roughness resulting from the etching process. A process gas comprising CO2 and CO is introduced into the plasma processing system, and plasma is formed. The mask layer is removed, and a second roughness, less than the first roughness, is produced by selecting a flow rate of the CO relative to a flow rate of the CO2.

Abstract: A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench.

Abstract: In a semiconductor device manufacturing method according to this invention, an SiO2 film used as a mask at the time of trench formation is removed by a wet process after hydrophilic treatment is performed on the interior of a hydrophobic trench.

Abstract: A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.

Abstract: A method for correcting a mask pattern used for dry-etching an object with higher accuracy, and for manufacturing an acceleration sensor and an angular velocity sensor. The object is first etched by a dry-etching process using an uncorrected reference mask pattern. Then, distribution of the size of expansion of a tapered portion formed in a surface of the object is measured. Thereafter, the measured distribution is approximated by using a quadratic curve (Y=AX2+B) so as to determine A and B. Consequently, an amount t of correction for the tapered portion, which is expressed by the following equation (1) and related to a width of an opening of the mask pattern in a position at a distance r from a center of the object to be etched, can be set. In this way, the correction for the tapered portion can be carried out.

Abstract: Provided herein are hardmask compositions that include an organosilane polymer prepared by the reaction of one or more compounds of Formula (I) Si(OR1)(OR2)(OR3)R4 wherein R1, R2 and R3 may each independently be alkyl acetoxy or oxime; and R4 may be hydrogen, alkyl, aryl or arylalkyl; and wherein the organosilane polymer has a polydispersity in a range of about 1.1 to about 2.

Abstract: A film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a trench formed between adjacent raised surfaces. A first portion of the film is deposited over the substrate from a first gaseous mixture flowed into the process chamber by chemical-vapor deposition. Thereafter, the first portion is etched by flowing an etchant gas having a halogen precursor, a hydrogen precursor, and an oxygen precursor into the process chamber. Thereafter, a second portion of the film is deposited over the substrate from a second gaseous mixture flowed into the processing chamber by chemical-vapor deposition.

Abstract: A method for aligning a reticle is provided. A first patterned layer with a first alignment grid is formed. Sidewall layers are formed over the first patterned layer to perform a first shrink. The first alignment grid after shrink is etched into an etch layer to form an etched first alignment grid. The patterned layer is removed. An optical pattern of a second alignment grid aligned over the etched first alignment grid is measured. The optical pattern is used to determine whether the second alignment grid is aligned over the etched first alignment grid.

Abstract: A mechanical structure is disposed in a chamber, at least a portion of which is defined by the encapsulation structure. A first method provides a channel cap having at least one preform portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. A second method provides a channel cap having at least one portion disposed over or in at least a portion of an anti-stiction channel to seal the anti-stiction channel, at least in part. The at least one portion is fabricated apart from the electromechanical device and thereafter affixed to the electromechanical device. A third method provides a channel cap having at least one portion disposed over or in at least a portion of the anti-stiction channel to seal an anti-stiction channel, at least in part. The at least one portion may comprise a wire ball, a stud, metal foil or a solder preform. A device includes a substrate, an encapsulation structure and a mechanical structure.

Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.

Abstract: A method of processing a substrate that enables the amount removed of an insulating film to be controlled precisely, without damaging an electronic device. An insulating film on a substrate of a solid-state imaging device is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Abstract: A method of etching a substrate in a plasma processing chamber is disclosed. The method includes introducing the substrate having thereon an underlying layer, an anti-reflective layer above the underlying layer, and a photo-resist layer above the anti-reflective layer into the chamber. The method also includes flowing a gas mixture into the chamber, the gas mixture includes a flow of a hydrofluorocarbon gas, a flow of fluorocarbon gas, a flow of a halogen-containing gas other than the hydrofluorocarbon gas, and a flow of oxygen gas. The method further includes striking a plasma from the gas mixture. The method additionally includes etching at least through the anti-reflective layer with the plasma.

Abstract: A method of using a film formation apparatus for a semiconductor process includes processing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is arranged to supply the cleaning gas into the reaction chamber, and set an interior of the reaction chamber at a first temperature and a first pressure. The by-product film mainly contains a high-dielectric-constant material. The cleaning gas contains chlorine without containing fluorine. The first temperature and the first pressure are set to activate chlorine in the cleaning gas.

Abstract: A method for abating effluent from an etching process in one embodiment includes advancing etch gas product into a passageway of a gas connector in direct fluid communication with a first chamber of an interior void of an apparatus, advancing a gas from a gas source into said passageway of said gas connector at the same time said etch gas product is being advanced into said passageway, and advancing humidified gas from a humidified gas source into a second chamber of said interior void.

Abstract: A plasma processing method for processing a sample by applying a high-frequency bias power periodically for each one period (T) which is divided along a time axis into a first sub-period (T1) for which feedback control of a CD gain is executed, a second sub-period (T2) for which feedback control of a select ratio is executed, and a third sub-period (T3) for which feedback control of both the CD gain and the select ratio are executed. The applied power is set at a large value in the first sub-period, and a duty ratio T1/T is controlled in accordance with the CD gain. A plurality of samples are processed with preset process conditions, and feedback control for each processing unit of the samples is executed in accordance with a processing state of each of the samples so that an average applied power over the one period (T) is constant.

Abstract: A substrate processing apparatus comprises a processing chamber for storing a substrate and performing a specified processing on the substrate, a substrate holding jig for holding the substrate in the processing chamber, a placement stand capable of moving the substrate holding jig inside and outside the processing chamber while mounting the substrate holding jig, a substrate holding jig movement mechanism for moving the substrate holding jig to a location different from the placement stand while holding the substrate holding jig, and a substrate holding jig movement suppression mechanism for suppressing vertical and horizontal movement of the substrate holding jig in order to keep the substrate holding jig mounted on the placement unit of the substrate holding jig movement mechanism.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Abstract: This invention is directed to a process for etching a semiconductor device using an etchant composition to form a predetermined etched pattern therein. The semiconductor device typically has a plurality of layers. At least one of the layers comprises a refractory metal, refractory metal alloy or refractory metal silicide. The etchant composition contains a high concentration of chlorine. The source (or TCP) power is decreased over that of conventional methods, and the bias (or RF) power is increased. Using such an etchant composition, along with the adjusted power levels, uniform etching and increased oxide selectivity is achieved.

Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.

Abstract: Provided is a method and a substrate processing apparatus for fabricating a semiconductor device by forming a film at a relatively high rate without etching an N+ substrate. In the method, a silicon substrate is loaded into a processing chamber in a first step. In a second step, at least a first silane-based gas and a first etching gas is supplied to the processing chamber while heating the semiconductor substrate. In a third step, at least a second silane-based gas and a second etching gas is supplied to the processing chamber while heating the semiconductor substrate.

Abstract: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon layers at the same layer level, wherein the method includes the steps of: forming a photoresist film on the polysilicon layer; forming a photoresist pattern film having side surfaces with different inclination angles by patterning the photoresist film; forming the one or more polysilicon layers having side surfaces with different inclination angles by etching the polysilicon film using the photoresist pattern film.

Abstract: The present invention provides systems and methods of forming an epitaxial film on a substrate. After heating in a process chamber, the substrate is exposed to a silicon source and at least one of SiH2(CH3)2, SiH(CH3)3, Si(CH3)4, 1,3-disilabutane, and C2H2, at a temperature of greater than about 250 degrees Celsius and a pressure greater than about 1 Torr so as to form an epitaxial film on at least a portion of the substrate. Then, the substrate is exposed to an etchant so as to etch the epitaxial film and any other films formed during the deposition. The deposition and etching may be repeated until a film of a desired thickness is achieved. Numerous other aspects are disclosed.

Abstract: Methods of filling trenches/gaps defined by circuit elements on an integrated circuit substrate are provided. The methods include forming a first high-density plasma layer on an integrated circuit substrate including at least one trench thereon using a first reaction gas. The first high-density plasma layer is etched using an etch gas including nitrogen fluoride gas (NF3). A second high-density plasma layer is formed on the etched first high-density plasma layer using a second reaction gas including nitrogen fluoride.

Abstract: A method for forming a pattern of a semiconductor device includes: forming a first mask film and a second mask film over an underlying layer; partially etching the first and second mask films using a photoresist mask pattern as an etching mask to form a intermediate mask pattern having a protrusion shape and including first and second mask film layers, over a remaining portion of the first mask film; forming a first spacer at sidewalls of the intermediate mask pattern etching the remaining portion of the first mask film and the first mask film layer of the intermediate mask pattern using the first spacer and the second mask film layer of the intermediate mask pattern as an etching mask to expose the underlying layer and form a mask pattern having first and second mask film layers; forming a second spacer at sidewalls of the mask pattern; and removing the mask pattern to form a symmetrical spacer pattern.

Abstract: A substrate processing method for use in a substrate processing apparatus having a stocker therein which stores a multiplicity of dummy substrates; a reaction chamber for producing semiconductor products; and a transferring unit for transferring into the reaction chamber a process substrate and the dummy substrate stored in the stocker in order to form a film on the process substrate, the method includes transferring one dummy substrate selected among the dummy substrates stored in the stocker to the reaction chamber without being out of the apparatus; and introducing a cleaning gas into the reaction chamber to clean said one dummy substrate within the reaction chamber.

Abstract: A method and apparatus for removing residue, such as etch reside, from a substrate with substantially reduced damage to the substrate in a plasma processing system is described. A plasma ashing process comprising carbon dioxide (CO2) and optionally a passivation gas, such as a hydrocarbon gas, i.e., CxHy, wherein x, y represent integers greater than or equal to unity, is used to remove residue while reducing damage to underlying dielectric layers. Additionally, the process chemistry can further comprise the addition of an inert gas, such as a Noble gas (i.e., He, Ne, Ar, Kr, Xe, Rn).

Abstract: A semiconductor light emitting device can have stable electric characteristics and can emit light with high intensity from a substrate surface. The device can include a transparent substrate and a semiconductor layer on the substrate. The semiconductor layer can include a first conductive type semiconductor layer, a luminescent layer, a second conductive type semiconductor layer, and first and second electrodes disposed to make contact with the first and second conductive type semiconductor layers, respectively. The first conductive type semiconductor layer, the luminescent layer, and the second conductive type semiconductor layer can be laminated in order from the side adjacent the substrate. An end face of the semiconductor layer can include a first terrace provided in an end face of the first conductive type semiconductor layer in parallel with the substrate surface, and an inclined end face region provided nearer to the substrate than the first terrace.

Abstract: When the state of the vacuum processing chamber is switched to an idle state in which an insulating fluid is circulated while a semiconductor wafer W is not placed in the vacuum processing chamber and no plasma is generated in the vacuum processing chamber, nitrogen gas purging (N2 purging) of the inside of the vacuum processing chamber is started, and the pressure in the vacuum processing chamber is controlled to a predetermined level, for example, about 27 Pa (200 mTorr). This makes it possible to prevent a component in the vacuum processing chamber of a plasma processor from being charged to high voltage, so that an insulative material can be protected against breakdown caused by electric discharge or the like.

Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Abstract: In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first chamber (103). The combination of the semiconductor wafer or sample and the sample holder is enclosed within a second chamber (130) inside the first chamber. Gas is evacuated from the second chamber and an etching gas is introduced into the second chamber, but not into the first chamber, to etch the semiconductor wafer or sample.

Abstract: With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a single-sided etching or an asymmetric etching thereon. The present invention provides a method of etching a wafer comprising: performing a single-sided etching or an asymmetric etching on the wafer, wherein the performing the single-sided etching or the asymmetric etching comprises: overlapping two wafers whose one sides face each other; and etching the overlapped two wafers, and a solar cell including the etched wafers.

Abstract: It is an object to provide a high-precision method for forming deep holes of elliptic pattern, which can improve hole directionality on the short diameter side, the hole directionality being possibly deteriorated as a result of excessive polymer deposition in the initial etching stage. The insulating film dry etching method is for treating a work on which a mask of elliptic pattern is formed with a fluorocarbon gas, wherein the etching process is divided into a first and second steps after the etching is started, the first step operating to deposit a polymer at a rate set lower than that in the second step, and controlling step time in accordance with ellipticity (long diameter/short diameter ratio) of the elliptic pattern.

Abstract: A method of etching organic low-k dielectric materials is provided herein. In one embodiment, a method of etching organic low-k dielectric materials includes placing a substrate comprising an exposed organic low-k dielectric material in an etch reactor; supplying a process gas comprising an oxygen-containing gas, a nitrogen-containing gas, and methane (CH4); and forming a plasma from the process gas to etch the organic low-k dielectric material. The organic low-k dielectric material may include polymer-based low-k dielectric materials, photoresists, or organic polymers. The oxygen-containing gas may be oxygen (O2) and the nitrogen-containing gas may be nitrogen (N2).

Abstract: The voltage of a wafer on the pedestal of an RF plasma reactor is instantly determined from the applied bias current and the applied bias voltage sampled during plasma processing of the wafer using a pair constants. Prior to plasma processing of the wafer, a determination is made of first and second constants based upon electrical characteristics of a transmission line through which RF power is coupled to the pedestal. During plasma processing of the wafer, the wafer voltage is determined by performing the steps of sampling an RF input current and an RF input voltage at the impedance match circuit; multiplying the RF input voltage by the first constant to produce a first product; multiplying the RF input current by the second constant to produce a second product; and computing a sum of the first and second products.

Abstract: A fabrication method of a semiconductor device includes steps of performing any one of O2 ashing, organic processing, and dry etching on a surface of a GaN-based semiconductor layer, etching the surface of the GaN-based semiconductor layer in a mixed solution of acid and an oxidizing agent, and forming an electrode on the surface of the GaN-based semiconductor layer.

Abstract: A method for manufacturing a semiconductor device comprises: forming an interlayer insulating film including a storage node contact plug over a semiconductor substrate; forming an etching barrier film, a sacrificial insulating film, and a hard mask film over the storage node contact plug and the interlayer insulating film; forming a first storage node region by removing a portion of the sacrificial insulating film and the hard mask film by an etching process such that a polymer film is formed at a sidewall of the hard mask film and the sacrificial insulating film; and forming a second storage node region by removing the remaining portions of the sacrificial insulating film and the etching barrier film, thereby exposing the storage node contact plug. The method prevents a bowing phenomenon in the etching process for forming a storage node region and thus allows storage nodes having substantially vertical profiles to be formed.

Abstract: A method is disclosed for applying a plasma etch process to facet a masking layer in a semiconductor device by creating sloped surfaces in the masking layer. The masking layer is plasma etched with a plasma that has a high sputter etch component. The plasma etch process removes material from vertical edges of the masking layer to form a sloped surface at each vertical edge of the masking layer. A layer of conductive material is then applied to the masking layer. When the layer of conductive material is subsequently removed by an overetch process the sloped profile of the masking layer facilitates the removal of stringers of conductive material without using an excessively lengthy overetch.

Abstract: The present invention is directed to a method for fabricating a metal line of a semiconductor device. The method comprises the steps of forming an insulation layer, a metal layer and an organic anti-reflection coating in order on a semiconductor substrate on which devices or lower lines are formed, forming a photoresist pattern having an opening of certain width on the organic anti-reflection coating, forming a buffer layer of certain thickness on the photoresist pattern, and selectively removing the metal layer at a lower side of the opening by performing a dry etching process.

Abstract: An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip.

Abstract: A silicon substrate having a first silicon oxide film formed via thermal oxidation and a second silicon oxide film formed via chemical vapor deposition and the like is subjected to preprocessing prior to selective epitaxial growth, wherein both the first and second silicon oxide films are etched with the same etching rate so as to completely remove the first silicon oxide film. Thus, it is possible to precisely control the sizes of contact holes formed in the silicon substrate, thus preventing contact plugs from short-circuiting with silicon epitaxial layers.

Abstract: A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region.