Abstract: Making it possible to execute the detection of the particles floating inside a processing chamber with the use of an optical system including one observing window and one unit (An object of the present invention is, by using an optical system including one observing window and one unit, to make it possible to execute the detection of the particles floating inside a processing chamber.) Also, in order to be able to detect exceedingly feeble particle scattered-lights with a high-accuracy, when performing a desired thin-film forming or thin-film processing treatment toward a to-be-processed target inside the processing chamber, the following method is employed: First, the irradiation with a beam is executed into the processing chamber through the observing window.

Abstract: A plasma etching method includes preparing in a reaction chamber a semiconductor substrate on which a material layer to be etched is provided; and injecting an etching gas into the reaction chamber, the etching gas being ionized through an RF (Radio Frequency) power source to generate a plasma, wherein the RF power source outputs RF power in a pulse output mode. The plasma etching apparatus includes a reaction chamber adapted to contain an etching gas; and an RF power source adapted to output RF power for excitation of the etching gas to generate plasma, wherein the apparatus further include a pulse control circuit adapted to control the RF power source to output RF power in a pulse output mode. With the invention, the plasma for etching can be generated in a pulse output mode, thus improving a precision of an endpoint where the etching can be disabled.

Abstract: A method for fabricating capacitor in a semiconductor device includes forming an sacrificial layer and over a substrate, forming a mask pattern over the sacrificial layer, etching the sacrificial layer in two steps with differentiated top and bottom power levels using the mask pattern as an etch mask to form an opening, and forming a bottom electrode over the opening.

Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition structures for calibrating a plasma process. The selective-redeposition structures receive a controllable and/or measurable amount of redeposited material during the plasma process.

Abstract: In a first step and a thirst step, etching gases are used which contain fluorocarbon gases having C/F atom number ratios higher than that in a second step. A hole is formed to a midpoint in a silicon oxide film in the first step, the hole is formed until a base SiN film begins to be exposed or immediately before it is exposed in the second step, and overetching is performed in the third step. This enables even a hole having a fine diameter and a high aspect ratio to be formed in an excellent shape.

Abstract: A method of fabricating a semiconductor device which prevents a pitting phenomenon from occurring on a gate insulating layer is provided.

Abstract: A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein A can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.

Abstract: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.

Abstract: A method and system for etching a hafnium containing material using a boron tri-chloride (BCl3) based process chemistry is described. A substrate having a hafnium containing layer, such as a layer of hafnium dioxide (HfO2) is subjected a dry etching process comprising BCl3 and an additive gas including: an oxygen-containing gas, such as O2; or a nitrogen-containing gas, such as N2; or a hydrocarbon gas (CxHy), such as CH4; or a combination of two or more thereof.

Abstract: In an operation status determination method for a plasma processing apparatus, a principal component analysis is carried out by using operation status data groups. Processing parameter values in the respective operation status data groups are converted into principal component scores which are plotted in a two-dimensional coordinate system with axes of the selected principal components. A movement vector P from a first recipe operation status data group for reference apparatus to a first recipe operation status data group for target apparatus is calculated. An actually measured normal area A2 is set, and a predicted normal area B2 is set by moving the area A2 along the movement vector P. Then, it is determined whether or not the principal component scores corresponding to the respective processing parameter values when the second recipe is applied to the target apparatus are included in the predicted normal area B2.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

Abstract: A method for etching a dielectric film is provided herein. In accordance with the method, a device (201) is provided which comprises a first chamber (203) equipped with a first gas supply (209) and a second chamber (205) equipped with a second gas supply (215), wherein the second chamber is in communication with the first chamber by way of an acceleration grid (211) having a variable potential. The gas flow into the plasma chamber is oscillated between a first state in which the gas flow into the first chamber has the composition f11 and the gas flow into the second chamber has the composition f21, and a second state in which the gas flow into the first chamber has the composition f12 and the gas flow into the second chamber has the composition f22.

Abstract: The present invention attracts a wafer 6, placed on a susceptor 5, toward the susceptor 5 by the electrostatic attractive power of an electrostatic chuck electrode 7, varies the output voltage of a variable direct current power source 23 for the electrostatic chuck electrode 7 while measuring the temperature of the wafer 6 by a temperature detection sensor 21; and detects the potential of the wafer 6 based on the output voltage of the variable direct current power source 23 at a time when the temperature of the wafer 6 peaks.

Abstract: A method of manufacture includes processing an object in a chamber and subsequently generating an electrical force of attraction to float contaminants off of a region adjacent the processed object before the object is unloaded from the chamber. The object may be processed with the use of plasma. The plasma is produced by introducing a first gas into the chamber and applying a source power to the first gas. The plasma is extinguished after the object is processed with the use of the plasma. Then, a second gas is introduced into the chamber and a source power is applied to the second gas to generate the electrical force of attraction. At this time, the parameters are controlled so that particle contaminants are readily removed without any influence on the object. Also, the same electrode can be used to apply source power to both the first and second gas. Thus, the operation of removing the particle contaminants is relatively simple.

Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.

Abstract: A plasma processing method performs a plasma processing on a substrate mounted on a mounting table installed in an airtight processing chamber, the mounting table having a smaller size than the substrate. The substrate having a surface, on which a resist mark is formed, is mounted on the mounting table and then electrostatically adsorbed on the mounting table by applying a voltage to an electrostatic chuck. The surface of the substrate is etched by using a plasma of an etching gas while the substrate is cooled through a heat transfer between the substrate and the mounting table via a thermally conductive gas supplied between a top surface of the mounting table and a bottom surface of the substrate. The supply of the thermally conductive gas is stopped, and the resist mask on the substrate is ashed by using a plasma of an ashing gas containing O2.

Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A workpiece is processed in a chamber by striking a plasma in the chamber, treating the workpiece by cyclically adjusting the processing parameters between at least a first step having a first set of processing parameters and a second step having a second set of process parameters, wherein the plasma is stabilized during the transition between the first and second steps. These steps may comprise cyclic etch and deposition steps. One possibility for stabilizing the plasma is by matching the impedance of the plasma to the impedance of the power supply which provides energy to the plasma, by means of a matching unit which can be controlled in a variety of ways depending upon the step type or time during the step. Another possibility is to prevent or reduce substantially variation in the pressure in the chamber between the first and second steps.

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract: A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.

Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.

Abstract: A plasma processing method for processing a sample by reducing a pressure within a processing chamber, including mounting the sample on a sample holder disposed in the processing chamber, and processing using a plasma generated in the processing chamber above the sample holder while supplying a gas for heat transfer to a space between a surface of the sample holder having the sample mounted thereon and a rear surface of the sample. The sample holder has a plurality of substantially ring-shaped depressed portions at the surface where the sample is mounted. A pressure in a space between the depressed portions arranged at a central portion of the sample holder with respect to outer circumferential portion and the sample is set to be lower than a pressure in a space between the depressed portions at the outer circumferential portion and the sample.

Abstract: Methods of performing controllable lateral etches into the silicon layer using a plasma-enhanced etch-deposit-etch sequence are disclosed. The first etch step etches into the silicon layer. The deposition step passivates horizontal surfaces, including the bottom of the etched feature. The second etch step increases the lateral undercut, resulting in a low V:L ratio silicon layer etch.

Abstract: An etching method for plasma-etching a low-k film, wherein the plasma etching is conducted under an etching gas atmosphere including a fluorocarbon gas, O2 gas and Ar gas, and under the conditions of a pressure of 60 mTorr (7999.32 mPa) or higher and a high-frequency output (RF power) of 600 W or less.

Abstract: A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A method and reactant gas bypass system for carrying out a plasma enhanced chemical vapor deposition (PECVD) process with improved gas flow stability to avoid unionized reactant precursors and thickness non-uniformities the method including providing a semiconductor process wafer having a process surface within a plasma reactor chamber for carrying out at least one plasma process; supplying at least one reactant gas flow at a selected flow rate to bypass the plasma reactor chamber for a period of time to achieve a pre-determined flow rate stability; and, redirecting the at least one reactant gas flow into the plasma reactor chamber to carry out the at least one plasma process.

Abstract: A method for manufacturing an article having polymeric residue that is to be removed during the manufacture of the article is disclosed. The article is introduced into a controlled environment of a processing tool having one or more processing chambers. Free radicals are generated from one or more reactant gases and introduced into at least one of the one or more processing chambers where they react with the polymeric residue. A cryogenic cleaning medium is supplied into at least one of the one or more processing chambers where the cryogenic cleaning medium removes the polymeric residue present after the free radicals react with the polymeric residue. The reactant gases are selected to facilitate removal of the polymeric residue with the cryogenic cleaning medium. The cryogenic cleaning medium is supplied with a pulsating flow via a nozzle implement that sweeps across the article.

Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Abstract: The present invention presents a method for detecting an endpoint of an etch process for etching a substrate in plasma processing system (1) comprising: etching the substrate; measuring at least one endpoint signal; generating at least one filtered endpoint signal by filtering the at least one endpoint signal, wherein the filtering comprises applying a Savitsky Golay filter (12) to the at least one endpoint signal; and determining (14) an endpoint of the etch process from the at least one filtered endpoint signal.

Abstract: A processing method which, when an organic film layer such as a PR film layer 202 formed on the surface of a wafer W is to be removed from an SiO2 film layer 204 below it by generating plasma of a process gas in a chamber 1 comprises the step of using O2 gas as the process gas to remove the organic film layer at a first pressure, e.g., 20 mTorr, lower than in a conventional case, and the step of using the same O2 gas to remove the organic film layer at a second pressure, e.g., 200 mTorr, higher than the first pressure.

Abstract: A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.

Abstract: A method and system for facilitating etching. Specifically, the method includes incorporating a fluorescent marker in a layer of a grouping of patterned layers. Etching of the group of patterned layers is controlled based upon the fluorescent marker.

Abstract: An etching method etches an organic film by using an inorganic film as a mask at a high etch rate, in a satisfactory etch profile in a satisfactory in-plane uniformity without causing the inorganic film to peel off. An organic film formed on a workpiece is etched by using an inorganic film as a mask with a plasma produced by discharging an etching gas in a processing vessel (1). The etching method uses a mixed gas containing NH3 gas and O2 gas for etching the organic film when the organic film is to be etched in a pattern having an opening ratio of 40% or above. The etching method uses NH3 gas as an etching gas for etching the organic film when the organic film is to be etched in a pattern having an opening ratio below 40%.

Abstract: A component delivery mechanism for distributing a component inside a process chamber is disclosed. The component is used to process a work piece within the process chamber. The component delivery mechanism includes a plurality of component outputs for outputting the component to a desired region of the process chamber. The component delivery mechanism further includes a spatial distribution switch coupled to the plurality of component outputs. The spatial distribution switch is arranged for directing the component to at least one of the plurality of component outputs. The component delivery mechanism also includes a single component source coupled to the spatial distribution switch. The single component source is arranged for supplying the component to the spatial distribution switch.

Abstract: A method to prevent photoresist residues formed in an aperture is provided. The method includes using a halogen-containing plasma treatment before the aperture is filled with a photoresist. Due to the halogen-containing plasma treatment, amine components on the sidewalls of a via or contact hole or trench opening can be efficiently removed. Accordingly, photoresist residues or via poison can be avoided.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line to reduce a height of a finally formed storage node contact plug, thereby increasing a storage node open area and reducing a short circuit between the bit lines.

Abstract: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a first portion of the BARC layer filling in the vias, and supplying a second gas mixture comprising NH3 gas into the reactor to etch a second portion of the BARC layer disposed in the vias.

Abstract: A plasma etching apparatus includes: a chamber capable of reducing pressure; a substrate support provided inside the chamber to place a substrate; a first electrode which is arranged outside and in proximity to the chamber and to which high frequency power is applied to generate plasma of an etching gas in the chamber; and a second electrode comprising a plurality of separated electrodes which are arranged between the chamber and the first electrode and to each of which high frequency power is applied independently.

Abstract: The present invention relates to a method for forming a storage node contact of a semiconductor device. The method includes the steps of: depositing sequentially a conductive layer, a nitride layer and a polysilicon layer on a substrate having an insulating structure and a conductive structure; etching selectively the polysilicon layer, the nitride layer and the conductive layer to form a plurality of conductive patterns with a stack structure of the conductive layer and a dual hard mask including the polysilicon layer and the nitride layer; forming an insulation layer along a profile containing the conductive patterns; and etching the insulation layer by using a line type photoresist pattern as an etch mask to form a contact hole exposing the conductive structure disposed between the neighboring conductive patterns.

Abstract: A method of reducing critical dimension is provided. A dielectric layer is formed on a substrate. Then, a patterned photoresist is formed on the dielectric layer to expose part of the dielectric layer, wherein the patterned photoresist has a first line width. An etching process is performed to remove the exposed dielectric layer by using the patterned photoresist as an etching mask, wherein the final line width of the dielectric layer is smaller than the first line width. The conditions of the etching process include an etching pressure at 80 torr to 400 torr, an etching gas that includes a fluorocarbon compound and oxygen, wherein the ratio of the fluorocarbon compound to the oxygen is large than 0 and less than 10. Consequently, the etching process can be stabilized to form a smooth sidewall for the gate and to provide a uniform critical dimension.

Abstract: The invention aims at solving the problems of throughput deterioration, reproducibility deterioration and plasma discharge instability when performing continuous discharge during multiple steps of plasma etching. According to the present invention, the gas supply unit is operated while determining the timing for switching conditions of a plurality of plasma etching steps, and the gas flow rate and gas pressure are controlled so that the pressure of processing gas supplied from the gas supply unit to the processing chamber does not fall below a predetermined pressure immediately subsequent to switching steps.

Abstract: Systems and method for adjusting an etch rate of an organic bottom antireflective coating (BARC) layer on a wafer. The BARC layer can be exposed to an energy source at varied intensities to determine a relationship between bake temperature and solubility of the BARC after baking, which correlates to a rate at which the BARC can be etched. The BARC can be a cross-linking BARC, which becomes more cross-linked as bake temperature is increased, resulting in decreased etch rate, or can be a cleaving BARC, which is subject to removal of etch-resistant monomers as bake temperature is increased, resulting in increased etch rate. Thus, the invention provides for adjustable BARC etch rates that can be aligned to an etch rate of a photoresist deposited over the BARC to permit concurrent etching of both layers while mitigating structural defects that can occur if etch rates of the respective layers differ.

Abstract: A method for etching metal deposited on a substrate, the method comprising: depositing a metal layer above a substrate; coating at least a portion of the deposited metal layer with a photo-resist; pattering the photo-resist; etching the deposited metal layer with an inert gas plasma at an energy density of less than 0.5 Watt/cm2, the substrate being maintained at a temperature of less than 50° C.; and ashing a resultant crust with an ashing gas, the ashing gas comprising CF4 and O2.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: A wafer stage including an electrostatic chuck and a method for dechucking a wafer using the wafer stage are provided, wherein, the wafer stage includes an electrostatic chuck support, an electrostatic chuck, a lifting means, and a grounding means including a device for connecting the interconnections for grounding the lifting means. According to the method for dechucking a wafer, when a lifting means is in contact with a rear side of the wafer, the lifting means is grounded. Then, an electrostatic chuck is neutralized by supplying power to electrostatic electrodes, and the wafer is neutralized by supplying plasma to the wafer.

Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.