Abstract: A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

Abstract: An etching method comprises a step of forming a via hole structure based on a photoresist film layer (210) for forming a wiring pattern, a silicon oxide film layer (201) which is a hard mask layer formed under the photoresist film, and an organic Low-k film layer (203) formed under the hard mask layer, wherein in the step, the organic film layer and the organic Low-k film layer are etched by using a mixture gas of N2 gas, H2 gas, and a CF gas.

Abstract: The present invention is a plasma processing method including: a step of introducing a substrate into a processing container, a metal or metallic compound film being formed on a surface of the substrate; a step of supplying a noble gas and an H2 gas into the processing container; and a step of generating plasma in the processing container while the noble gas and the H2 gas are supplied, so that a natural oxide film formed on a surface of the metal or metallic compound film is removed by means of the plasma. According to the invention, the noble gas and the H2 gas are supplied into the processing container, the plasma is generated in the processing container, and the plasma acts on the natural oxide film formed on a surface of the metal or metallic compound film. Thus, active hydrogen in the plasma reduces the natural oxide film, and active species of the noble gas etch the natural oxide film. As a result, the natural oxide film can be removed with a satisfactory selective ratio.

Abstract: An etching processing method capable of etching a low dielectric constant layer at a reduced cost by using an etching processing apparatus comprising a vacuum vessel, a sample loading electrode disposed in the vacuum vessel, a gas introduction device for introducing a reaction gas into the vacuum vessel, an antenna for forming plasmas in the vacuum vessel, and a high frequency power supply for supplying a bias power to a sample loaded on the sample loading electrode, wherein the bias power to be supplied to the sample is 3 W/cm2 or less, and the gas introduction device introduces a gas containing chlorine atoms or bromine atoms to apply etching processing to an inorganic insulation material of low dielectric constant loaded on the loading electrode.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: The present invention provides a method for controlling pressure in a vacuum chamber during a time division multiplexed process. A throttle valve is pre-positioned and held for a predetermined period of time. A process gas is introduced into the vacuum chamber during the associated plasma step (deposition or etching) of the silicon wafer. At the end of the predetermined period of time, the process gas continues to flow with the throttle valve being released from the set position. At this point, the throttle valve is regulated through a proportional derivative and integral control for a period that lasts the remaining time of the associated plasma step.

Abstract: A method for plasma treatment etches an SiC layer with an increased etching rate and enhanced selectivities of SiC with respect to SiO2 and an organic layer. An etching gas is converted into plasma to etch SiC. The etching gas may include CHF3; CHF3 and N2, for example, a mixed gas of CHF3, N2 and Ar; or a material having C, H and F and a material having N but without any material having O.

Abstract: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

Abstract: After forming a first insulating film of a silicon nitride film, a silicon nitrided oxide film or a silicon carbide film, a second insulating film of a silicon oxide film is formed on the first insulating film. In a chamber of a high density plasma etching system, the second insulating film is selectively etched by using a first etching gas including a fluorocarbon gas having a cyclic structure as a principal constituent, so as to form an upper hole in the second insulating film. Subsequently, in the same chamber, the first insulating film is selectively etched by using a second etching gas including an oxygen gas as a principal constituent, so as to form a lower hole continuous to the upper hole in the first insulating film.

Abstract: A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the device. In one embodiment, a heightened positive voltage and heightened negative voltage is applied to the semiconductor device while plasma etching is occurring to thereby induce charge to be removed from the semiconductor device.

Abstract: The present invention presents a method and apparatus for reducing charging damage to a substrate is described. In particular, a method of operating a plasma processing system is described that leads to the removal of, or significant reduction of, the accumulated charge on the substrate.

Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

Abstract: Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This is particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along with a surrounding dielectric material to form trenches overlying the via opening.

Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.

Abstract: Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.

Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.

Abstract: A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the copper wiring. A plasma treatment is carried out on a surface of copper exposed at a bottom of the opening without turning plasma discharge off after forming the opening in the same chamber as the formation of the opening.

Abstract: A method of etching a ferroelectric device 100 having a ferroelectric layer 112 between a top and a bottom electrode 114, 108 is disclosed herein. Hardmasks 116, 118 are deposited on the top electrode 114, two or more hardmasks being spaced apart by narrow first regions 115 and spaced apart from other hardmasks by wider second regions 117. The top electrode 114 and ferroelectric layer 112 are then etched to pattern the top electrode 114 thus forming capacitors 102, 104, and the bottom electrode 108 is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode 108, but in the second regions the bottom electrode is severed. To pattern the bottom electrode 108, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

Abstract: Disclosed a method for dry etching a semiconductor wafer by a plasma generated between a power-supplied first electrode and a grounded second electrode. After the bottom surface of the edge of the wafer is in contact with the first electrode, and the top surface of the edge and the side surface of the wafer are etched by ionized plasma species generated by the plasma discharge of reactive ion etching. Then, after the upper surface of the edge of the wafer is in contact with the second electrode, and the bottom surface of the edge and the side surface of the wafer are etched by radicalized plasma species generated by the plasma discharge of plasma etching.

Abstract: Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.

Abstract: A method of forming semiconductor devices on a wafer is provided. An etch layer is formed over a wafer. A photoresist mask is formed over the etch layer. The photoresist mask is removed only around an outer edge of the wafer to expose the etch layer around the outer edge of the wafer. A deposition gas is provided comprising carbon and hydrogen containing species. A plasma is formed from the deposition gas. A polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, wherein the polymer is formed from the plasma from the deposition gas. The etch layer is etched through the photoresist mask, while consuming the photoresist mask and the polymer deposited on the exposed etch layer around the outer edge of the wafer.

Abstract: A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.

Abstract: The present invention is directed to a semiconductor device having a gate electrode includes of a plurality of sidewalls, each having a recess formed therein. The present invention is also directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of dopant material in a layer of polysilicon and etching the layer of polysilicon to define a gate electrode having a plurality of sidewalls, each of which have a recess formed therein.

Abstract: A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid/ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.

Abstract: Abstract of the Disclosure A method for manufacturing a semiconductor device including a conductive path extending from the upper surface of an insulating layer on a semiconductor substrate to a conductive member embedded in the insulating layer. An etching mask, which defines an etched hole for the conductor path, is formed on the insulating layer within a specified permissible error, and that portion of the insulating layer which is not covered by the etching mask is removed by a reactive ion etching unit having a reaction chamber into which a reactive gas of CHF3/CO is introduced at a CHF3/CO flow ratio of about 15/85. After this, the etched hole formed by an etching process is filled with a conductive material for the conductive path.

Abstract: This invention is directed to a process for etching a semiconductor device using an etchant composition to form a predetermined etched pattern therein. The semiconductor device typically has a plurality of layers. At least one of the layers comprises a refractory metal, refractory metal alloy or refractory metal silicide. The etchant composition contains a high concentration of chlorine. The source (or TCP) power is decreased over that of conventional methods, and the bias (or RF) power is increased. Using such an etchant composition, along with the adjusted power levels, uniform etching and increased oxide selectivity is achieved.

Abstract: A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Abstract: A method of dry plasma etching a semiconductor structure (20), having at least one semiconductor material layer (21), on a semiconductor wafer (200), involving a dry plasma reaction gas mixture (30i) being chemically selected for, and having an etch rate corresponding to, each semiconductor material layer (21); dividing the semiconductor structure (20) into a masked portion (23a) and an unmasked portion (23b); and sequentially exposing the unmasked portion (23b) of the semiconductor structure (20) to the dry plasma reaction gas mixture (30i).

Abstract: According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step 102), forming a hard mask layer (step 104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step 106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step 108) and etching through a first insulating layer without first removing a photoresist layer (step 110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.

Abstract: A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous-etchant.

Abstract: We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 ?m in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 ?m, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method and apparatus provided for controlling cumulative wafer effects. The method comprises processing a workpiece, determining a cumulative effect of the processing on the workpiece and comparing the determined cumulative effect to a reference target value. The method further comprises adjusting a downstream process of the workpiece based on comparing the determined cumulative effect to the reference target value.

Abstract: The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

Abstract: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the subject matter include, but are not necessarily limited to, Cl, Br, F, and I. Once the CuX, or CuX and CuX2, are formed the subject invention can then involve passing a reducing gas over the area of Cu for a sufficient time to etch away at least a portion of the CuX, or CuX2, respectively. With respect to a specific embodiment in which CuX and CuX2 are produced when the halide gas is passed over the area of Cu, the reducing gas can be passed until essentially all of the CuX2 is etched and at least a portion of the CuX is etched. Examples of reducing gases which can be utilized with the subject invention include, but are not necessarily limited to, hydrogen gas and hydrogen gas plasma.

Abstract: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

Abstract: A method of depositing a high density plasma silicon oxide layer having improved gapfill capabilities. In one embodiment the method includes flowing a process gas consisting of a silicon-containing source, an oxygen-containing source and helium into a substrate processing chamber and forming a plasma from the process gas. The ratio of the flow rate of the helium with respect to the combined flow rate of the silicon source and oxygen source is between 0.5:1 and 3.0:1 inclusive. In one particular embodiment, the process gas consists of monosilane (SiH4), molecular oxygen (O2) and helium.

Abstract: A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon layer according to the pattern of the hard mask layer using a fluorine-containing etchant gas. The resulting sidewall profile of the etched polysilicon layer is substantially straight, uniform and devoid of a necking or notched configuration.

Abstract: A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.

Abstract: A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

Abstract: The process of the present invention comprises reactive ion etching of AlxFyOz oxide deposits on aluminum-containing bond pads using feed gases, such as, SF6/CF4/Ar or Cl2/BCL3/Ar. whose active plasma etches the AlxFyOz oxide deposits by physical etching and chemical etching for more complete removal of the AlxFyOz oxide deposits.

Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Abstract: The present invention provides a method and apparatus for precleaning a patterned substrate with a plasma comprising a mixture of argon, helium, and hydrogen. Addition of helium to the gas mixture of argon and hydrogen surprisingly increases the etch rate in comparison to argon/hydrogen mixtures. Etch rates are improved for argon concentrations below about 75% by volume. RF power is capacitively and inductively coupled to the plasma to enhance control of the etch properties. Argon, helium, and hydrogen can be provided as separate gases or as mixtures.

Abstract: A method for etching a feature in an etch layer through a photoresist mask over a substrate is provided. A substrate with an etch layer disposed below a photoresist mask is placed in a process chamber. The photoresist mask is conditioned, wherein the conditioning comprises providing a conditioning gas comprising a hydrogen containing gas with a flow rate and at least one of a fluorocarbon and a hydrofluorocarbon with a flow rate to the process chamber; and energizing the conditioning gas to form the conditioning plasma. The conditioning plasma is stepped. An etch plasma is provided to the process chamber, wherein the etch plasma is different than the conditioning plasma. A feature is etched in the etch layer with the etch plasma.

Abstract: A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

Abstract: A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by (1) maintaining various portions of the etch chamber at elevated temperatures, and/ox (2) using an etch chemistry having a fluorohydrocarbon gas containing at least as many hydrogen atoms as fluorine atoms, preferably CH2F2 or CH3F.

Abstract: A method of determining the endpoint of an etch layer in a semiconductor element fabrication, wherein said element is comprised of at least a first material layer, a second material layer on said first material layer, said endpoint determining method comprises the steps of (i) determining the total emission intensity wavelength of the first material layer; (ii) determining the total emission intensity wavelength of the second material layer; (iii) plotting the scalar of the wavelength differential of the upper and lower layers; and (iv) choosing the highest peak of wavelength differential as the best range of endpoint detection wavelength. This method is particularly useful for etching stacks where the first and second material layers have endpoint emission wavelengths that are close to each other. This include nitrogen-rich silicon layer which is overlaid by an antireflective coating (ARC) layer, e.g. silicon nitride, Si3N4 overlaid by bottom antireflective coating (BARC).

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating film on a semiconductor element; forming a polysilicon layer on the interlayer insulating film; implanting dopant atoms into the polysilicon layer; forming a resist layer on the polysilicon layer; forming one or more first openings in the resist layer; etching the polysilicon layer using the resist layer as a first mask, thereby forming one or more second openings in the polysilicon layer; and forming one or more contact holes in the interlayer insulating film using at least the polysilicon layer as a second mask.

Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.