Including Change In Etch Influencing Parameter (e.g., Energizing Power, Etchant Composition, Temperature, Etc.) Patents (Class 438/714)
  • Patent number: 7425512
    Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: September 16, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Kezhakkedath R. Udayakumar, Ted S. Moise, Scott R. Summerfelt, Martin G. Albrecht, William W. Dostalik, Jr., Francis G. Celii
  • Patent number: 7425510
    Abstract: Methods of cleaning a processing chamber of semiconductor device fabrication equipment are highly effective in removing polymers produced as a by-product of a fabrication process from surfaces in a processing chamber. The cleaning process uses a plasma etchant produced from cleaning gas including an O-based gas and at least one gas selected from the group consisting of an F-based gas and a Cl-based gas. The polymer is dissolved in-situ using the plasma etchant. Thus, frequency at which PM (preventative maintenance) of the equipment must be performed is minimized, and the method contributes to maximizing the yield and quality of the semiconductor devices.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Ju Kim
  • Patent number: 7422982
    Abstract: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially inward of the first electrode with a bias that is different than the bias applied to the first electrode. In one embodiment, the first electrode is coated with an inert material and in this way the same polish rate is obtained with a lower potential level applied to the first electrode.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: September 9, 2008
    Assignee: Applied Materials, Inc.
    Inventors: You Wang, Jie Diao, Stan D. Tsai, Lakshmanan Karuppiah
  • Patent number: 7422020
    Abstract: A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Vijayakumar Ramachandrarao, Grant Kloster
  • Patent number: 7419914
    Abstract: A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns in the contact hole; and performing plasma irradiation using an H2O-containing gas prior to a wet process when removing the resist mask.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 2, 2008
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishida
  • Patent number: 7419908
    Abstract: A method of fabricating electronic, optical or magnetic devices requiring an array of large numbers of small feature in which regions defining individual features of the array are foamed by the steps of: (a) depositing a very thin film of a highly soluble solid onto a flat hydrophilic substrate; (b) exposing he film to solvent vapor under controlled conditions so that the film reorganizes into an array of discrete hemispherical islands on the surface; (c) depositing a film of a suitable resist material over the whole surface; (d) removing the hemispherical structures together with their coating of resist leaving a resist layer with an array of holes corresponding to the islands; and (e) subjecting the resulting structure to a suitable etching process so as to form a well at the position of each hole.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: September 2, 2008
    Assignee: Imperial Innovations Limited
    Inventor: Mino Green
  • Publication number: 20080207003
    Abstract: In order to provide a production method of a semiconductor apparatus that can form a film, even in the case of forming a carbon film, on a semiconductor substrate while maintaining an improved optical transparency at a visible band and while maintaining a preferable adhesion property, the semiconductor apparatus production method includes: a first step of generating and controlling plasma by using oxygen and conducting a plasma operation on a surface of a semiconductor substrate set inside a reaction chamber in which a film is formed on the surface of the semiconductor substrate; and a second step of generating and controlling plasma by using hydrogen and conducting a plasma operation on the surface of the semiconductor substrate set inside the reaction chamber, wherein the second step is conducted after the first step and before forming the film on the surface of the semiconductor substrate inside the reaction chamber.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 28, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Toshiyuki HIROTA
  • Patent number: 7413993
    Abstract: The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate, the process comprising the steps of: (a) heating up the substrate with the metal structure in the presence of molecular nitrogen gas (N2); (b) a stabilization step in the presence of pure molecular nitrogen gas (N2); (c) a passivation step employing a plasma containing at least one of the group of water, nitrogen and oxygen; and (d) a stripping step containing oxygen to remove the residue, comprising resist.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: August 19, 2008
    Assignees: Infineon Technologies AG, Nanya Technology Corporation
    Inventors: Ronald Gottzein, Jens Bachmann, Dirk Efferenn, Uwe Kahler, Chung-Hsin Lin, Wen-Bin Lin, Lee Donohue
  • Patent number: 7413673
    Abstract: An apparatus and method for adjusting the voltage applied to a Faraday shield of an inductively coupled plasma etching apparatus is provided. An appropriate voltage is easily and variably applied to a Faraday shield such that sputtering of a plasma can be controlled to prevent and mitigate deposition of non-volatile reaction products that adversely affect an etching process. The appropriate voltage for a particular etching process or step is applied to the Faraday shield by simply adjusting a tuning capacitor. It is not necessary to mechanically reconfigure the etching apparatus to adjust the Faraday shield voltage.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: August 19, 2008
    Assignee: Lam Research Corporation
    Inventors: Shrikant P. Lohokare, Andras Kuthi, Andrew D. Bailey, III
  • Patent number: 7413992
    Abstract: The embodiments provides an improved tungsten silicide etching process with reduced etch rate micro-loading effect. In one embodiment, a method for etching a layer formed on a substrate is provided. The method includes providing a substrate into a plasma processing chamber, the substrate having a metal silicide layer formed thereon and a patterned mask defined over the metal silicide layer. The method also includes supplying an etching gas mixture of a fluorine-containing gas, a chlorine-containing gas, a nitrogen-containing gas, and an oxygen-containing gas to the plasma processing chamber, wherein the ratio of the nitrogen-containing gas to the fluorine-containing gas is between about 5 to about 15.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: August 19, 2008
    Assignee: Lam Research Corporation
    Inventors: Sok Kiow Tan, Shenjian Liu, Harmeet Singh, Sam Do Lee, Linda Fung-Ming Lee
  • Publication number: 20080194114
    Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 14, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Ryoichi Yoshida
  • Publication number: 20080188082
    Abstract: A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Inventors: Kyeong-Koo Chi, Erik A. Edelberg
  • Publication number: 20080188081
    Abstract: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
    Type: Application
    Filed: February 5, 2007
    Publication date: August 7, 2008
    Inventors: Kyeong-Koo Chi, Erik A. Edelberg
  • Patent number: 7407891
    Abstract: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: August 5, 2008
    Assignee: Siltronic AG
    Inventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
  • Publication number: 20080182416
    Abstract: A method is provided for processing a workpiece in a plasma reactor chamber having electrodes including at least a ceiling electrode and a workpiece support electrode. The method includes coupling respective RF power sources of respective VHF frequencies f1 and f2 to either (a) respective ones of the electrodes or (b) a common one of the electrodes, where f1 is sufficiently high to produce a center-high non-uniform plasma ion distribution and f2 is sufficiently low to produce a center-low non-uniform plasma ion distribution. The method further includes adjusting a ratio of an RF parameter at the f1 frequency to the RF parameter at the f2 frequency so as to control plasma ion density distribution, the RF parameter being any one of RF power, RF voltage or RF current.
    Type: Application
    Filed: April 11, 2007
    Publication date: July 31, 2008
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Douglas A. Buchberger, Shahid Rauf, Kallol Bera, Lawrence Wong, Walter R. Merry, Matthew L. Miller, Steven C. Shannon, Andrew Nguyen, James P. Cruse, James Carducci, Troy S. Detrick, Subhash Deshmukh, Jennifer Y. Sun
  • Publication number: 20080182418
    Abstract: A method of processing a workpiece in a plasma reactor chamber includes coupling RF power via an electrode to plasma in the chamber, the RF power being of a variable frequency in a frequency range that includes a fundamental frequency f. The method also includes coupling the electrode to a resonator having a resonant VHF frequency F which is a harmonic of the fundamental frequency f, so as to produce VHF power at the harmonic. The method controls the ratio of power near the fundamental f to power at harmonic F, by controlling the proportion of power from the generator that is up-converted from f to F, so as to control plasma ion density distribution.
    Type: Application
    Filed: April 11, 2007
    Publication date: July 31, 2008
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Douglas A. Buchberger, Shahid Rauf, Kallol Bera, Lawrence Wong, Walter R. Merry, Matthew L. Miller, Steven C. Shannon, Andrew Nguyen, James P. Cruse, James Carducci, Troy S. Detrick, Subhash Deshmukh, Jennifer Y. Sun
  • Publication number: 20080182417
    Abstract: In a plasma reactor chamber a ceiling electrode and a workpiece support electrode, respective RF power sources of respective VHF frequencies f1 and f2 are coupled to either respective ones of the electrodes or to a common one of the electrodes, where f1 is sufficiently high to produce a center-high non-uniform plasma ion distribution and f2 is sufficiently low to produce a center-low non-uniform plasma ion distribution. Respective center ground return paths are provided for RF current passing directly between the ceiling electrode and the workpiece support electrode for the frequencies f1 and f2, and an edge ground return path is provided for each of the frequencies f1 and f2. The impedance of at least one of the ground return paths is adjusted so as to control the uniformity of the plasma ion density distribution.
    Type: Application
    Filed: April 11, 2007
    Publication date: July 31, 2008
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Douglas A. Buchberger, Shahid Rauf, Kallol Bera, Lawrence Wong, Walter R. Merry, Matthew L. Miller, Steven C. Shannon, Andrew Nguyen, James P. Cruse, James Carducci, Troy S. Detrick, Subhash Deshmukh, Jennifer Y. Sun
  • Patent number: 7405162
    Abstract: An etching method forms an opening with a substantially vertical profile extending to a stopper layer by performing an etching with a plasma of an etching gas acting on an object to be processed loaded in an evacuable processing vessel, wherein the object has a mask layer of a predetermined pattern, a silicon layer to be etched formed below the mask layer and the stopper layer formed below the silicon layer. The etching method includes a first etching process for forming an opening with a tapered wall surface in the silicon layer by using a first etching gas including a fluorine-containing gas and O2 but not HBr; and a second etching process for etching the opening by using a second etching gas including a fluorine-containing gas, O2 and HBr.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Koji Maruyama, Yusuke Hirayama, Nozomi Hirai, Takanori Mimura
  • Patent number: 7402527
    Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: July 22, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Yamashita, Takao Yamaguchi, Hideo Niko
  • Patent number: 7399707
    Abstract: A continuous in situ process of deposition, etching, and deposition is provided for forming a film on a substrate using a plasma process. The etch-back may be performed without separate plasma activation of the etchant gas. The sequence of deposition, etching, and deposition permits features with high aspect ratios to be filled, while the continuity of the process results in improved uniformity.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: July 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Padmanabhan Krishnaraj, Pavel Ionov, Canfeng Lai, Michael Santiago Cox, Shamouil Shamouilian
  • Patent number: 7399710
    Abstract: The present invention consists in a method of plasma treatment of a semiconductor substrate in a process chamber connected to a vacuum line via a valve, said treatment including a plurality of cycles comprising at least one etching step during which an etching gas is introduced alternating with at least one passivation step during which a passivation gas is introduction into said chamber, which method includes the following operations: (a) a reference pressure Pref is defined at which it is wished to effect the treatment, (b) the position of the valve is fixed during the first etching step, (c) the pressure in the process chamber is allowed to stabilize during n cycles, (d) the pressure in the process chamber is measured during the etching step during m cycles, with m at least equal to 2, and an average pressure value Pc is calculated from the measurements effected, (e) after n+m cycles, the position of the valve is corrected with a view to obtaining a pressure in the process chamber that approximates the
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: July 15, 2008
    Assignee: Alcatel
    Inventor: Nicolas Launay
  • Patent number: 7399712
    Abstract: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: July 15, 2008
    Assignee: Novellus Systems, Inc.
    Inventor: Wesley P Graff
  • Patent number: 7399711
    Abstract: A method of controlling a recess etch process for a multilayered substrate having a trench therein and a column of material deposited in the trench includes determining a first dimension from a surface of the substrate to a reference point in the substrate by obtaining a measured net reflectance of at least a portion of the substrate including the trench, computing a modeled net reflectance of the portion of the substrate as a weighted incoherent sum of reflectances from n?1 different regions constituting the portion of the substrate, determining a set of parameters that provides a close match between the measured net reflectance and the modeled net reflectance, and extracting the first dimension from the set of parameters; computing an endpoint of the process as a function of the first dimension and a desired recess depth measured from the reference point; and etching down from a surface of the column of material until the endpoint is reached.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: July 15, 2008
    Assignee: Lam Research Corporation
    Inventors: Andrew J. Perry, Vijayakumar C. Venugopal
  • Patent number: 7396769
    Abstract: A method of forming a feature in a low-k (k<3.0) dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A stripping gas comprising CO2 is provided. A plasma is formed from the stripping gas comprising CO2. The plasma from the stripping gas comprising CO2 is used to strip the patterned photoresist mask.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: July 8, 2008
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Peter Cirigliano
  • Patent number: 7396771
    Abstract: A plasma etching apparatus includes a processing chamber in which a specimen is subjected to plasma processing, a specimen holder for holding the specimen, the specimen holder including a temperature controller for controlling temperatures at at least 2 positions of the specimen, at least two gas supply sources for supplying processing gases, at least two gas inlets for introducing the processing gases into the processing chamber, a regulator for independently controlling the compositions or the flow rates of the processing gases introduced from the at least two gas inlets and the temperatures controlled with at least two temperature controllers in the specimen holder, and an electromagnetic wave supply unit for sending an electromagnetic wave into the processing chamber, wherein the compositions or the flow rates of the processing gases introduced from the gas inlets and the temperature controlled with the temperature controllers in the specimen holder are independently controlled.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: July 8, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Go Miya, Seiichiro Kanno, Naoshi Itabashi, Motohiko Yoshigai, Junichi Tanaka, Masahito Mori, Naoyuki Kofuji, Go Saito
  • Patent number: 7390751
    Abstract: A dry etching method includes loading a wafer on a lower electrode having at least two cooling paths. Cooling fluids having different temperatures are supplied to each of the cooling paths of the lower electrode so that the multiple cooling paths are at different temperatures from one another. The wafer is etched during cooling.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Kwon Kim
  • Patent number: 7390753
    Abstract: A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: June 24, 2008
    Assignee: Taiwan Semiconductor Mfg. Co., Ltd.
    Inventors: Li-Te Lin, Yui Wang, Huan-Just Lin, Yuan-Hung Chiu, Hun-Jan Tao
  • Patent number: 7390755
    Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: June 24, 2008
    Assignees: Novellus Systems, Inc., STMicroelectronics S.R.L.
    Inventors: David L. Chen, Yuh-Jia Su, Eddie Ka Ho Chiu, Maria Paola Pozzoli, Senzi Li, Giuseppe Colangelo, Simone Alba, Simona Petroni
  • Publication number: 20080138995
    Abstract: A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and
    Type: Application
    Filed: October 29, 2007
    Publication date: June 12, 2008
    Inventor: Mitsuhiro OMURA
  • Publication number: 20080138994
    Abstract: A starting substrate can be appropriately oxidized, while oxidation of the starting substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a starting substrate to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the starting substrate to form a plasma discharge, and processing the starting substrate by the hydrogen plasma.
    Type: Application
    Filed: March 14, 2006
    Publication date: June 12, 2008
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
  • Publication number: 20080138993
    Abstract: A dry etching apparatus comprises: a vacuum chamber where a processing target is disposed on a bottom wall side of an internal space; a coil for generating plasma that is disposed above and outside the vacuum chamber and has conductors disposed so that a gap is formed in a plane view; a top wall that closes the top of the internal space and has a transparent section at a position corresponding to the gap between conductors of the coil 36 in the plane view; and a camera that is disposed above the coil and can capture at least a part of the processing target in a field of view through the gap and the transparent section. The status of the processing target during plasma processing can be observed in real-time.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 12, 2008
    Inventors: Mitsuru Hiroshima, Sumio Miyake, Mitsuhiro Okune, Shozoh Watanabe, Hiroyuki Suzuki
  • Patent number: 7384876
    Abstract: A plasma processing device comprising a gas injection system is described, wherein the gas injection system comprises a gas injection assembly body, a consumable gas inject plate coupled to the gas injection assembly body, and a pressure sensor coupled to a gas injection plenum formed by the gas injection system body and the consumable gas inject plate. The gas injection system is configured to receive a process gas from at least one mass flow controller and distribute the process gas to the processing region within the plasma processing device, and the pressure sensor is configured to measure a gas injection pressure within the gas injection plenum. A controller, coupled to the pressure sensor, is configured to receive a signal from the pressure sensor and to determine a state of the consumable gas inject plate based upon the signal.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 10, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Eric J. Strang
  • Patent number: 7381344
    Abstract: The invention teaches a multi-step method for shutting down the dry-etch process. The ICP rf power is reduced between each of these consecutive power-down steps of the dry-etch process, the complete power-down sequence consists of six steps. These six steps are executed in sequence and without interruption and form the totality of the dry-etch chamber power-down procedure.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chi Chin, Shy-Jay Lin
  • Patent number: 7381650
    Abstract: The present invention provides a method for controlling pressure in a chamber during a time division multiplexed process. A throttle valve is positioned based on an open-loop pressure control algorithm within at least one step of the time division multiplexed etch process. A pressure response of the step is evaluated and compared to a desired pressure response. The throttle valve is then positioned through a proportional, integral and derivative controller step to step of the time division multiplexed etch process based on the evaluation to the desired pressure response.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: June 3, 2008
    Assignee: Unaxis USA Inc.
    Inventors: David Johnson, Russell Westerman, Mike Teixeira, Shouliang Lai
  • Patent number: 7381651
    Abstract: Processes for monitoring the levels of oxygen and/or nitrogen in a substantially oxygen and nitrogen-free plasma ashing process generally includes monitoring the plasma using optical emission. An effect produced by the low levels of oxygen and/or nitrogen species present on other species generally abundant in the plasma is monitored and correlated to amounts of oxygen and nitrogen present in the plasma. This so-called “effect detection” process monitors perturbations in the spectra specifically associated with species other than nitrogen and/or oxygen due to the presence of trace amounts of oxygen and/or nitrogen species and is used to quantitatively determine the amount of oxygen and/or nitrogen at a sensitivity on the order of 1 part per million and potentially 1 part per billion.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: June 3, 2008
    Assignee: Axcelis Technologies, Inc.
    Inventors: Palanikumaran Sakthivel, Thomas J. Buckley, Alan F. Becknell
  • Patent number: 7378352
    Abstract: After low dielectric constant films are formed on a wiring, hardmasks are formed on the low dielectric constant films. A resistmask is formed on the hardmasks. Via holes are formed in the low dielectric constant films using the resistmask. Ashing the resistmask is performed. During this process, a protection film is formed by sticking a sputtered material generated from the resistmask at least onto side surfaces of the via holes. Thereafter, the via holes are extended to the wiring, and a conductive material is buried into the via holes.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: May 27, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoshihisa Iba
  • Patent number: 7375037
    Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 20, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kazuo Yamazaki, Shinji Kuniyoshi, Kousuke Kusakari, Takenobu Ikeda, Masahiro Tadokoro
  • Patent number: 7375034
    Abstract: Recessing a trench using feed forward data is disclosed. In one embodiment, a method includes providing a region on a wafer including a trench area that includes a trench and a field area that is free of any trench, and a material applied over the region so as to fill the trench in the trench area and form a step between the trench area and the field area; etching to partially etch the trench; determining a target etch duration (tD) for etching to the target depth (DT); and etching the trench to the target depth (DT) for a period approximately equal to the target etch duration (tD). The target etch duration tD may be fed forward for recessing another trench to the target depth DT. The method does not require a send ahead wafer, is fully compatible with conventional automated processes and provides in-situ etch time correction to each wafer.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 7375036
    Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc
    Inventor: Rod C. Langley
  • Patent number: 7375038
    Abstract: Methods for etching chromium and forming a photomask using a carbon hard mask are provided. In one embodiment, a method of a chromium layer includes providing a substrate in a processing chamber, the substrate having a chromium layer partially exposed through a patterned carbon hard mask layer, providing a process gas containing chlorine and carbon monoxide into the etching chamber, and maintaining a plasma of the process gas and etching the chromium layer through the carbon hard mask layer. The method of etching a chromium layer through a patterned carbon hard mask layer is useful for fabricating photomasks.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 20, 2008
    Assignee: Applied Materials, Inc.
    Inventor: Ajay Kumar
  • Patent number: 7371688
    Abstract: A process for the selective removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance from a substrate comprising: providing the substrate having the substance deposited thereupon wherein the substance comprises a transition metal ternary compound, a transition metal quaternary compound, and combinations thereof; reacting the substance with a process gas comprising a fluorine-containing gas and optionally an additive gas to form a volatile product; and removing the volatile product from the substrate to thereby remove the substance from the substrate.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 13, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Bing Ji, Martin Jay Plishka, Dingjun Wu, Peter Richard Badowski, Eugene Joseph Karwacki, Jr.
  • Patent number: 7371690
    Abstract: A condition without using Ar as plasma gas is applied to processing of an organic anti-reflection-coating, which suppresses a spatter effect and decreases the cleavage of C—H and OC—O bonds in a resist. As a result, roughness of the resist after processing the anti-reflection-coating can be suppressed, and pitting and striations after processing a next film to be processed, that is an insulating film, can be prevented. For a rare gas to be used at the time of processing the insulating film, any one of Xe, Kr, a mixed gas of Ar and Xe, and a mixed gas of Ar and Kr is applied in place of Ar, giving rise to reduction in pitting and striations after etching. In addition, a dry etching method with less critical-dimension shift and excellence in both apparatus cost and throughput can be provided by performing resist modification and etching by turns.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 13, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Nobuyuki Negishi, Masaru Izawa, Kenetsu Yokogawa
  • Patent number: 7368315
    Abstract: An X-ray detecting device and a fabricating method thereof that is capable of preventing breakage of a transparent electrode. In the device and method, a contact hole passing through a protective film is formed centering around a contact hole passing through a storage insulating film. Accordingly, step coverage of a transparent electrode provided on the protective film can stabilized to prevent breakage of the transparent electrode.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: May 6, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Kyo Ho Moon
  • Publication number: 20080102644
    Abstract: Methods for removing photoresist from a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, a method for removing a photoresist from a semiconductor substrate comprises the steps of exposing the semiconductor substrate and the photoresist to a first plasma formed from oxygen, forming an oxide layer on exposed regions of the semiconductor substrate, and subjecting the photoresist to a second plasma formed from oxygen and a fluorine-comprising gas, wherein the first plasma is not the second plasma.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: NOVELLUS SYSTEMS, INC.
    Inventors: Haruhiro Harry GOTO, Weijie ZHANG, David CHEUNG
  • Patent number: 7365017
    Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 29, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Bo Yeoun Jo
  • Patent number: 7361605
    Abstract: In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one contact opening is associated with each contact. Stripping of the patterned layer of photoresist and related residues is performed. After stripping, the stop layer is removed from the contacts. In one feature, the stop layer is removed from the contacts by etching the stop layer using a plasma that is generated from a plasma gas input that includes hydrogen and essentially no oxygen. In another feature, the photoresist is stripped after the stop layer is removed. Stripping the patterned layer of photoresist and the related residues is performed, in this case, using a plasma that is formed predominantly including hydrogen without oxygen.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: April 22, 2008
    Assignee: Mattson Technology, Inc.
    Inventors: Stephen E. Savas, Wolfgang Helle
  • Patent number: 7358197
    Abstract: The method for avoiding polysilicon film over etch abnormal includes cleaning a semiconductor substrate. A dielectric layer is formed on the substrate. Subsequently, a first silicon source gas at a first flow rate is next performed injecting into a reaction chamber to form a first polysilicon film over the dielectric layer. Successively, a second silicon source gas at a second flow rate is performed injecting into the reaction chamber to form a second polysilicon film over the first polysilicon film, wherein the second silicon source gas having a different growth rate than the first silicon source gas. A patterned photoresist layer is then formed on the second polysilicon film. After the patterned photoresist layer is formed, a dry etching process by way of using the patterned photoresist layer as a etching mask is performed to etch through in turn the second polysilicon film and the first polysilicon film till exposing to the dielectric layer. Finally, the photoresist layer is removed.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: April 15, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Bruce Han, Jen-Tsung Lin, Kuo-Ping Huang
  • Patent number: 7354778
    Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 8, 2008
    Assignee: Infineon Technologies AG
    Inventors: Percy Heger, Tobias Hoerning, Ralf Otto
  • Patent number: 7354525
    Abstract: For a surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. A mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of a vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to a step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masatoshi Oyama, Yoshiyuki Ohta, Tsuyoshi Yoshida, Hironobu Kawahara
  • Patent number: RE40264
    Abstract: The present invention provides a technique, including a method and apparatus, for etching a substrate in the manufacture of a device. The apparatus includes a chamber and a substrate holder disposed in the chamber. The substrate holder has a selected thermal mass to facilitate changing the temperature of the substrate to be etched during etching processes. That is, the selected thermal mass of the substrate holder allows for a change from a first temperature to a second temperature within a characteristic time period to process a film. The present technique can, for example, provide different processing temperatures during an etching process or the like.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: April 29, 2008
    Inventor: Daniel L. Flamm