Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.

Abstract: A process for defining a chalcogenide material layer using a chlorine based plasma and a mask, wherein the portions of the chalcogenide material layer that are not covered by the mask are etched away. In a phase change memory cell having a stack of a chalcogenide material layer and an AlCu layer, the AlCu layer is etched first using a chlorine based plasma at a higher temperature; then the lateral walls of the AlCu layer are passivated; and then the chalcogenide material layer is etched at a lower temperature.

Abstract: A method and apparatus for providing a positive voltage spike to a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

Abstract: A process for forming a tapered trench in a dielectric material includes the steps of forming a dielectric layer on a semiconductor wafer, and plasma etching the dielectric layer; during the plasma etch, the dielectric layer is chemically and physically etched simultaneously.

Abstract: A method and a furnace are provided for the vapor phase deposition of components onto semiconductor substrates. The main flow direction of the process gases can be varied or reversed by the furnace in the course of the method. This prevents temperature and concentration inhomogeneities of the process gas within the furnace, and permits the components to be uniformly deposited onto the semiconductor substrates.

Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant, a silicon source and a carrier gas. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during etching or smoothing processes. In another embodiment of the invention, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. The silicon-containing surface is exposed to an etching gas that contains an etchant, preferably chlorine, a carrier gas and an optional silicon source.

Abstract: The present invention provides a method for processing a photolithographic substrate within a vacuum chamber. The method comprising the steps of cooling the photolithographic substrate to a target temperature before the photolithographic substrate is processed within the vacuum chamber. At least one processing gas is introduced into the vacuum chamber. After the photolithographic substrate is at the target temperature, a plasma is ignited from the processing gas wherein the photolithographic substrate is processed using the plasma. Upon completion of the processing, the photolithographic substrate is unloaded from the vacuum chamber.

Abstract: A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: A more uniform plasma process is implemented for treating a treatment object using an inductively coupled plasma source which produces an asymmetric plasma density pattern at the treatment surface using a slotted electrostatic shield having uniformly spaced-apart slots. The slotted electrostatic shield is modified in a way which compensates for the asymmetric plasma density pattern to provide a modified plasma density pattern at the treatment surface. A more uniform radial plasma process is described in which an electrostatic shield arrangement is configured to replace a given electrostatic shield in a way which provides for producing a modified radial variation characteristic across the treatment surface. The inductively coupled plasma source defines an axis of symmetry and the electrostatic shield arrangement is configured to include a shape that extends through a range of radii relative to the axis of symmetry.

Abstract: The present invention provides a low-k dielectric etching process with high etching selectivities with respect to adjacent layers of other materials, such as an overlying photoresist mask and an underlying barrier/liner layer. The process comprises the step of exposing a portion of the low-k dielectric layer to a plasma of a process gas that includes a fluorocarbon gas having a relatively low fluorine to carbon ratio, a nitrogen-containing gas, and an inert gas, wherein a volumetric flow ratio of the nitrogen-containing gas to the fluorocarbon gas is greater than about 20:1. The process can be used to over etch the low-k dielectric layer to provide improved selectivity to the photoresist mask and the barrier/liner layer, reduced striations and reduced CD loss as compared with conventional low-k dielectric etching processes.

Abstract: A plasma processing system for and method of utilizing an improved etch chemistry for effectively etching high aspect ratio silicon features. The process chemistry employs precursor gases suitable for producing a fluorine/chlorine etch chemistry as well as precursor gases suitable for forming chemical bonds of sufficient strength to create stable feature side-walls. The improved process chemistries include SO2/SF4/SiCl4, SO2/SF4/Cl2, SO2/SiF4/SiCl4, SO2SIF4/Cl2, O2/F2/Cl2, N2 O/F2/Cl2, and NO2/F2/Cl2-based chemistries.

Abstract: Methods for forming a protective polymeric coating on a silicon or silicon-carbide electrode of a plasma processing chamber are provided. The polymeric coating provides protection to the underlying surface of the electrode with respect to exposure to constituents of plasma and gaseous reactants. The methods can be performed during a process of cleaning the chamber, or during a process for etching a semiconductor substrate in the chamber.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: During microelectronic processing of a substrate, a gap on the substrate surface may be filled with a material by alternating deposition and etch processes while the substrate remains in the same process chamber. Alternating deposition and etch processes allows the gap to be completely filled absent a void.

Abstract: A method for etching a silicon substrate is presented in which fast etching speed and etching structures with smooth and perpendicular wall surfaces are achieved. In the etching step, a constant electric power is applied to the silicon substrate to provide a bias potential. Using a mixture of SF6 gas and fluorocarbon gas, there is a step mainly for the progression of dry etching of the etching ground surface. Similarly, using a mixture gas, there is a step mainly for forming a protective layer on the structure surfaces which are perpendicular with respect to the etching ground surface. These two steps are repeated one after the other. In the step for dry etching, the mixture gas is 5–12 volume of fluorocarbon gas with respect to 100 volume SF6 gas. The mixture gas in the protective film formation step is a mixture of 2–5 volume of SF6 gas with respect to 100 volume fluorocarbon gas.

Abstract: A method of plasma etching a layer of dielectric material having a dielectric constant that is greater than four (4). The method includes exposing the dielectric material layer to a plasma comprising a hydrocarbon gas and a halogen containing gas.

Abstract: A processing gas constituted of CH2F2, O2 and Ar is introduced into a processing chamber 102 of a plasma processing apparatus 100. The flow rate ratio of the constituents of the processing gas is set at CH2F2/O2/Ar=20 sccm/10 sccm/100 sccm. The pressure inside the processing chamber 102 is set at 50 mTorr. 500 W high frequency power with its frequency set at 13.56 MHz is applied to a lower electrode. 108 on which a wafer W is placed. The processing gas is raised to plasma and thus, an SiNx layer 206 formed on a Cu layer 204 is etched. The exposed Cu layer 204 is hardly oxidized and C and F are not injected into it.

Abstract: A method of forming conductive connections for semiconductor devices is provided. An organic low-k dielectric layer is formed over a wafer. A conductive aluminum containing layer is formed over the organic low-k dielectric layer. The wafer is placed in an etch chamber. An etch gas comprising HBr is provided into the etch chamber. A plasma is formed from the etch gas comprising HBr. The plasma from the etch gas comprising HBr is used to selectively etch the conductive aluminum containing layer with respect to the low-k dielectric layer.

Abstract: An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could include CF4 chemistry. The inner edges of the sloped ARC areas reduce the original photo-defined space since the underlying layers are now defined by the sloped edges.

Abstract: A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-stop material of the CMOS structure at a second temperature lower than the first temperature to extend the holes and slits to devices of the CMOS structure.

Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.

Abstract: A plasma processing method utilizing a plasma processing apparatus having a plasma generating unit, a process chamber including an outer cylinder for withstanding a reduced pressure, and an inner cylinder made of non-magnetic material and being replaceable arranged inside the outer cylinder, a process gas supply unit for supplying gas to the process chamber, a specimen table for holding a specimen and a vacuum pumping unit. A temperature of the inner cylinder is monitored, and a desired inner cylinder temperature which is inputted in advance in response to a processing condition of the specimen is compared with the monitored temperature of the inner cylinder. A temperature of the outer cylinder is controlled in response to a result of the comparison so as to control the inner cylinder temperature to a predetermined value.

Abstract: A method of micro-machining a semiconductor substrate to form through slots therein and substrates made by the method. The method includes providing a dry etching chamber having a platen for holding a semiconductor substrate. During an etching cycle of a dry etch process for the semiconductor substrate, a source power is decreased, a chamber pressure is decreased from a first pressure to a second pressure, and a platen power is increased from a first power to a second power. Through slots in the substrate provided by the method can have a reentrant profile for fluid flow therethrough.

Abstract: Methods of forming a semiconductor device are provided by forming a gate pattern that includes a gate electrode on a substrate. Lightly doped impurity diffusion layers are formed in the substrate at both sides of the gate pattern. Spacers are formed on sidewalls of the gate pattern. The spacers having a bottom width. Impurity ions are implanted using the gate pattern and the spacer as a mask to form a heavily doped impurity diffusion layer in the substrate. The spacers are removed. A conformal etch stop layer is formed on the gate pattern and the substrate. The etch stop layer is formed to a thickness of at least the bottom width of the spacers.

Abstract: III-V based compounds are etched to produce smooth sidewalls for electro-optical applications using BCl3 together with chemistries of CH4 and H2 in RIE and/or ICP systems. HI or IBr or some combination of group VII gaseous species (Br, F, I) may be added in accordance with the invention.

Abstract: In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure.

Abstract: Systems and methods are described for controlling critical dimension (CD) variation at the bottom of a tapered contact via on a semiconductor substrate. The invention monitors contact vias on a wafer to detect variations in CD at the top of the via in order to facilitate selective alteration of etching component ratios in an etching process, which permits adjustment of the slope of the tapered contact vias. In this manner, the invention compensates for top CD variations to maintain desired CD at the bottom of tapered vias within a target tolerance on subsequent wafers in a wafer fabrication environment.

Abstract: A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming the polymer, plasma etching is conducted using a gas which is effective to etch polymer from chamber internal surfaces. In one implementation, the gas has a hydrogen component effective to form a gaseous hydrogen halide from halogen liberated from the polymer. In one implementation, the gas comprises a carbon component effective to getter the halogen from the etched polymer. In another implementation, a plasma etching method includes positioning a semiconductor wafer on a wafer receiver within a plasma etch chamber. First plasma etching of material on the semiconductor wafer occurs with a gas comprising carbon and a halogen. A polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10–25 ?m and more particularly 15–18 ?m, or a frequency ranging from 12–30 THz and more particularly 16.5–20 THz.

Abstract: A method for forming a dual damascene feature is provided. Vias are formed in an etch layer. A trench patterned mask is provided over the etch layer. A trench is etched, where the etching the trench comprises a cycle of forming protective sidewalls over the sidewalls of the vias and etching a trench through the trench patterned mask. The mask is then stripped.

Abstract: The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.

Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.

Abstract: Conventionally, there is no method for quantitatively evaluating the three-dimensional shape of an etched pattern in a non-destructive manner and it takes much time and costs to determine etching conditions. With the conventional length measuring method only, it has been impossible to detect an abnormality in the three-dimensional shape and also difficult to control the etching process. According to the present invention, variations in signal amounts of an SEM image are utilized to compute three-dimensional shape data on the pattern associated with the etching process steps, whereby the three-dimensional shape is quantitatively evaluated. Besides, determination of etching process conditions and process control are performed based on the three-dimensional shape data obtained. The present invention makes it is possible to quantitatively evaluate the three-dimensional shape of the etched pattern in a non-destructive manner.

Abstract: A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

Abstract: The invention provides a method of assaying at least one element in a material including silicon. The method includes the steps of decomposing a portion of the material with an etching agent to form a solution containing hexafluorosilicic acid and at least one element to be assayed, heating the solution to a temperature sufficient to transform a substantial portion of the hexafluorosilicic acid into silicon tetrafluoride and to cause at least some of the silicon tetrafluoride to evaporate, such that a solution for assaying is obtained in which the silicon content is reduced while and the elements to be assayed are conserved; and assaying at least one element contained in the solution. The invention is applicable to the field of manufacturing substrates or components for optics, electronics, or optoelectronics, and in particular to the field of quality control.

Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example He—O2) flow rate of from about 12 sccm to about 15.6 sccm.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.

Abstract: A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using etch gases that include at least one organic fluorocarbon gas. At least one etch gas is used that includes one or more nitrogen-comprising gases to deposit a surface polymeric material during the etching for maintaining a masking layer over the silicon oxide layer. The method of the invention achieves a complete and anistropic etching of a contact opening having a high aspect ratio and the desired dimensions.

Abstract: The present invention relates to a method of forming a metal line layer in a semiconductor device comprising step of depositing a metal line layer on a semiconductor structure; forming an insulating film and a photoresist material on the metal line layer in a sequential manner, patterning the metal line layer by using the photoresist material and the insulating film as a mask; removing the photoresist material; and etching the insulating film in an isotropic manner. According to the present invention, since metal polymers and metal residues are perfectly removed during the process of forming the metal line layer, it is possible to remove sources, which induce the bridge phenomena. Therefore, it is possible to remarkably improve reliability of a semiconductor device.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: A manufacturing method of an MR thin-film magnetic head with an MR film and lead conductors overlapping each other, includes a step of depositing a conductor layer on at least the magnetoresistive effect film, a step of forming a cap layer patterned on the deposited conductor layer, and a step of dry-etching the deposited conductor layer through a mask of the patterned cap layer using an Ar gas and an O2 gas, an O2 gas or a N2 gas so as to pattern the deposited conductor film to form the lead conductors.

Abstract: A method of manufacturing a semiconductor device comprising forming an insulating layer above a semiconductor layer, forming a conductive layer including at least tantalum and tantalum nitride, and etching the conductive layer with using a gas including SiCl4 and NF3.

Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

Abstract: In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of corresponding lot is for an etching process after a predetermined RF time of etching apparatus. RF time of the etching apparatus is compared with the predetermined RF time, and it is decided whether the etching process of corresponding lot can be performed in the etching apparatus if the etching process for the corresponding lot should be performed after a lapse of the predetermined RF time.

Abstract: The present invention relates to plasma etching in which O2 gas is added with He gas as a main component. At an early stage of a plasma discharge, Cl2 gas is added and thereafter the supply of the Cl2 gas is stopped. A small amount of Cl2 gas is added in advance before the discharge start and thereafter the discharge is started.