Abstract: In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited material can be a metal nitride, e.g., a transition metal nitride such as titanium metal nitride. As part of the preparation for unloading substrates from the chamber, the substrates may be cooled and the chamber is backfilled with a reducing gas to increase the chamber pressure. It has been found that oxidants can be introduced into the chamber during this time. The introduction of a reducing gas has been found to protect exposed metal-containing films from oxidation during the backfill and/or cooling process. The reducing gas is formed of a reducing agent and a carrier gas, with the reducing agent being a minority component of the reducing gas.

Abstract: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the film deposited during the first etching has been removed to an extent that further exposure to the etchant may remove the liner and expose underlying structures. Accordingly, the etching is stopped upon detection of distinctive reaction products and the next deposition in the deposition/etching/deposition process is begun.

Abstract: A method and apparatus for anisotropically etching a recess in a silicon substrate is disclosed. Generally, a plasma is used for energetic excitation of a reactive etching gas, wherein the reactive etching gas is a constituent of a continuous gas flow. A recess is anisotropically etched in a silicon substrate using the reactive etching gas, during which time the recess id deepened by at least fifty micrometers without interrupting the gas flow of the reactive etching gas.

Abstract: A method of forming an organic light-emitting display (OLED) includes the steps of providing a substrate, forming a black matrix on the substrate, forming a buffer layer on the black matrix, forming an active layer on the buffer layer, simultaneously patterning the black matrix and the buffer layer, and forming a display electrode and a thin film transistor over the buffer layer.

Abstract: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).

Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.

Abstract: An electron-emitting device comprises a pair of electrodes and an electroconductive film arranged between the electrodes and including an electron-emitting region carrying a graphite film. The graphite film shows, in a Raman spectroscopic analysis using a laser light source with a wavelength of 514.5 nm and a spot diameter of 1 ?m, peaks of scattered light, of which 1) a peak (P2) located in the vicinity of 1,580 cm?1 is greater than a peak (P1) located in the vicinity of 1,335 cm?1 or 2) the half-width of a peak (P1) located in the vicinity of 1,335 cm?1 is not greater than 150 cm?1.

Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening and including a nickel chrome film, a gold film, and a nickel film in this order when seen from the layer to be subjected to etching; and performing etching on the layer to be subjected to etching, with the mask layer serving as a mask.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.

Abstract: After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating the wafer with a photoresist layer, and patterning the photoresist layer to expose at least the edge and an upper bevel region of the wafer for etching the material layers remaining after performing the first etch.

Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.

Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.

Abstract: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.

Abstract: A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of the conductive layer, performing plasma treatment with a reducing gas on the surface of the conductive layer, thereby permitting the surface of the conductive layer to be reduced and the hydrogen adsorbed by the heat treatment to be released, and forming an oxidation resistance film that covers the surface of the conductive layer such that the surface of the conductive layer is not exposed to an oxygen-containing atmospheric gas after the plasma treatment.

Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.

Abstract: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal nitride is formed upon reaction between excited nitrogen and the precursor, and formed as a film on the substrate. After film formation of the metal nitride, a metal component of the precursor is formed as a film on the metal nitride on the substrate. In this manner, a barrier metal film with excellent burial properties and a very small thickness is produced at a high speed, with diffusion of metal being suppressed and adhesion to the metal being improved.

Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: An electronic substrate manufacturing method includes: forming a wiring pattern on a substrate; providing a mask with an opening for the substrate on which the wiring pattern has been formed; performing a specified treatment in a part area of the wiring pattern through the opening of the mask. The opening has a size based on an accuracy of an alignment between the substrate and the mask.

Abstract: Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.

Abstract: Methods for etching a metal material layer disposed on a substrate to form features with desired profile and uniform critical dimension (CD) of the features across the substrate. In one embodiment, a method for etching a material layer disposed on a substrate includes providing a substrate having a metal layer disposed on a substrate into an etch reactor, flowing a gas mixture containing at least a halogen containing gas and a passivation gas into the reactor, the passivation gas including a nitrogen containing gas and an unsaturated hydrocarbon gas, wherein the nitrogen gas and the unsaturated hydrocarbon gas and etching the metal layer using a plasma formed from the gas mixture. The CD uniformity could be conveniently, efficiently tuned by the gas ratio, if the concentration of the unsaturated hydrocarbon gas is high enough that the molecular ratio of the unsaturated hydrocarbon gas in the diluent gas times the reactor pressure in milliTorr is greater than 1.25.

Abstract: A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed after said step of patterning the metallic electrode.

Abstract: A method of making a microelectromechanical system (MEMS) device is disclosed. The method includes forming a stationary layer over a substrate. A sacrificial layer is formed over the stationary layer. The sacrificial layer is formed of a first material. A mechanical layer is formed over the sacrificial layer. A hard mask layer is formed over the mechanical layer. The hard mask layer is formed of a second material. The first and second materials are etchable by a single etchant which is substantially selective for etching the first and second materials relative to the mechanical layer. The hard mask layer is patterned after forming the hard mask layer. Subsequently, the mechanical layer is etched through the patterned hard mask layer. The patterned hard mask layer is removed simultaneously with the sacrificial layer after etching the mechanical layer.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension. A cavity is formed in the electrically conductive feature. The cavity has a second lateral dimension being greater than the first lateral dimension. The cavity and the opening are filled with an electrically conductive material.

Abstract: A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

Abstract: This invention is directed to a process for etching a semiconductor device using an etchant composition to form a predetermined etched pattern therein. The semiconductor device typically has a plurality of layers. At least one of the layers comprises a refractory metal, refractory metal alloy or refractory metal silicide. The etchant composition contains a high concentration of chlorine. The source (or TCP) power is decreased over that of conventional methods, and the bias (or RF) power is increased. Using such an etchant composition, along with the adjusted power levels, uniform etching and increased oxide selectivity is achieved.

Abstract: A method for fabricating a semiconductor device with a gate is provided. The method includes: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide layer using the patterned hard mask layer as a mask such that the silicide layer has a cross-sectional etch profile that is negatively sloped; etching the polysilicon layer using the patterned hard mask layer as a mask to form a gate; and performing a light oxidation process to oxidize exposed sidewalls of the polysilicon layer and the silicide layer.

Abstract: Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device according to a method including: (i) forming a metal layer on a semiconductor substrate; (ii) forming a groove on an upper surface of the metal layer by etching the metal layer; (iii) etching the metal layer so as to form a groove-engraved lower metal line that is wider than the groove; (iv) forming an insulator layer covering the semiconductor substrate and the groove-engraved lower metal line; (v) etching the insulator layer so as to form a contact hole exposing the groove; and (vi) forming a contact electrode filling the contact hole and an upper metal line connected thereto, above the insulator layer.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: A fabrication method of a semiconductor device includes steps of performing any one of O2 ashing, organic processing, and dry etching on a surface of a GaN-based semiconductor layer, etching the surface of the GaN-based semiconductor layer in a mixed solution of acid and an oxidizing agent, and forming an electrode on the surface of the GaN-based semiconductor layer.

Abstract: A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three factors have been identified as causes of the defects. The three factors are: (1) phosphorus-doping in the base dielectric, and (2) using for SOG etchback an etch tool that was last used for a bond pad etch process, and (3) residual metal contaminants in the etch chamber used for the SOG etchback. Elimination of any one of these three factors eliminates the defects.

Abstract: The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.

Abstract: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a first layer is formed over a substrate, second layer is formed on the first layer, the first layer and the second layer are etched to form a first pattern, and the second layer in the first pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen using ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) to form a second pattern.

Abstract: An inventive semiconductor device production method is a method for producing a semiconductor device having a metal interconnection by etching a metal film including a lower layer of a first metal material and an upper layer of a second metal material different from the first metal material. In the production method, the upper layer is selectively etched under conditions such that an etching rate for the upper layer is higher than an etching rate for the lower layer. The etching is terminated when the lower layer is exposed. Thereafter, the upper layer is over-etched under conditions such that the etching rate for the upper layer is substantially equal to the etching rate for the lower layer. Then, the lower layer is selectively etched.

Abstract: A magnetic recording medium is provided in which a magnetic recording layer 5 is provided in a predetermined concavo-convex pattern on a substrate 1A, a concave portion in a concavo-convex pattern is filled with a non-magnetic material, and a non-magnetic layer 16 formed of the non-magnetic material positioned at the bottom surface of the concave portion in the non-magnetic materials is formed on a convex portion of the concavo-convex pattern while surface of the convex portion and the concave portion is substantially flattened, and a thickness of the non-magnetic layer 16 is 1 nm or less.

Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

Abstract: A process for etching a thick aluminum contact layer of a semiconductor wafer comprises the formation of a wet etch photoresist mask and the opening of a window in the mask, followed by a wet etch of a first portion of the thickness of the contact layer exposed by the window and the inherent under cutting of the contact layer under the mask window. A dry etch is next carried out, using the same window as a mask, to cut the remaining web of the contact layer under the window. An etch stop layer of Ti or TiN can be formed within the body of the contact layer to define the depth of the initial wet etch into the contact layer.

Abstract: A method for manufacturing a TFT panel of an LCD device includes the steps of wet etching a multilayer metallic structure including a high-melting-point metal film (HMPM) film, Al film and another HMPM film while using side etching technique by using a photoresist mask, hot-water washing the side walls of the Al film after the wet etching, and dry etching for configuring the channel region of a TFT in each pixel, and removing the photoresist mask. The presence of the photoresist mask and the protection film prevents corrosion of Al caused by plasma of the etching gas in the dry etching.

Abstract: A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or less.

Abstract: A method of producing a patterned mirror on a transparent conductive substrate comprises the steps of; coating a layer of conductive material onto a substrate, coating a layer of metal onto the layer of conductive material, coating a layer of photoresist onto the layer of metal, curing the layer of photoresist, exposing a desired pattern of transparent conductors through a first mask onto the layer of photoresist, developing the photoresist and simultaneously etching the layer of the conductive material and the layer of metal, exposing a desired pattern of metal conductors through a second mask onto the remaining layer of photoresist, developing the photoresist and etching the layer of metal.

Abstract: In a vacuum processing chamber, an etching is performed on an object to be processed having at least a mask layer formed in a predetermined pattern and a Ti layer, as a layer to be etched, formed under the mask layer. During the etching, a first plasma processing is carried out to etch the Ti layer by using a plasma of an etching gas containing a fluorine compound at an inner pressure of the chamber of 4 Pa or less. Subsequently, a second plasma processing for dry cleaning is performed by using a plasma of a cleaning gas after the first plasma processing is completed. At this time, a deposit containing a Ti compound produced during the plasma processing is removed.

Abstract: A method of multilevel microfabrication processing is provided. The method includes providing a planar substrate that comprises one or more material layers. A first hardmask layer placed on top of the substrate is patterned into the lithographic pattern desired for the top lithographic layer. Subsequent hardmask layers are patterned until the number of hardmask layers equals the number of lithographic layers desired. The method includes etching into the substrate and stripping the top hardmask layer. Furthermore, the method includes alternating etching into the substrate and stripping the subsequent hardmask layers until the bottom hardmask layer is stripped.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.