Abstract: Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: The invention is concerned with a process for removing residue comprising a polymeric resist and metal oxide from a metal structure on a semiconductor substrate, the process comprising the steps of: (a) heating up the substrate with the metal structure in the presence of molecular nitrogen gas (N2); (b) a stabilization step in the presence of pure molecular nitrogen gas (N2); (c) a passivation step employing a plasma containing at least one of the group of water, nitrogen and oxygen; and (d) a stripping step containing oxygen to remove the residue, comprising resist.

Abstract: A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for blocking ions from diffusing into the epitaxial layer, and a deposition layer formed on the ion barrier layer. Thereby, the deep trench of the super-junction device is formed by performing an etch process on the epitaxial layer via the hard mask structure. The hard mask structure can effectively prevent ions from diffusing into the epitaxial layer, so as to avoid unusual electrical property.

Abstract: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting a process condition, including the flow rate of CH2F2 and the power coupled to the dry plasma etching system, such that a proper balance of active etching radicals and polymer forming radicals are formed within the etching plasma.

Abstract: The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate. The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layer 16 and the conductive layer 14 thereby leaving voids. A layer of dielectric 22 is then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areas 28 of the sacrificial layer. Conductive material 30 is then deposited on the surface of the etched dielectric.

Abstract: A method of manufacturing a semiconductor device, includes: forming a resin layer with a resin containing an aromatic compound on a surface, where an electrode is formed, of a semiconductor substrate, by avoiding at least part of the electrode; removing an oxide film from a surface of the electrode using Ar gas and carbonizing the surface of the resin layer to form a carbonized layer; forming wiring from the electrode to over the carbonized layer; and etching, after forming the wiring, the carbonized layer by O2 plasma using the wiring as a mask so as to remove the carbonized layer partially.

Abstract: After low dielectric constant films are formed on a wiring, hardmasks are formed on the low dielectric constant films. A resistmask is formed on the hardmasks. Via holes are formed in the low dielectric constant films using the resistmask. Ashing the resistmask is performed. During this process, a protection film is formed by sticking a sputtered material generated from the resistmask at least onto side surfaces of the via holes. Thereafter, the via holes are extended to the wiring, and a conductive material is buried into the via holes.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Abstract: A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

Abstract: A method of fabricating a grayscale reticle includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticle; and using the reticle to pattern a microlens array.

Abstract: A method for improving accuracy of determining polish endpoint of chemical mechanical polish (CMP) process is provided. The method is performed before the CMP process. First, a test wafer with a to-be-polished layer and a material layer under the to-be-polished layer is provided. Then, a test beam with a wavelength is provided to irradiate the test wafer. The CMP process is performed to the test wafer to remove the to-be-polished layer until the material layer is exposed while the reflection of the test beam during the polish process is continuously detected. The reflection tendency is detected when the to-be-polished layer is to be completely removed and when the CMP process reaches the interface between the to-be-polished layer and the material layer. If the reflection tendency is gradually weakened, the test beam with the wavelength is chosen for the subsequent polish process.

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: A method of removing the pattern resist that remains on a microchip wafer after etching a patterned layer that is supported by a spacer layer. After the etch, the wafer is cleaned with a develop clean process that removes polymer residues from the pattern resist surface. Next is an ash to remove the hardened pattern resist surface, followed by removal of the pattern resist.

Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum or tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.

Abstract: In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing a regular pattern of contact structures with a period which corresponds to the order of magnitude of twice the edge length of the contact hole, and with the second mask containing a pattern with a structure which surrounds at least the contact hole area, and thus covers it.

Abstract: A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an insulation layer over a substrate; forming a hard mask layer over the insulation layer; forming a photoresist pattern over the hard mask layer; forming a polymer over the photoresist pattern to increase a thickness of the photoresist pattern; patterning the hard mask layer by using the photoresist pattern having the increased thickness; and selectively removing the insulation layer by using the photoresist pattern having the increased thickness and the hard mask layer as an etch mask to form a contact hole.

Abstract: The formation of devices in semiconductor material. In one embodiment, a method of forming a semiconductor device is provided. The method comprises forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and then forming interconnect metal layers.

Abstract: In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.

Abstract: For fabricating a phase change memory cell, a layer of phase change material and a layer of a first electrode material are deposited. In addition, the first electrode material is patterned using an etchant including a low-reactivity halogen element such as bromine or iodine to form a first electrode. By using the low-reactivity halogen element, change to the composition of the phase change material and formation of undercut and deleterious halogen by-product are avoided.

Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.

Abstract: Provided is a method for manufacturing a circuit board including an electrode wiring formed above a surface portion of a substrate, and a plurality of electrothermal converting elements which have a heating resistor film for generating thermal energy formed above the electrode wiring. The method includes: forming an electrode wiring layer for forming the electrode wiring, forming the heating resistor film; and collectively etching the electrode wiring layer and the heating resistor film to thereby form the electrode wiring. With the method according to the present invention, the circuit board can be manufactured with a higher density, higher endurance, and lower power consumption recording head to provide high resolution images.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.

Abstract: Microbolometers with regionally thinned microbridges are produced by depositing a thin film (0.6 ?m) of silicon nitride on a silicon substrate, forming microbridges on the substrate, etching the thin film to define windows in a pixel area, thinning the windows, releasing the silicon nitride, depositing a conductive YBaCuO film on the bridges, depositing a conductive film (Au) on the YBaCuO film, and removing selected areas of the YBaCuO and conductive films.

Abstract: A method of forming patterns in a semiconductor device comprises: forming a conductive film on a substrate; forming an anti-reflective layer on the conductive film; cleaning oxide residues on the anti-reflective layer using a first cleaning solution; cleaning the oxide residues on the anti-reflective layer using a second cleaning solution; forming a photoresist pattern on the anti-reflective layer; and patterning the conductive film using the photoresist pattern.

Abstract: A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g.

Abstract: A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a bit line contact region and a storage node contact region are simultaneously formed, and then a storage node contact hole is formed after a form of bit line to reduce a height of a finally formed storage node contact plug, thereby increasing a storage node open area and reducing a short circuit between the bit lines.

Abstract: A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.

Abstract: A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.

Abstract: A method for manufacturing an electronic device comprising the steps of: dry-etching a Ti-containing metal film formed on a substrate with a gas containing fluorine; and treating the substrate with a chemical solution containing fluorine ions after the dry etching step.

Abstract: A method for etching metal deposited on a substrate, the method comprising: depositing a metal layer above a substrate; coating at least a portion of the deposited metal layer with a photo-resist; pattering the photo-resist; etching the deposited metal layer with an inert gas plasma at an energy density of less than 0.5 Watt/cm2, the substrate being maintained at a temperature of less than 50° C.; and ashing a resultant crust with an ashing gas, the ashing gas comprising CF4 and O2.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: For a semiconductor device having copper wiring, an exemplary method according to an embodiment of the present invention may include forming a first insulation layer on a silicon substrate having a transistor thereon; forming a contact hole by etching the first insulation layer; forming a metal plug so as to fill the contact hole; forming a second insulation layer on the metal plug; forming a trench exposing an upper surface of the metal plug by partially removing the second insulation layer; sputter-etching an interior wall and bottom surface of the trench with a plasma; and forming a copper line layer so as to fill the sputter-etched trench. According to this method, electrical contact between a metal plug and a copper line layer may be maintained or improved prevented by reducing or removing by-products on the metal plug using the sputter-etching process.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.

Abstract: A temporal protection layer is employed to a wafer backside for use of micro-electro-mechanical systems (MEMS). The formation of the temporal protection layer prevents the wafer backside from scratch in process of transferring system for IC manufacturers. With regard to low cost and easy forming and removing, an oxide layer is used as the temporal protection layer. The throughput and yield rate of the wafer production are improved by the use of the temporal protection layer.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: An apparatus and method are described for etching Ni-containing films using gas phase plasma etching. Etching of Ti—Ni alloys is carried out by exposure to plasma comprising hydrogen halide (HX) and carbonyl etching gases. The Ti in the Ti—Ni alloy is etched via an ion-assisted reaction with HX and the Ni is etched by reacting with CO. The method is particularly well suited for anisotropic etching of Ti—Ni metal gates for CMOS applications. Etching of Ni—Fe layers is carried out by exposure to plasma comprising a carbonyl etching gas.

Abstract: A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask pattern as a mask; forming a second mask pattern having a plane shape different from that of the first mask pattern by deforming the first mask pattern; and forming a second pattern of the film to be etched different from the first pattern by using the second mask pattern. By applying the process for forming a pattern, for example, to the formation of a semiconductor layer and source and drain electrodes of a TFT substrate of a liquid crystal display apparatus, the above-stated formation requiring two photoresist process steps in a conventional manufacturing method of a liquid crystal display apparatus can be carried out by only one process step, thereby reducing manufacturing cost thereof.

Abstract: A reticle manufacturing method comprises a step of retreating side surfaces of a lift-off pattern to reduce an area of a wide pattern portion, a step of forming a wide convex pattern and a narrow convex pattern by etching a glass substrate (transparent substrate) while using a second mask pattern as a mask, a step of reducing an area of a first wide mask portion, a step of reducing at least an area of a second wide mask portion smaller than an area of the first wide mask portion, and a step of reducing an area of a wide light shielding portion by etching the wide light shielding portion while using the first wide mask portion as a mask.

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh