Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract: The insulation film etching method according to the present invention prevents the pause of etching an insulation film while ensuring a good anisotropic (vertical) configuration and high selectivity to both the mask and the base film. When the first step plasma etching using CHF3/Ar/N2 mixed gas is ended, Ar gas as a purging gas is fed into a processing vessel from an Ar gas supply source 46 with the plasmas extinguished, whereby residual hydrogen and hydrogen compounds in the processing vessel 10 are whirled by the purging gas to be discharged through an exhaust port 10b and through an exhaust pipe 52. When the purging step is completed, the second step plasma etching is performed with C4F8/Ar/N2 mixed gas.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. A conformal Si-rich oxide layer is formed on the surface of the trench by HDPCVD. A conformal first oxide layer is formed on the Si-rich oxide layer by HDPCVD. A conformal second oxide layer is formed on the first oxide layer by LPCVD. Part of the Si-rich oxide layer, the second oxide layer and the first oxide layer are removed by anisotropic etching to form an oxide spacer composed of a remaining Si-rich oxide layer, a remaining second oxide layer and a remaining first oxide layer. The remaining second oxide layer, part of the remaining first oxide layer and part of the Si-rich oxide layer are removed by BOE. Thus, parts of the remaining first and Si-rich oxide layers are formed on the lower surface of the trench, thereby reducing the trench aspect ratio.

Abstract: A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.

Abstract: On a multilayer film which is formed on a semiconductor substrate, an opening which is opened on a base and an emitter is formed in the multilayer film, and after an SiGe/SiGeC film, which has a composition with a higher content of Si in an upper layer region and a lower layer region, and a higher content of Ge in an intermediate layer region, is formed on an entire surface, anisotropic dry etching is performed for the SiGe/SiGeC film up to a predetermined height of the opening.

Abstract: Method of etching a ferroelectric layer includes etching an upper electrode and partially through a ferroelectric layer. A dielectric material is subsequently deposited upon the upper electrode and the partially etched ferroelectric layer. A second etch step completely etches through the remaining portion of the ferroelectric layer and also etches lower electrodes. A random access memory apparatus is constructed that includes a first conductive layer, a dielectric layer disposed upon the first conductive layer, a second conductive layer disposed upon the dielectric layer, where such layers form a stack having a sidewall. Further, the sidewall has a protective dielectric film disposed thereon and extending from the second layer down to the dielectric layer.

Abstract: The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.

Abstract: A method of forming a narrow diameter opening in an insulator layer, featuring a vertical shape profile, has been developed. Using a photoresist shape as an etch mask a first plasma procedure is used to form an initial opening, with a tapered profile shape, in the insulator layer exposing a portion of the top surface of an underlying stop layer. The first plasma procedure results in formation of a thin polymer layer located at the bottom of the initial opening. A second plasma procedure performed in situ, results in deposition of additional polymer layer, comprised of carbon and fluorine, at the bottom of the initial opening. This is followed by a third plasma procedure, performed in situ in an oxygen plasma, removing polymer and releasing fluorine based radicals which etch portions of insulator layer exposed at the bottom of the initial opening, resulting in a final opening featuring a vertical profile shape.

Abstract: An apparatus and method for etching a feature in a wafer with improved depth control and reproducibility is described. The feature is etched at a first etching rate and then at a second etching rate, which is slower than the first etching rate. An optical end point device is used to determine the etching depth and etching is stopped so that the feature has the desired depth. Two different etching rates provides high throughput with good depth control and reproducibility. The apparatus includes an etching tool in which a chuck holds the wafer to be etched. An optical end point device is positioned to measure the feature etch depth. An electronic controller communicates with the optical end point device and the etching tool to control the tool to reduce the etch rate part way through etching the feature and to stop the etching tool, so that that the feature is etched to the desired depth.

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

Abstract: A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample material using an etchant.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A method of fabricating an X-ray detecting device that is capable of preventing breakage of a transparent electrode. In the method, patterning of first and second insulating films occurs at different etching rates, with an etching ratio of the second insulating material to the first insulating material being greater than 1. Accordingly, undercut of the first and second insulating materials can be prevented. This stabilizes the step coverage of a subsequently formed transparent electrode.

Abstract: A method of forming a MEMS device includes providing a substructure including a base material and at least one conductive layer formed on a first side of the base material, forming a dielectric layer over the at least one conductive layer of the substructure, forming a protective layer over the dielectric layer, defining an electrical contact area for the MEMS device on the protective layer, and forming an opening within the electrical contact area through the protective layer and the dielectric layer to the at least one conductive layer of the substructure.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.

Abstract: In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: The present invention is directed to methods for editing copper features embedded within an organic body by exposing at least a portion of a top surface of the copper feature, forming a mill box there-over and then simultaneously milling both the copper feature and any organic material exposed through the mill box in a single step using an ion beam in combination with a XeF2 gas for a dwell time of at least 10 milliseconds. The invention dramatically increases the efficiency of Focused Ion Beam milling of copper features embedded in organic layers by milling these features in a gas-depleted environment at significantly increased dwell time while avoiding the problems of graphitization, destruction of the organic layer and metal redeposition.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: A method of efficiently fabricating a semiconductor device with less fabrication steps is provided. A second inter-layer insulation film is removed to form an aperture by substantially using a first hard mask film as a mask in accordance with the method of fabricating a semiconductor device having a multi-layer wiring structure using a dual-damascene method. In addition, an etching stopper film is removed, and then a first inter-layer insulation film is removed to form a via hole in the first inter-layer insulation film.

Abstract: The present invention relates to a method of anisotropically etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas that previously was used to enhance oxide etching but not nitride selectivity. The present invention uses the fluorocarbon gas under conditions that enhance selectivity of the etch to nitride with respect to a bulk dielectric material such as doped and undoped silicon dioxide.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of minimizing losses of a gate electrode and a hard mask during a self align contact (SAC) formation process. For this effect, the present invention includes the steps of: forming a plurality of conductive patterns on a substrate; forming hard masks on the conductive patterns; forming an organic based dielectric layer on the substrate including the conductive patterns and the hard mask; forming an oxide based insulation layer on the organic based dielectric layer; selectively etching the insulation layer so as to expose the organic based dielectric layer allocated between the conductive patterns; and selectively etching the exposed organic based dielectric layer to form a contact hole that exposes the surfaces of the substrate between the conductive patterns with an O2 gas as a main etching gas.

Abstract: In one embodiment, the invention includes a method of removing at least a portion of a material from a substrate. The method includes providing a substrate in a reaction chamber, the substrate having a material supported thereover, and first etching the material while the substrate is in the reaction chamber. The method also includes, after the first etching, cleaning a component from at least one sidewall of the reaction chamber while the substrate remains therein; the component comprising a species that is present in the material. The cleaning includes exposing the sidewall and substrate to conditions which substantially selectively remove the component from the sidewall while not removing the material from the substrate, and not etching any other materials supported by the substrate. After the cleaning, the method includes second etching the material while the substrate is in the reaction chamber.

Abstract: Method of avoiding or eliminating deposits in the exhaust area of a vacuum system in which a gas containing depositable constituents in the exhaust area is at least intermittently pumped out of a vacuum chamber that is connected to a vacuum pump via a gas line. A reactive gas that removes deposits from the gas in the vacuum pump and/or units provided downstream therefrom, and/or reduces or eliminates existing deposits in this area is at least intermittently added to the gas directly upstream from or within the vacuum pump. The proposed method is particularly suitable for anisotropic plasma etching of silicon using alternating etching steps and polymerization steps, the vacuum chamber being supplied with a sulfur-containing etching gas during the etching steps and a polymerizing agent-containing gas during the polymerization steps.

Abstract: A method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, forming a second layer over the first layer, patterning the second layer to form a plurality of second layer patterns, patterning the first layer to form a plurality of first layer patterns, performing a tone reversal to form a reversed tone for the second layer patterns, and etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A process for smoothing a rough surface on a substrate, such as a diamond or silicon carbide substrate, said rough surface including protruding peak portions separated by valleys, said smoothing comprising (a) depositing a coating on said rough surface so as to adhere to and to fill at least the valleys of said rough surface, (b) mechanically polishing the thus coated rough surface so as to achieve a smooth coated surface, and (c) dry etching the smooth coated surface, such as by PACE, so as to remove the remaining coating and at least protruding peak portions of the substrate so as to achieve a smooth surface on the substrate, wherein in the mechanical polishing step (b) the coating is removed at a rate of reduction of thickness greater than the rate at which the substrate is subject to reduction of thickness by the mechanical polishing, and in the dry etching step (c) the coating and substrate are removed at substantially the same or a similar rate of reduction of thickness, and, if necessary, steps (a), (b

Abstract: A method for forming a dielectric film in a PDP includes the steps of: reducing the ambient pressure of an insulating film including a dielectric material before the ambient temperature reaches the reaction temperature of the dielectric material; introducing heated gas to increase the ambient pressure up to the atmospheric pressure while maintaining the ambient temperature at the reaction temperature; and lowering the ambient temperature down to the solidifying temperature of the insulating film while maintaining the atmospheric ambient pressure.

Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist patter of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist patter of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.

Abstract: A silicon oxide film having a ununiform thickness is deposited inside each of trenches defined in a silicon substrate by etching within a device isolation region, in such a manner that only corner portions of trench bottoms are exposed. The silicon substrate is selectively etched from the exposed trench corner portions of the silicon substrate lying inside the trenches to thereby increase the volume of each trench.

Abstract: A multi-step etching process for a lead overlay structure such as a thin-film magnetic head structure using secondary ion mass spectroscopy (SIMS) whereby high selectivity of a lead material or other high conductivity metal layer is realized versus that of a metallic mask material and stopping layer. The first step includes patterning the mask layer using IBE or RIE. Advantageously, a photoresist layer is present over a portion of the mask layer and is left in place to be removed in a subsequent step. The second step includes etching the high conductivity metal layer using CAIBE or RIBE with an inert/reactive gas mixture and using SIMS to detect when the stopping layer is reached.

Abstract: In the step of forming a gate electrode in the region having the line width in which the miniaturization has been progressed, the present invention provides a method of fabricating a thin film transistor (TFT) whose patterning margin can be enlarged without requiring carrying out the photolithography multiple times. According to a fabricating method of the present invention, the mask pattern of the first layer and the mask pattern of the second layer can be formed in a self-aligned process and as a mask pattern which is analog and whose size are different from each other by performing the photolithography once. The hut shape gate can be formed in a self-aligned process by setting the line width located on the active layer so as to be Li in the mask pattern of the first layer, and so as to be L′ in the mask pattern of the second layer, and by in turn carrying out the anisotropic etching using the mask pattern of the second layer and the anisotropic etching using the mask pattern of the first layer.

Abstract: The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which supports a stack and an electrical node. The stack comprises an electrically insulative cap over an electrically conductive material. An electrically insulative layer is formed over the stack and over the electrical node. A first etch is utilized to etch through the electrically insulative layer to the electrical node and to the electrically insulative cap. The first etch etches partially into the electrically insulative cap but does not etch entirely through the electrically insulative cap. A second etch is utilized after the first etch to etch entirely through the electrically insulative cap to the electrically conductive material of the stack.

Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.

Abstract: A semiconductor wafer comprises an SOI comprising a device layer on an oxide layer supported on a handle layer. Micro-mirrors are formed in the device layer, and access bores extend through the handle layer and the oxide layer to the micro-mirrors for accommodating optical fibers to the micro-mirrors. The access bores are accurately aligned with the micro-mirrors, and the access bores are accurately formed of circular cross-section. Each access bore comprises a tapered lead-in portion extending to a parallel portion. The diameter of the parallel portion is selected so that the optical fibers are a tight fit therein for securing the optical fibers in alignment with the micro-mirrors. The tapered lead-in portions of the access bores are formed to a first depth by a first dry isotropic etch for accurately forming the taper and the circular cross-section of the tapered lead-in portions.

Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. The present invention sequentially forms a DCS HTO film and a nitride film on the entire structure after a self align source etch process so that so that they can serve as a spacer for compensating for the sidewall of a gate structure damaged upon the self align source etch process. Therefore, the present invention can increase the integrity capability of data by preventing movement of charges and holes between a floating gate electrode and peripheral circuits and can mitigate a stress due to the nitride film in a subsequent process. Further, the present invention can prevent increase of the thickness of the dielectric film between a first polysilicon silicon layer and a second polysilicon layer in a subsequent annealing process and can secure the uniformity of a screen oxide film to make uniform the depth of the junction upon a high concentration ion implantation process.

Abstract: In the method for etching the organic insulating film in which the first RF power is applied to the electrode 12 with the object-to-be-processed having the organic insulating film mounted on and the second RF power is applied to the electrode 14 opposed to the electrode 12, whereby plasma of gas containing NH3 is generated to etch the organic insulating film, the first RF power and the second RF power are controlled so as to make the Vpp value of the voltage applied to the electrode 12 below 500 V. Thus, the organic insulating film can be vertically processed while the bow amplitude and the corner loss amount of the hard mask are decreased.

Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.

Abstract: Disclosed is a method for forming a shallow trench isolation. A pad oxide layer is formed on a semiconductor substrate. First and second stopping layers are sequentially formed on the pad oxide layer. The second stopping layer, the first stopping layer, the pad oxide layer and the semiconductor substrate are etched to form a second stopping layer pattern, a first stopping layer pattern, a pad oxide layer pattern and a trench. A trench inner wall oxide layer is formed at an inner surface portion of the trench. A nitride layer liner is formed on a resulted structure. A field oxide layer is formed in the trench. By selectively removing the second stopping layer pattern, the first stopping layer pattern is exposed. Then, the first stopping layer pattern is removed. Since the chemical mechanical polishing is stopped at the second stopping layer pattern, the first stopping layer pattern is prevented from erosion when the chemical mechanical polishing process is carried out.

Abstract: The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a via hole reaching a metal wiring and a concave groove are simultaneously formed in an interlayer film. When the interlayer film and the material of an organic film embedded in the via hole are etched, the etching rate for the material of the organic film with an etching gas is set to be higher than the etching rate for the interlayer film with an etching gas. Thus, plasma etching does not proceed in a state in which the material of the organic film projects from the bottom of the concave groove formed in the interlayer film, and the production of depositions is prevented.

Abstract: A stringer block is formed on the interface between a HDP silicon oxide layer and a silicon substrate. During an etching process for defining the profile of a floating gate, the stringer block functions to expose a bottom corner stringer. Following that, a polysilicon etching process effectively removes the bottom corner stringer. As a result, a stringerless flash memory cell is formed to prevent leakage currents, resulting from the bottom corner stringer, and improve both the reliability and data retention ability of the device.