Abstract: A ferroelectric capacitor encapsulation method for preventing hydrogen damage to electrodes and ferroelectric material of the capacitor. In general terms, the method for encapsulating a capacitor includes etching a bottom electrode of a capacitor to expose an underlying wafer surface. An undercut is etched between the capacitor and the wafer surface. The undercut is refilled with a barrier layer to reduce the diffusion of hydrogen from the surface of the wafer into the capacitor.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: There is provided a method for forming a vertical gate on a vertical array semiconductor device having support devices. The method includes the step of forming a pedestal of the vertical gate from SiGe. The pedestal is etched in a gate conductor (GC) post etch treatment (PET) that is selective with respect to the support devices. A trench top nitride spacer process is performed to obtain a GC SiN spacer combined with a DT (deep trench) top SiN spacer, wherein the GC SiN spacer and the DT top SiN spacer isolate a bitline contact from the vertical gate with respect to critical dimension and overlay.

Abstract: A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes a first thermoelement and a second thermoelement electrically coupled to the first thermoelement. An array of first tips are in close physical proximity to, but not necessarily in physical contact with, the first thermoelement at a first set of discrete points. An array of second tips are in close physical proximity to, but not necessarily in physical contact with, the second thermoelement at a second set of discrete points. The first and second conical are constructed entirely from metal, thus reducing parasitic resistances.

Abstract: A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. When a trench of a STI structure is formed, a portion of a pad nitride film on an active region is removed . Thus, formation of a moat around an upper corner portion of the trench of the STI structure is prevented. Also, the upper corner portion of the trench is rounded. Therefore, a parasitic effect, degradation in gate oxide integrity, an inverse narrow effect and a sub-threshold hump phenomenon can be prevented. Further, a breakdown phenomenon, a gate bridge phenomenon and difference in the coupling ratio between gate electrodes can be prevented.

Abstract: A trench is formed by performing an anisotropic etching treatment on a silicon substrate with the use of a mask pattern including a pad oxide film, a polysilicon film, and a silicon nitride film formed on the silicon substrate, as a mask. Next, the side surface of the polysilicon film is retreated by etching so that the part of an oxide film formed on the side surface of the polysilicon film may not be hung over the part of an oxide film formed on the side surface of the pad oxide film. Next, an oxide film is formed by performing a thermal oxidation treatment on the inner wall surface of the trench including the exposed side surface of the polysilicon film. This produces a semiconductor device that prevents voids from being formed in a trench isolation structure.

Abstract: A method for manufacturing a semiconductor device having a movable unit includes a step of forming an SOI substrate that includes a semiconductor substrate, an insulating layer, and a semiconductor layer. The method further includes a step of dry etching the semiconductor layer to form a trench and a step of dry etching a sidewall defining the trench at a portion adjacent to a bottom of the trench to form the movable unit. The later dry etching is implemented with a charge building up on a surface of the insulating layer that is exposed during the former dry etching to etch the portion. In addition, the later dry etching is implemented at an etching rate higher than that at which the former dry etching is implemented to reduce the deposition amount of a protection film deposited on a reverse side of the movable unit during the later dry etching.

Abstract: A process for forming a bond pad structure to be used to accommodate a subsequent wire bond, has been developed. The process features defining a bond pad opening in a composite insulator stack, exposing a portion of a top surface of an upper level metal interconnect structure at the bottom of the bond pad opening. The bond pad opening is formed with a top portion of the composite insulator stack laterally pulled back from a bottom portion of the same composite insulator stack. The bond pad structure, comprised of aluminum—copper, is then formed entirely in the bond pad opening, with the top surface of the bond pad structure lower than the top surface of the composite insulator stack, thus resulting in a bond pad structure topography offering reduced risk of damage during subsequent pre-wire bonding procedures.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

Abstract: For fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, any region of a stack of a layer of tunnel dielectric material, a layer of floating gate material, a layer of floating dielectric material, and a layer of control gate material, not under a patterning structure, is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material over the tunnel dielectric structure, to form a floating dielectric structure comprised of the floating dielectric material disposed over the floating gate structure, and to form a control gate structure comprised of the control gate material disposed over the floating dielectric structure.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A system and method are disclosed which constrain a microcomponent that is totally released from a substrate for handling of such totally released microcomponent. A preferred embodiment provides a system and method which constrain a totally released microcomponent to a base (e.g., another microcomponent or a substrate). For example, a preferred embodiment provides constraining members that work to constrain a microcomponent to a substrate as such microcomponent is totally released from such substrate. Accordingly, such constraining members may aid in preserving the microcomponent with its substrate during the release of such microcomponent from its substrate during fabrication. Additionally, a preferred embodiment provides constraining members that are suitable for constraining a totally released microcomponent to a base for post-fabrication handling of the microcomponent.

Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads which have a core and a spacer coating are dispensed as a hexagonally-packed monolayer onto a thermo-adhesive layer, which is on a target layer. The beads are kept in place by a bead confinement wall. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.

Abstract: A method of fabricating a micro-mechanical sensor (101) comprising the steps for forming an insulating layer (6) onto the surface of a first wafer (4) bonding a second wafer (2) to the insulating layer (6), patterning and subsequently etching either the first (4) or second wafer (6) such that channels (18,20) are created in either the first (2) or second (4) wafer terminating adjacent the insulating layer (6) and etching the insulating layer (6) to remove portions of the insulating layer (6) below the etched wafer such that those portions of the etched wafer below a predetermined cross section, suspended portions (22), become substantially freely suspended above the un-etched wafer. This method uses Silicon on Insulator technology. Also disclosed is a micro-mechanical gyroscope structure (101) allowing an anisotropic silicon to be used to fabricate a sensor functioning as if fabricated from isotropic silicon.

Abstract: A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction.

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. According to the present invention, the transistor has an auxiliary electrode to which a voltage is applied apart from a gate electrode and formed at both sides of the gate electrode. In a transistor that is turned on/off depending on a voltage applied to the gate electrode, a region where the gate electrode and the source/drain overlap is maintained to have the same voltage by the auxiliary electrode by always applying a high voltage to the auxiliary electrode upon an on operation of the transistor even when the gate electrode becomes a zero (0) volt upon a refresh operation of a DRAM device. Therefore, the present invention can prevent generation of GIDL current. Further, even though the gate electrode is continuously turned on/off, the auxiliary electrode always maintains the same voltage between the gate electrode and the bit line.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: A surface-micromachined rotatable member formed on a substrate and a method for manufacturing thereof are disclosed. The surface-micromachined rotatable member, which can be a gear or a rotary stage, has a central hub, and an annulus connected to the central hub by an overarching bridge. The hub includes a stationary axle support attached to the substrate and surrounding an axle. The axle is retained within the axle support with an air-gap spacing therebetween of generally 0.3 &mgr;m or less. The rotatable member can be formed by alternately depositing and patterning layers of a semiconductor (e.g. polysilicon or a silicon-germanium alloy) and a sacrificial material and then removing the sacrificial material, at least in part. The present invention has applications for forming micromechanical or microelectromechanical devices requiring lower actuation forces, and providing improved reliability.

Abstract: A vertical cavity surface emitting laser (VCSEL) structure and fabrication method therefor are described in which a subsurface air, gas, or vacuum current confinement method is used to restrict the area of electrical flow in the active region. Using vertical hollow shafts to access a subsurface current confinement layer, a selective lateral etching process is used to form a plurality of subsurface cavities in the current confinement layer, the lateral etching process continuing until the subsurface cavities laterally merge to form a single subsurface circumferential cavity that surrounds a desired current confinement zone. Because the subsurface circumferential cavity is filled with air, gas, or vacuum, the stresses associated with oxidation-based current confinement methods are avoided. Additionally, because the confinement is achieved by subsurface cavity structures, overall mechanical strength of the current-confining region is maintained.

Abstract: A method of creating an undercut sidewall profile within an opening formed in a positive resist layer disposed upon a transparent substrate includes the step of forming a positive resist layer on the upper surface of the substrate, and optically patterning the resist layer by selectively directing light at the resist layer from above the upper surface of the substrate. The lower surface of the substrate is flooded with light to partially expose the lowermost region of the resist layer, and the exposed resist is dissolved to form patterned openings therein. The resulting sidewalls of the patterned resist openings have an enlarged width adjacent the upper surface of the substrate. The sidewalls of the resist layer are then flooded with light from above the substrate, the upper region of the resist layer is cured by an electron beam, and the resist layer is developed a second time to dissolve exposed portions of the resist sidewalls, thereby forming an undercut resist sidewall profile.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: A method of manufacturing a fluidic channel through a substrate includes etching an exposed section on a first surface of the substrate, and coating the etched section of the substrate. The etching and the coating are alternatingly repeated until the fluidic channel is formed.

Abstract: A method for producing a thin film on a carrier substrate. For this purpose, a buried sacrificial layer is initially produced in the interior of a parent body, the buried sacrificial layer separating a layer from a residual body remaining from the parent body. After that, the carrier substrate is attached to the layer and the sacrificial layer is then removed. As a result, the thin film to be produced comes into being on the carrier substrate. The method is suitable for the production of electronic components or thin-film solar cells, the parent body being made up, for example, of monocrystalline silicon in which a sacrificial layer of porous silicon is produced.

Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.

Abstract: A microelectromechanical (MEMS) device and a method of fabricating a MEMS device are provided. The method of fabricating the MEMS device includes the steps of: etching a die release trench in a primary handle layer of a wafer having the handle layer, an etch-stop layer disposed on the primary handle layer, and a device layer disposed on the etch-stop layer; patterning a release trench in the device layer that is aligned with the release trench in the primary handle layer; temporarily attaching an additional handle layer to the primary handle layer; etching the device layer to define a structure in the device layer; removing the etch-stop layer; and removing the additional handle layer to release the die.

Abstract: A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract: An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

Abstract: A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.

Abstract: A method for forming ultra-fine width lines on a substrate avoids occurrence of overetch/underetch defects in the many etching steps, as solder layer or copper film etching steps. With the present method the line shape is able to be achieved close to an ideal shape, so that the quality of the lines is high and the integration of the substrate is also high.

Abstract: A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. In order to eliminate or at least reduce heat and/or charge accumulation that accelerates the DRIE etch rate of certain suspended structures, means are provided to electrically and/or thermally tie the suspended structures to each other and/or the surrounding bulk substrate. As a result, the process window is increased to allow slower-etching structures to be etched to completion without overetching the more rapidly-etched structures.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: A method for forming an etching mask structure on a substrate comprises etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.

Abstract: Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface. in an over-etch step.

Abstract: An electrical isolation method for silicon microelectromechanical systems provides trenches filled with insulation layers that support released silicon structures. The insulation layer that fills the trenches passes through the middle portion of the electrodes, anchors the electrodes to the silicon substrate and supports the electrode. The insulation layers do not attach the electrode to the sidewalls of the substrate, thereby forming an electrode having an “island” shape. Such an electrode is spaced far apart from the adjacent walls of the silicon substrate providing a small parasitic capacitance for the resulting structure. The isolation method is consistent with fabricating a complex structure or a structure with a complicated electrode arrangement. Furthermore, the structure and the electrode are separated from the silicon substrate in a single release step.

Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the a second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.

Abstract: An apparatus and method for gas-phase bromine trifluoride (BrF3) silicon isotropic room temperature etching system for both bulk and surface micromachining. The gas-phase BrF3 can be applied in a pulse mode and in a continuous flow mode. The etching rate in pulse mode is dependent on gas concentration, reaction pressure, pulse duration, pattern opening area and effective surface area.

Abstract: The present invention includes a method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask. The method for making the emitter is practiced by providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask is practiced by forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: A surface-micromachined rotatable member formed on a substrate and a method for manufacturing thereof are disclosed. The surface-micromachined rotatable member, which can be a gear or a rotary stage, has a central hub, and an annulus connected to the central hub by an overarching bridge. The hub includes a stationary axle support attached to the substrate and surrounding an axle. The axle is retained within the axle support with an air-gap spacing therebetween of generally 0.3 &mgr;m or less. The rotatable member can be formed by alternately depositing and patterning layers of a semiconductor (e.g. polysilicon or a silicon-germanium alloy) and a sacrificial material and then removing the sacrificial material, at least in part. The present invention has applications for forming micromechanical or microelectromechanical devices requiring lower actuation forces, and providing improved reliability.

Abstract: A system and method for reducing contamination in a semiconductor device formed on a substrate is disclosed. The method and system include providing a barrier metal layer on the substrate. A first portion of the barrier metal layer is thinner than a second portion of the barrier metal layer. The method and system further include removing the first portion of the barrier metal layer.

Abstract: Provided is a method for producing a silicon element. A substrate configuration is provided that includes a silicon layer having a first face and a thickness corresponding to a specified thickness of the silicon element to be formed. The configuration includes a layer of an electrically-insulating material located below and adjacent to the silicon layer. A substantially vertical trench is etched from the first face in the silicon layer to a depth that exposes the insulating layer. Then the trench in the silicon layer is exposed to a gaseous environment that is reactive with silicon, to substantially lateral etch the silicon layer preferentially at the depth of the insulating layer along a surface of the insulating layer. This lateral etch is continued for a duration that results in release of a silicon element over the insulating layer. Also provided is a process for etching an angled trench in a silicon layer.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

Abstract: An oxide film 26 is formed on a silicon substrate 10. The oxide film 26 is topped with wiring patterns 34. Top and side portions of the wiring patterns 34 are covered with nitride film top walls 36 and nitride film side walls 38. After an interlayer oxide film 40 is deposited, contact holes 42 are formed through self-alignment. Under the nitride film side walls 38, isotropic etching is carried out to retract side edge surfaces 32 of the oxide film 26 from the wall surface. Contacts 44 are then formed inside the contact holes 42 whose bottom diameter is expanded by the isotropic etching above.