Abstract: A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure comprising at least one mechanical layer having a first thermal response characteristic and a first mechanical stress response characteristic, at least one layer of the actuating structure, the at least one layer having a second thermal response characteristic different to the first thermal response characteristic and a second mechanical stress response characteristic different to the first mechanical stress response characteristic, a first compensation layer having a third thermal response characteristic and a third mechanical stress characteristic, and a second compensation layer having a fourth thermal response characteristic and a fourth mechanical stress response characteristic.

Abstract: Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

Abstract: A light emitting diode and a light emitting diode (LED) manufacturing method are disclosed. The LED comprises a substrate; a first n-type GaN layer; a second n-type GaN layer; an active layer; and a p-type GaN layer formed on the substrate in sequence; the second n-type GaN layers has a bottom surface interfacing with the first n-type GaN layer, a rim of the bottom surface has a roughened exposed portion, and Ga—N bonds on the bottom surface has an N-face polarity.

Abstract: A semiconductor die includes at least one first region and at least one second region. The at least one first region is configured to emit light having at least a first wavelength. The at least one second region is configured to emit light having at least a second wavelength, which is different from the first wavelength.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxially depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad.

Abstract: A method for fabricating a MEMS resonator is provided. A stacked main body including a silicon substrate, a plurality of metallic layers and an isolation layer is formed and has a first etching channel extending from the metallic layers into the silicon substrate. The isolation layer is filled in the first etching channel. The stacked main body also has a predetermined suspended portion. Subsequently, a portion of the isolation layer is removed so that a second etching channel is formed and the remained portion of the isolation layer covers an inner sidewall of the first etching channel. Afterwards, employing the isolation layer that covers the inner sidewall of the first etching channel as a mask, an isotropic etching process through the second etching channel is applied to the silicon substrate, thereby forming the MEMS resonator suspending above the silicon substrate.

Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.

Abstract: Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a universally shrinkable support handle onto the epitaxial material, wherein the universally shrinkable support handle contains a shrinkable material, and shrinking the support handle to form tension in the support handle and compression in the epitaxial material during a shrinking process. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature.

Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

Abstract: A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

Abstract: According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Abstract: A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like.

Abstract: To provide a method for manufacturing a thin film transistor and a display device using a small number of masks, a thin film transistor is manufactured in such a manner that a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; then, a resist mask is formed thereover; first etching is performed to form a thin-film stack body; second etching in which the first conductive film is side-etched is performed by dry-etching to form a gate electrode layer; and a source electrode, a drain electrode, and the like are formed. Before the dry etching, it is preferred that at least a side surface of the etched semiconductor film be oxidized.

Abstract: A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and a silicon layer. An epi-silicon layer is formed in the buried insulation layer of the peripheral region and connects a peripheral portion of a channel area of the silicon layer to the silicon substrate. A gate is formed on the silicon layer and junction areas are formed in the silicon layer on both sides of the gate.

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region.

Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved, thereby realizing high-speed operation and low power consumption. A stressor 2 composed of silicon germanium is formed in a portion in an active region that is separated by an insulating film formed on a silicon substrate, a silicon channel layer 1 composed of silicon is formed above the stressor, and a tensile stress layer 10 is formed so as to surround a gate electrode and a sidewall formed on the gate electrode.

Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.

Abstract: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.

Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.

Abstract: Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a unidirectionally induced-shrinkage support handle onto the epitaxial material, and shrinking the support handle tangential to reinforcement fibers therein to form tension in the support handle and compression in the epitaxial material during the shrinking process. The unidirectionally induced-shrinkage support handle contains a shrinkable material and reinforcement fibers extending unidirectional throughout the shrinkable material. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature.

Abstract: A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method comprises consecutively depositing and patterning polysilicon and mask material on a substrate to form a polysilicon layer and a mask layer, reducing a width of the polysilicon layer, depositing and etching insulating material on the substrate to form a spacer on a lateral side of the polysilicon layer, and forming a source/drain region in the substrate at sides of the spacer.

Abstract: Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula SixCyNz. These aminosilanes, in contrast, to some of the precursors employed heretofore, are liquid at room temperature and pressure allowing for convenient handling. In addition, the invention relates to a process for producing such films. The classes of compounds are generally represented by the formulas: and mixtures thereof, wherein R and R1 in the formulas represent aliphatic groups typically having from 2 to about 10 carbon atoms, e.g., alkyl, cycloalkyl with R and R1 in formula A also being combinable into a cyclic group, and R2 representing a single bond, (CH2)n, a ring, or SiH2.

Abstract: A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

Abstract: After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component.

Abstract: In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.

Abstract: A light-emitting device with a protection layer for Zn inter-diffusion and a process to form the device are described. The device of the invention provides an active layer containing aluminum (Al) as a group III element, typically AlGaInAs, and protection layers containing silicon (Si) to prevent the inter-diffusion of zing (Zn) atoms contained in p-type layers surrounding the active layer. One of protection layers is put between the active layer and the p-type cladding layer, while, the other of protection layers is disposed between the active layer and the p-type burying layer.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.

Abstract: A method for forming a fine pattern of a semiconductor device include forming a stack structure including a 1st layer hard mask film to a nth layer hard mask film (n is an integer ranging from 2 or more) over an underlying layer formed over a semiconductor substrate. The nth layer hard mask film, the top layer, is selectively etched to obtain a first hard mask pattern of the nth layer. A second hard mask pattern of the nth layer is formed between the first hard mask patterns of the nth layer. A (n?1)th layer hard mask film is etched using the first and the second hard mask pattern of the nth layer as etching masks. The (c) step to the (d) step repeat to form the first and the second hard mask patterns of the 1st layer over the underlying layer. And, the underlying layer is etched using the first and second hard mask patterns of the 1st layer as etching masks.

Abstract: A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

Abstract: After a first insulating film is formed on a substrate, a wiring groove is formed in the first insulating film, and then a wire is formed inside the wiring groove. Subsequently, a protection film is formed on the first insulating film and on the wire, and then a hard mask film is formed on the protection film. After that, the hard mask film is patterned. Subsequently, the protection film and the first insulating film are partially removed using the patterned hard mask film to form an air gap groove, and then a second insulating film is formed to close an upper portion of the air gap groove for forming an air gap.

Abstract: A process for structuring at least one layer as well as an electrical component with structures from the layer are described. The invention states a process to generate at least one structured layer (10A), wherein a mask structure (20) with a first (20A) and second structure (20B) is generated on a layer (10) which is present on a substrate (5). Through this mask structure (20), the first layer (20A) is transferred onto the layer (10) using isotropic structuring processes, and the second structure (20B) is transferred onto the layer (10) using anisotropic structuring processes. The process as per the invention permits the generation of two structures (20A, 20B) in at least a single layer while using a single mask structure.

Abstract: A method for producing an optoelectronic component is disclosed. The method includes the steps of providing a substrate, applying a semiconductor layer sequence to the substrate, applying at least two current expansion layers to the semiconductor layer sequence, applying and patterning a mask layer, patterning the second current expansion layer by means of an etching process during which sidewalls of the mask layer are undercut, patterning the first current expansion layer by means of an etching process during which the sidewalls of the mask layer are undercut at least to a lesser extent than during the patterning of the second current expansion layer, and removing the mask layer.

Abstract: A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.