Abstract: A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.

Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract: Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad.

Abstract: The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).

Abstract: A method of forming a metal contact and passivation of a semiconductor feature, and devices made using the method. The method comprises the steps of forming a dielectric mask on a semiconductor substrate utilising photolithography processes; etching the semiconductor substrate such that one or more features are formed underneath respective portions of the dielectric mask; depositing a passivation layer on the substrate with the dielectric mask in place above the features; subjecting the substrate to an etchant such that the dielectric mask is etched at a higher rate than the passivation layer, whereby portions of the passivation layer deposited on the dielectric mask are lifted off from the substrate; and depositing a metal layer on the substrate including over the remaining passivation layer and exposed portions of the features.

Abstract: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

Abstract: In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to form a metal line. The photoresist pattern is removed by a predetermined thickness to form a residual photoresist pattern on the metal line. The channel layer is etched by using the metal line to form an undercut under the metal line. The protruding portion of the metal line is removed by using the residual photoresist pattern. The protruding portion relatively protrudes by formation of the undercut. Thus, an aperture ratio is increased, an afterimage is prevented, and the display quality is improved.

Abstract: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

Abstract: The present invention relates to integrated circuits. In particular, but not exclusively, the invention relates to a method and apparatus for connecting elements of integrated circuits with interconnects having one or more voids formed between adjacent interconnects. Embodiments of the invention provide apparatus for connecting elements in an integrated circuit device, comprising: at least one interconnect comprising one or more sidewalls; an interconnect sidewall spacer element arranged to provide structural support to the interconnect and formed on at least one of the interconnect sidewalls; and at least one void adjacent said interconnect and extending from the sidewall spacer element.

Abstract: It is an object of the present invention to enhance a selection ratio in an etching process, and provide a method for manufacturing a semiconductor device that has favorable uniform characteristics with high yield. In a method for manufacturing a semiconductor device according to the present invention, a first layer is formed over a substrate, second layer is formed on the first layer, the first layer and the second layer are etched to form a first pattern, and the second layer in the first pattern is selectively etched with plasma of boron trichloride, chlorine, and oxygen using ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) to form a second pattern.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first hard mask layer over a semiconductor substrate and a second hard mask layer over the first hard mask layer, selectively etching the second hard mask layer and the first hard mask layer by using a line/space mask as an etching mask to form a second hard mask layer pattern and a first hard mask layer pattern, forming an insulating film filling the second hard mask layer pattern and the first hard mask layer pattern, selectively etching the second hard mask layer and its underlying first hard mask layer pattern by using the insulating film as an etching mask to form a fourth hard mask layer pattern overlying a third hard mask layer pattern, removing the insulating film and the fourth hard mask layer pattern, and patterning the semiconductor substrate by using the third hard mask layer pattern as an etching mask, to form a fine pattern.

Abstract: The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer.

Abstract: To suppress stiction of a MEMS resonator during fabrication, conductive structures of the MEMS resonator are electrically coupled via a ground strap during the step of forming isolation trenches around their contact structures. After the isolation trenches have been formed, the ground strap is transformed into a non-conductive material to complete the electrical isolation of the conductive structures. An etch mask formed on top of the ground strap prevents etching of the ground strap during the formation of the trenches. Depending on the etching process, the ground strap may be formed as a bridge that suspends above the isolation trench or as a column that extends down to the bottom of the isolation trench.

Abstract: Methods of forming a fluid channel in a semiconductor substrate may include applying a material layer to at least one surface of the semiconductor substrate. The method may further include manipulating the material layer to form a surface topography corresponding to a channel, the surface topography being configured to control directionality of ion bombardment of said substrate along electromagnetic field lines in a plasma sheath coupled to said surface topography.

Abstract: A method of manufacturing a field emission device (FED), which reduces the number of photomask patterning processes and improves the manufacturing yield of the FED, is provided.

Abstract: A method for fabricating a semiconductor structure includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer. The method further includes forming an opening in the protective layer and the carbon masking layer and processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer. The method further includes enlarging the opening in the carbon masking layer and performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer.

Abstract: In producing an integrated sensor, regions of silicon between compensating electronics and a sensor are electrically isolated, while the sensor is delineating and released. The described process can be performed at the end of a fabrication process after electronics processing (i.e., CMOS processing) and compensating electronics are formed. In an aspect, the sensor and a conductive bridge are simultaneously developed from a silicon-on-insulator (SOI) substrate. In an aspect, the sensor is undercut from a silicon substrate utilizing a lateral etch. A cavity is concurrently defined by the same lateral etch in the silicon layer, forming the conductive bridge connecting the sensor to a logic component. An isolation trench is defined in the silicon layer between the sensor components and the logic component. A polymer masks vertical surfaces from the lateral etch, and an insulator layer and photosensitive film mask horizontal surfaces from the lateral etch.

Abstract: A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Abstract: Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

Abstract: Disclosed are methods of fabricating semiconductor devices. A method may include forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The method may also include forming a mask layer on the third conductive layer, forming a photoresist pattern on the mask layer, and forming at least one middle electrode by patterning the mask layer, the third conductive layer, the second dielectric layer, and the second conductive layer using the photoresist pattern as an etching mask. The method may also include forming a mask pattern by selectively etching a side wall of the patterned mask layer, removing the photoresist pattern, and forming an upper electrode by patterning the third conductive layer using the mask pattern as an etching mask.

Abstract: A method for manufacturing a semiconductor substrate comprises: forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base; forming a first semiconductor layer on the semiconductor base in the SOI structure area; forming a second semiconductor layer having an etching selection ratio smaller than an etching selection ratio of the first semiconductor layer on the first semiconductor layer; removing a part of the second semiconductor layer and a part of the first semiconductor layer in the SOI structure area so as to form a recess exposing the semiconductor base and supporting a support; forming a support forming layer on the semiconductor base so as to bury the recess and cover the second semiconductor layer; etching an area excluding the recess, the element area, and an area covering the element isolation film so as to form the support and an opening face exposing a part of end parts of the first semiconductor layer and the second semiconductor layer, the opening face being

Abstract: The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device with high reliability, at low cost, in which an element forming layer having a thin film transistor and the like provided over a substrate is peeled from the substrate, so that a semiconductor device is manufactured. According to the invention, a metal film is formed over a substrate, a plasma treatment is performed to the metal film in a dinitrogen monoxide atmosphere to form a metal oxide film over the metal film, a first insulating film is formed continuously without being exposed to the air, an element forming layer is formed over the first insulating film, and the element forming layer is peeled from the substrate, so that a semiconductor device is manufactured.

Abstract: A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

Abstract: A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

Abstract: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a cavity under the mask, which mask is left behind as a suspended membrane above the cavity; and performing a subsequent anisotropic etch that etches anisotropically the pattern of the mask in the bottom of the cavity.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method and system for release etching a micro-electrical-mechanical-systems (MEMS) device from a substrate. In one aspect, the invention is a method comprising (a) supporting at least one substrate having a sacrificial oxide and a non-sacrificial material in a process chamber at a pressure and at a temperature; (b) introducing a gas phase mixture comprising a halide-containing species and an alcohol vapor selected from a group consisting of ethanol, 1-propanol, and an aliphatic alcohol having four carbon groups into the process chamber, the gas phase mixture having a volumetric ratio of the halide-containing species to the alcohol vapor of approximately 2 or less; and (c) etching the sacrificial oxide with the gas phase mixture. In another aspect, the invention is a system for carrying out the method.

Abstract: A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.

Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: A method of manufacturing semiconductor substrates. After supporting layers are provided on side walls of grooves formed in a semiconductor substrate, grooves that expose a second semiconductor layer are formed. Etching gas or etching liquid is brought in contact with the first semiconductor layer through the grooves, to form a void portion between the semiconductor substrate 1 and the second semiconductor layer. By thermally oxidizing the semiconductor substrate, the second semiconductor layer and the supporting layers, an oxide film is formed in the void portion between the semiconductor substrate and the second semiconductor layer, an oxide film is formed on side walls of the semiconductor substrate in the grooves, and the supporting layers are changed into oxide films.

Abstract: A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.

Abstract: In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface on top of the film to be patterned and the first film. Then, by removing the first film, an etching mask is obtained from the second film formed on the film to be patterned. The film to be patterned is selectively etched through dry etching using the etching mask. A patterned thin film having a groove is thereby obtained.

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

Abstract: A single crystal silicon etching method includes providing single crystal silicon substrate having at least one trench therein. The substrate is exposed to an anisotropic etchant which undercuts the silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: A MEMS device having a proof mass resiliently mounted above a substrate has projections formed on adjacent surfaces of the mass and substrate. The device is formed by creating a plurality of holes in the upper layer. A substance suitable for removing the intermediate layer without substantially removing the upper layer and substrate is introduced through the holes. A substance removing the upper layer, the substrate, or both, is then introduced through the holes to remove a small amount of the substrate and upper layer. Portions of the intermediate layer between the projections are then removed. The dimple structure fabricated from this process will prevent MEMS device stiction both in its final release and device operation.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.

Abstract: A method for fabricating a semiconductor device includes etching a portion of a substrate to form a recess. A polymer layer fills a lower portion of the recess. Sidewall spacers are formed over the recess above the lower portion of the recess. The polymer layer is removed. The lower portion of the recess is isotropically etching to form a bulb-shaped recess.

Abstract: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the patterned protective layer. An opening within the substrate structure overlies an exposed portion of the substrate structure. The method further includes removing the exposed portion of the patterned protective layer, thereby exposing a portion of the first electrode and forming an undercut region of the substrate structure. The method still further includes depositing a liquid over the first electrode after removing the exposed portion of the patterned protective layer, and solidifying the liquid to form a solid layer.

Abstract: A method of forming a semiconductor device includes forming a first layer over a semiconductor substrate and forming a second layer over the first layer. The second layer includes silicon and has an etch selectivity to the second layer that is greater than approximately 1,000. In one embodiment, the second layer is a porous material, such as porous silicon, porous silicon germanium, porous silicon carbide, and porous silicon carbon alloy. A gate insulator is formed over the second layer and a control electrode is formed over the gate insulator. The first layer is selectively removed with respect to the second layer and the semiconductor substrate.

Abstract: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall size, and greater density of features. In particular, the use of a polymer spacer material allows for the formation of contacts within flash memory cells having decreased dimensions so that higher density flash memory cells may be created without causing shorts between contacts or shorts due to misalignment of the contacts. Additionally, the use of the polymer spacer material extends the use of photolithography technologies that are used to form the patterns into the photoresists.

Abstract: One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pattern, the silicon dioxide is etched to form a plurality of hemispherical microcavities in the silicon dioxide. Openings in the patterned nitride are filled, then another layer is formed over the silicon nitride layer using the silicon nitride as a support over the microcavities. An inventive structure resulting from the method is also described.

Abstract: This invention provides a method of forming at least one thin film device, such as for example a thin film transistor. The method includes providing a substrate and depositing a plurality of thin film device layers upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film layers and 3D template structure are etched and at least one thin film layer is undercut.

Abstract: An exemplary method for making a memory structure having different-sized memory cell layers comprises forming at least two layers of ferromagnetic materials, forming at least one mask layer above the ferromagnetic materials, patterning the at least one mask layer, etching the ferromagnetic materials using the at least one mask layer as a first etch transfer mask, laterally reducing a planar dimension of the at least one mask layer to be narrower than the ferromagnetic materials, and etching a layer of the ferromagnetic materials using the reduced at least one mask layer as a second etch transfer mask, such that the ferromagnetic layer being etched becomes a different lateral size than another ferromagnetic layer of the ferromagnetic materials.

Abstract: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

Abstract: An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.

Abstract: A new method of patterning the polysilicon layer in the manufacture of an integrated circuit device has been achieved. A polysilicon layer is provided overlying a semiconductor substrate. The polysilicon layer may overlie a gate oxide layer and thereby comprise the polysilicon gate for MOS devices. A hard mask layer is provided overlying the polysilicon layer. A resist layer is provided overlying the hard mask layer. The resist layer is patterned to form a resist mask the exposes a part of the hard mask layer. The polysilicon layer is patterned in a plasma dry etching chamber. First, the resist layer is optionally trimmed by etching. Second, the hard mask layer is etched where exposed by the resist mask to form a hard mask that exposes a part of the polysilicon layer. Third, the resist mask is stripped away. Fourth, polymer residue from the resist mask is cleaned away using a chemistry containing CF4 gas. Fifth, the polysilicon layer is etched where exposed by the hard mask.