Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. A multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising poly-silicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material is selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x, (wherein NG=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer.

Abstract: A capacitor has a lower electrode formed on an insulation layer, a dielectric layer formed on the lower electrode, an upper electrode layer formed on the dielectric layer, and a first protection layer pattern formed on the upper electrode layer. The upper electrode layer is etched using the first protection layer pattern to form an upper electrode. A second protection layer is formed enclosing the dielectric layer, the upper electrode and the first protection layer pattern.

Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features.

Abstract: A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

Abstract: The present invention provides a method of forming a titanium silicon nitride barrier layer on a semiconductor wafer, comprising the steps of depositing a titanium nitride layer on the semiconductor wafer; plasma-treating the titanium nitride layer in a N2/H2 plasma; and exposing the plasma-treated titanium nitride layer to a silane ambient, wherein silicon is incorporated into the titanium nitride layer as silicon nitride thereby forming a titanium silicon nitride barrier layer. Additionally, there is provided a method of improving the barrier performance of a titanium nitride layer comprising the step of introducing silicon into the titanium nitride layer such that the silicon is incorporated into the titanium nitride layer as silicon nitride. Also provided is a method of integrating copper into a semiconductor device and a method of improving copper wettability at a copper/titanium nitride interface in a semiconductor device.

Abstract: The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity. Another aspect of the invention includes a substrate having a silicon carbide anti-reflective coating, comprising a dielectric layer deposited on the substrate and a silicon carbide anti-reflective coating having a dielectric constant of less than about 7.0 and preferably about 6.0 or less.

Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate.

Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.

Abstract: There is a method of manufacturing a semiconductor device. In an example embodiment, the method comprises applying a semiconductor substrate that is provided with a conductor at a surface. The conductor has a top surface portion and sidewall portions, of which at least the top surface portion is provided with an etch stop layer comprising silicon carbide. A dielectric layer is applied. A via is etched in the dielectric layer over the conductor and, and stopping on the etch stop layer to create an exposed part of the etch stop layer. Inside the via from at least the top surface portion of the conductor, the exposed part of the etch stop layer is removed. The via is filled with a conductive material.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract: The present invention provides an auxiliary semiconductor device fabrication method that forms wiring 113 by using the wiring groove 108 that is formed in the sacrificial oxide film 104. An interlayer insulating film is formed by removing, by means of etching, the sacrificial oxide film that is used as a mold for the wiring layer formation and then allowing the porous Low-k film to fill the region from which the sacrificial oxide film has been removed.

Abstract: A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Abstract: The present invention relates to a method of anisotropically etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas that previously was used to enhance oxide etching but not nitride selectivity. The present invention uses the fluorocarbon gas under conditions that enhance selectivity of the etch to nitride with respect to a bulk dielectric material such as doped and undoped silicon dioxide.

Abstract: A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.

Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.

Abstract: In a method for forming a dual damascene structure in a semiconductor device, an insulating layer is formed on a semiconductor substrate and a silicon nitride etch stop layer is formed on the insulating layer. Then a photoresist layer is applied on the etch stop layer for a contact hole pattern. Thereafter, the insulating layer is etched according to the contact hole pattern and the rest etch stop layer is pull back etched to expose upper surface of the insulating layer. The insulating layer is etched again according to the modified pattern of the rest etch stop layer and the rest etch stop layer is removed so that a dual damascene structure is completed. Therefore, a dual damascene structure can be made by using a single photoresist process and a single etch stop layer so that a manufacturing process is simplified.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of minimizing losses of a gate electrode and a hard mask during a self align contact (SAC) formation process. For this effect, the present invention includes the steps of: forming a plurality of conductive patterns on a substrate; forming hard masks on the conductive patterns; forming an organic based dielectric layer on the substrate including the conductive patterns and the hard mask; forming an oxide based insulation layer on the organic based dielectric layer; selectively etching the insulation layer so as to expose the organic based dielectric layer allocated between the conductive patterns; and selectively etching the exposed organic based dielectric layer to form a contact hole that exposes the surfaces of the substrate between the conductive patterns with an O2 gas as a main etching gas.

Abstract: A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

Abstract: A self-aligned contact, and a method for fabricating the same, are provided. A conductive element having an overlying hydrogen silsesquioxane (HSQ)-based dielectric cap is formed over a semiconductor substrate. Dielectric sidewall spacers are then formed adjacent to sidewalls of the conductive element and the HSQ-based dielectric cap. A HSQ-based dielectric layer is formed over the resulting structure, and an inter-layer dielectric layer, such as TEOS, is formed over the HSQ-based dielectric layer. The inter-layer dielectric layer is then etched through a mask having an opening located over a sidewall spacer, a portion of the HSQ-based dielectric cap and a portion of the substrate. The etch (which may be a C5F8 based etch) has a high selectivity (e.g., about 20:1) with respect to the HSQ-based dielectric layer, thereby enabling the etch to stop on the HSQ-based dielectric layer. Another etch removes the exposed HSQ-based dielectric layer to expose the substrate.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without degradation of transistor characteristics including forming a buffer oxide layer on a semiconductor substrate; successively conducting ion implantations for well formation and field stop formation in the substrate through the buffer oxide layer; removing the buffer oxide layer; forming and patterning a sacrificial layer to form a trench successively conducting ion implantations for threshold voltage adjustment and punch stop formation on the semiconductor substrate area exposed by the trench; forming a gate oxide layer on the exposed surface of the substrate; forming a polysilicon layer so as to completely fill the trench; polishing the polysilicon layer to form a gate electrode; removing the sacrificial layer; forming an LDD region in the substrate; forming spacers on side walls of the gate electrode; and forming source/drain regions.

Abstract: The present invention relates to a process for selectively plasma etching a structure upon a semiconductor substrate to form designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom. In the application, a multilayer structure is first formed comprising layers of silicon, gate oxide, polysilicon, and tungsten silicide.

Abstract: A method for forming a metal interconnect comprises exposing a dielectric layer to an etch chemistry containing nitrogen-containing compound such as NH3, NF3 or N2O. The nitrogen-containing compound provides selectivity and/or profile control comparable to that provided by N2, while avoiding poisoning of photoresist by embedded N2.

Abstract: A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.

Abstract: A tuning-fork crystal wafer 1A which has legs 11, 12 with grooves 11c, 12c is shaped by etching of a crystal substrate 2. To improve processing precision of the depth of the grooves 11c, 12c, the width of the grooves 11c, 12c, is set in advance, based on the etch stop technique in which the amount of etching depends on the pattern of an etch portion. Consequently, as far as the etch time satisfies a required minimum time, it is possible to obtain the depth as designed.

Abstract: A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: Formed is a lamination structure of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer as an intermediate insulating film between a floating gate and a control gate. A silicon nitride film above the control gate is removed by dry etching. In this event, CH3F gas, CH2F2 gas or a mixed gas thereof and O2 gas are used as an etching gas, a pressure inside a reaction chamber is set in the range of 10.6 to 13.3 Pa (80 to 100 mTorr), and a flow rate of the O2 gas is set five times that of the CH3F gas, CH2F2 gas or mixed gas thereof or more.

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing a bit line pattern from being attacked during a storage node contact hole formation. The method includes the steps of: forming a bit line insulation layer on a substrate structure having a plurality of plugs; forming a group of trenches exposing a group of the plugs by etching the bit line insulation layer; burying each trench by a conductive material to form a bit line electrically connected to the exposed plug; isolating the bit line by performing a chemical mechanical polishing process until the bit line insulation layer is exposed; forming an inter-layer insulation layer on the above structure including the bit line; and etching selectively the inter-layer insulation layer and the bit line insulation layer to form storage node contact holes exposing another group of the plugs.

Abstract: A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

Abstract: A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC and hardmask. Then an isotropic etch to trim the linewidth by 0 to 50 nm per edge is performed simultaneously on the photoresist, ARC and hardmask. This method minimizes the amount of line end shortening to less than three times the dimension trimmed from one line edge. Since a majority of the photoresist layer is retained, the starting photoresist thickness can be reduced by 1000 Angstroms or more to increase process window. The pattern is then etched through the underlying layer to form a gate electrode. The method can also be used to form STI features in a substrate.

Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to an oxygen plasma or similar environment to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in either the second or a third etching chamber of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps.

Abstract: A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A method for fabricating an electronic device includes the steps of: preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer; forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer; etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: In one embodiment a micro device is formed by depositing a sacrificial layer over a metallic electrode, forming a moveable structure over the sacrificial layer, and then etching the sacrificial layer with a noble gas fluoride. Because the metallic electrode is comprised of a metallic material that also serves as an etch stop in the sacrificial layer etch, charge does not appreciably build up in the metallic electrode. This helps stabilize the driving characteristic of the moveable structure. In one embodiment, the moveable structure is a ribbon in a light modulator.

Abstract: A method for manufacturing a semiconductor includes: a first step of forming an etching stop layer on a first semiconductor layer; and a second step of forming a second semiconductor layer made of a group III-V compound semiconductor on the etching stop layer. An etching rate for the etching stop layer by dry etching is less than an etching rate for the second semiconductor layer.

Abstract: A gallium nitride type semiconductor laser device includes: a substrate; and a layered structure formed on the substrate. The layered structure at least includes an active layer of a nitride type semiconductor material which is interposed between a pair of nitride type semiconductor layers each functioning as a cladding layer or a guide layer. A current is injected into a stripe region in the layered structure having a width smaller than a width of the active layer. The width of the stripe region is in a range between about 0.2 &mgr;m and about 1.8 &mgr;m.