Abstract: A method of defining a gate structure for a MOSFET device featuring the employment of dual anti-reflective coating (ARC) layers to enhance gate structure resolution, and featuring a dry procedure for removal of all ARC layers avoiding the use of hot phosphoric acid, has been developed. After formation of a polysilicon layer on an underlying silicon dioxide gate insulator layer, a capping silicon oxide, a dielectric ARC layer, and an overlying organic ARC layer are deposited. A photoresist shape is formed and used as an etch mask to allow a first anisotropic RIE procedure to define the desired gate structure shape in the dual ARC layers and in the capping silicon oxide layer. After removal of the photoresist shape and the overlying organic ARC layer a second anisotropic RIE procedure is used to define a desired polysilicon gate structure, with the second anisotropic RIE procedure also resulting in the removal of the dielectric ARC shape.

Abstract: A method for the production of semiconductor components which includes applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. At least one of the masking layers is HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

Abstract: Methods and apparatuses for forming an oxide film. The method includes depositing an oxide film on a substrate using a process gas mixture that comprises a silicon source gas, an oxygen gas, and a hydrogen gas, and a process temperature between 800° C. and 1300° C. During the deposition of the oxide film, the process gas mixture comprises less than 6% oxygen, silicon gas, and predominantly hydrogen.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A process using integrated sensor technology in which a micromachined sensing element and signal processing circuit are combined on a single semiconductor substrate to form, for example, an infrared sensor. The process is based on modifying a CMOS process to produce an improved layered micromachined member, such as a diaphragm, after the circuit fabrication process is completed. The process generally entails forming a circuit device on a substrate by processing steps that include forming multiple dielectric layers and at least one conductive layer on the substrate. The dielectric layers comprise an oxide layer on a surface of the substrate and at least two dielectric layers that are in tension, with the conductive layer being located between the two dielectric layers. The surface of the substrate is then dry etched to form a cavity and delineate the diaphragm and a frame surrounding the diaphragm.

Abstract: A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching.

Abstract: An etching agent which can etch insulating film with high speeds without damaging the resist pattern, provide realistic throughput when the insulting film etching process in the semiconductor manufacturing process is replaced with the single wafer processing etching treatment method, and prevent roughness on the surface of the semiconductor after etching.

Abstract: A method of forming a silicon dioxide gate insulator layer on the surface of a native oxide free semiconductor substrate, has been developed. After performing wet clean procedures used to remove organic contaminants, as well as inorganic contaminants from a semiconductor substrate, a first native oxide layer formed on the surface of the semiconductor substrate as a result of the wet clean procedures is removed via a hydrofluoric acid solution. The hydrofluoric acid procedure results in fluoride ions now located on the surface of the semiconductor substrate. Insertion of the semiconductor substrate into an anneal—oxidation chamber results in a second native oxide formed on the surface of the semiconductor substrate, with the thickness of the second native oxide limited by the presence of the fluoride ions on the surface of the semiconductor substrate. An anneal procedure performed at a temperature greater than 1000° C.

Abstract: Disclosed is a a method of fabricating a MEMS device by means of surface micromachining without leaving any stiction or residues by etching silicon oxide of a sacrificial layer, which is an intermediate layer between a substrate and a microstructure, rather than by etching silicon oxide of a semiconductor device. The method according to the invention includes the steps of supplying alcohol vapor bubbled with anhydrous HF, maintaining a temperature of the supplying device and a moving path of the anhydrous HF and the alcohol to be higher than a boiling point of the alcohol, performing a vapor etching by controlling a temperature and a pressure to be within the vapor region of a phase equilibrium diagram of water, and removing silicon oxide of a sacrificial layer on a lower portion of the microstructure.

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permitivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.

Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon wafer 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.

Abstract: A processing solution containing hydrogen peroxide, hydracid fluoride salt, and water is used for pre-cleaning prior to a step of forming a gate oxide film 14 by subjecting a silicon water 1 to a heat treatment. Tetraalkyl ammonium fluoride, ammonium fluoride or the like is used as hydracid fluoride salt.

Abstract: Heavily concentrated impurities are selectively introduced into an exposed region of an oxide film. The exposed region of the oxide film where the impurities are introduced is selectively etched so that a surface of the semiconductor substrate is exposed An oxidizing process is performed and a second oxide film is formed on the first oxide film and the exposed surface of the semiconductor substrate. A polysilicon layer is formed as the floating gate.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: An in-process microelectronics device is treated by applying a heated liquid to the surface of the in-process microelectronics device, removing a portion of the liquid from the surface of the in-process microelectronics device and applying anhydrous HF gas to the surface of the in-process microelectronics device.

Abstract: A method for removing silicon oxide from a surface of a substrate is disclosed. The method includes depositing material onto the silicon oxide (110) and heating the substrate surface to a sufficient temperature to form volatile compounds including the silicon oxide and the deposited material (120). The method also includes heating the surface to a sufficient temperature to remove any remaining deposited material (130).

Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

Abstract: A method for forming aluminum bumps by first sputter aluminum and then chemical mechanical polishing to remove excess aluminum is disclosed. In the method, a pre-processed electronic substrate which has a plurality of I/O pads formed on top is first provided. An insulating material layer such as SiO2, Si3N4, SOG or polyimide is then deposited on the pads to a thickness that is essentially the thickness of the aluminum bumps to be formed. A plurality of openings with one on each of the plurality of I/O pads is then photolithographically formed, followed by a sputtering deposition to fill the plurality of openings with a metal that includes aluminum. A chemical mechanical polishing technique is then used to remove the excess aluminum so that a top surface of the aluminum bump is flush with the top surface of the insulating material layer, followed by the final step of removing at least partially a thickness of the insulating material layer by a wet etch process.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A method of making a micromirror unit is provided. In accordance with the method, a micromirror unit is made from a material substrate having a multi-layer structure composed of silicon layers and at least one intermediate layer. The resulting micromirror unit includes a mirror forming base, a frame and a torsion bar. The method includes the following steps. First, a pre-torsion bar is formed by subjecting one of the silicon layers to etching. The obtained pre-torsion bar is rendered smaller in thickness than the mirror forming base and is held in contact with the intermediate layer. Then, the desired torsion bar is obtained by removing the intermediate layer contacting with the pre-torsion bar.

Abstract: A method of fabricating an ultra shallow junction of a field effect transistor is provided. The method includes the steps of etching a substrate near a gate structure to define a source region and a drain region of the transistor, forming a spacer/protective film having poor step coverage to protect frontal surfaces of the source and drain regions, laterally etching sidewalls of the regions beneath a gate dielectric to define a channel region, and removing the protective film.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method. Means for Solution: The bonding pads 20 upon a semiconductor chip 18 are provided with a bonding region 30 and a probe contact region 32, and one end of the conductor wire 22 is bonded to the bonding region 30. The probe contact to the probe contact region 32 is used for making contact to the tips of the test probes in the semiconductor chip inspection step performed prior to the bonding.

Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Abstract: The present invention relates to a production process which, in the production of an electronic component by wet etching of an insulating layer in a laminate, is low in cost, does not use any organic solvent, which poses a problem of waste treatment. The production process of an electronic component comprises the steps of: wet etching a laminate of conductive inorganic material layer—insulating layer—conductive inorganic material layer or a laminate of conductive inorganic material layer—insulating layer to pattern the conductive inorganic material layer; and then performing wet etching to pattern the insulating layer. The patterning of the insulating layer by wet etching is carried out in a continuous form using a dry film resist; and, the dry film resist is laminated by roll pressing onto the laminate under a reduced pressure of not more than 80 KPa.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in a trench on a semiconductor substrate. In one embodiment, a method for forming a bottom oxide layer in a trench on a semiconductor substrate comprises depositing an oxide layer along the surface of the sidewall and the bottom of a trench on a semiconductor substrate which has top layers, depositing a nitride layer along the surface of the said oxide layer, and forming a photo-resist filler in a trench. The top surface of the photo-resist filler is lower than the top surface of the substrate to expose a portion of the nitride layer uncovered by the photo-resist filler. The exposed portion of the nitride layer is removed to expose the oxide layer underneath. A portion of the oxide layer on the sidewalls of a trench is removed to form a bottom oxide layer in a trench.

Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

Abstract: A method for removing a polysilicon layer from a non-silicon layer comprising the following steps. A structure having a non-silicon layer formed thereover is provided. A first polysilicon layer is formed upon the non-silicon layer. The first polysilicon layer is removed from over the non-silicon layer to expose the non-silicon layer using a NH4OH:DIW dip solution process having a NH4OH:DIW ratio of from about 1:2 to 1:8. Whereby the non-silicon layer is substantially unaffected by the NH4OH:DIW dip solution process.

Abstract: A semiconductor device having a metallized interconnect structure includes a conductor having an upper contact surface and an edge surface depending from the upper contact surface. An opening in an insulating layer overlying the conduct exposes at least a portion of the upper contact surface and at least a portion of edge surface. A liner material covers the edge surface and a portion of the upper contact surface exposed by the opening. An electrically conductive material resides within the opening and is separated from the edge surface by the liner material. A method for fabricating the metallized contact structure includes the deposition and anisotrophic etching of a liner material that is differentially etchable with respect to the insulating layer overlying the conductor. By covering the edge surface of the conductor, a metallized contact structure is provided that can be reliably fabricated using zero-overlap design tolerances.

Abstract: A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.

Abstract: A method for manipulating MEMS devices integrated on a semiconductor wafer and intended to be diced one from the other includes bonding of the semiconductor wafer including the MEMS devices on a support with interposition of a bonding sheet. The method may also include completely cutting or dicing of the semiconductor wafer into a plurality of independent MEMS devices, and processing the MEMS devices diced and bonded on the support in a treatment environment for semiconductor wafers. A support for manipulating MEMS devices is also included.

Abstract: A method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer including providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing the carbon doped oxide layer according to an oxidizing treatment to convert at oxidize at least a portion of the carbon doped oxide layer to produce silicon oxide; and, wet etching the silicon oxide to substantially remove the silicon oxide.

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract: A method for removing layers or layer systems from a substrate and subsequent application onto an alternative substrate. A porous breakaway layer is formed by anodization in hydrofluoric acid. Optionally, a stabilizing layer with lower porosity is previously produced on top of the breakaway layer. The oxide of the porous breakaway layer or the stabilizing layer is removed by brief contact with HF, and an epitaxial layer is applied on the porous breakaway layer or the stabilizing layer. The epitaxial layer or the layer system is then removed from the substrate, and the epitaxial layer or the layer system is applied onto an alternative substrate. Optionally, the stabilizing layer and/or residues of the breakaway layer are removed from the epitaxial layer.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Nanopores for single-electron devices may be used as templates for placing of a desired number of nanoparticles at a desired location in the devices. Nanopores may be fabricated by providing on a substrate spaced apart electrode regions, a spacer region therebetween, and a cover layer on the spaced apart electrode regions and on the spacer region. A wet etching solution is contacted to the cover layer. At least one of the spaced apart electrode regions is energized, to selectively wet etch the cover layer adjacent the spacer region and define a nanopore in the cover layer adjacent the spacer region. At least one nanoparticle is placed in the nanopore. Accordingly, nanopores can be aligned to a buried spacer region.

Abstract: Methods for etching or removing oxide scale from a substrate by applying a composition containing a polymer and an effective amount of hydrofluoric acid and maintaining the composition on the substrate until the substrate is etched or the oxide scale is removed.

Abstract: A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.

Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.