Charge Transfer Device (e.g., Ccd, Etc.) Patents (Class 438/75)
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Patent number: 7410823Abstract: An image sensor includes a substrate region of a first conductivity type, a photodiode region of a second conductivity type located in the substrate, a hole accumulated device (HAD) region of the first conductivity type located at a surface of the substrate and over the photodiode region, and a transfer gate located over the surface of the substrate adjacent the HAD region. The image sensor further includes a first channel region of the first conductivity type located in the substrate and aligned below the transfer gate, a second channel region of the second conductivity type located in the substrate between said transfer gate and the first channel region, and an floating diffusion region which is located in the substrate and which electrically contacts the second channel region.Type: GrantFiled: February 20, 2007Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Jongcheol Shin
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Patent number: 7402451Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.Type: GrantFiled: March 30, 2005Date of Patent: July 22, 2008Assignee: Micron Technology, Inc.Inventor: Howard E. Rhodes
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Patent number: 7402787Abstract: An image sensor includes a substrate having photosensitive areas; an insulator spanning at least a portion of the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area; and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging areas and the second layer overlays edges of the first layer.Type: GrantFiled: October 30, 2007Date of Patent: July 22, 2008Assignee: Eastman Kodak CompanyInventors: David N. Nichols, Eric G. Stevens, Stephen L. Kosman
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Patent number: 7402452Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.Type: GrantFiled: July 25, 2005Date of Patent: July 22, 2008Assignee: FUJIFILM CorporationInventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
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Publication number: 20080153196Abstract: A method of manufacturing image sensor devices, in which a dielectric protecting layer is formed on a photo-receiving region before a gate of a MOS is formed. Therefore, during the subsequent processes for forming the MOS component, damage to the surface of the photo-receiving region caused by plasma or etching can be avoided, and the dark current is improved. An image sensor device manufactured by the method is also disclosed and characterized in that a part of the gate stacks over the dielectric protecting layer and the surface of the photo-receiving region is smooth to obtain good performance.Type: ApplicationFiled: March 5, 2008Publication date: June 26, 2008Inventor: Ching-Hung Kao
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Publication number: 20080153197Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.Type: ApplicationFiled: February 19, 2008Publication date: June 26, 2008Inventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
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Patent number: 7391001Abstract: An image sensor includes a substrate having photosensitive areas; an insulator spanning the substrate; and a first and second layer of a multi-layer metallization structure, wherein the first layer forms light shield regions over selected portions of the photosensitive area as well forming circuit interconnections and barrier regions to prevent spiking into the substrate or gates at contacts in the non-imaging area; and the second layer spanning the interconnections and barrier regions of the first layer only over the non-imaging areas and the second layer overlays edges of the first layer.Type: GrantFiled: February 28, 2005Date of Patent: June 24, 2008Assignee: Eastman Kodak CompanyInventors: David N. Nichols, Eric G. Stevens, Stephen L. Kosman
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Patent number: 7382003Abstract: A solid-state image pick-up unit comprises: a semiconductor substrate comprising an area in which a photoelectric converting portion is formed; and an electric charge transfer portion that transfers an electric charge formed by the photoelectric converting portion, wherein the electric charge transfer portion comprises: an electric charge transfer electrode including a first layer electrode and a second layer electrode; and a gate oxide film, the gate oxide film comprises a second gate oxide film formed under the second layer electrode, the second gate oxide film comprising an ONO film which comprises a SiO film, a SiN film and a SiO film in this order, and the second gate oxide film is continuously formed to cover whole of a region between the first layer electrode and the second layer electrode and a region under the second layer electrode.Type: GrantFiled: March 14, 2006Date of Patent: June 3, 2008Assignee: Fujifilm CorporationInventor: Ryoichi Homma
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Publication number: 20080111159Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.Type: ApplicationFiled: November 15, 2006Publication date: May 15, 2008Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Richard J. Rassel
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Patent number: 7368771Abstract: Provided are a complementary metal oxide semiconductor (CMOS) image sensor and a method of fabricating the same, where the CMOS image sensor includes a photodiode, a drive transistor, a reset transistor, and a selection transistor; the drive transistor includes a threshold voltage adjustment region doped with impurities of a type substantially identical to that of impurities doped into a source and a drain of the drive transistor; and the CMOS image sensor includes pixels with expanded output signal ranges.Type: GrantFiled: March 16, 2006Date of Patent: May 6, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Seob Roh, Seok-Ha Lee
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Patent number: 7364960Abstract: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.Type: GrantFiled: August 25, 2005Date of Patent: April 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Jeong Ho Lyu
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Patent number: 7361527Abstract: An image sensor includes: a gate structure on a semiconductor layer of a first conductive type; a first impurity region of the first conductive type aligned with one side of the gate structure and extending to a predetermined depth from a surface portion of the semiconductor layer; spacers formed on sidewalls of the gate structure; and a second impurity region of a second conductive type formed in a portion of the semiconductor layer under the first impurity region, wherein the first impurity region includes: a first region of which portion aligned with the one side of the gate structure; a second region aligned with the one of the spacers and having a concentration higher than that of the first region; and a third region apart from the one side of the gate structure with a predetermined distance and having a concentration higher than that of the second region.Type: GrantFiled: July 28, 2005Date of Patent: April 22, 2008Assignee: Magnachip Semiconductor, Ltd.Inventor: Youn-Sub Lim
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Patent number: 7358105Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.Type: GrantFiled: December 2, 2005Date of Patent: April 15, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Nagasaki, Syouji Tanaka, Yoshiyuki Matsunaga
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Patent number: 7354791Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P?-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.Type: GrantFiled: September 13, 2004Date of Patent: April 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tooru Yamada
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Patent number: 7348204Abstract: A method for fabricating a solid state imaging device comprising photoelectric conversion sections and charge transfer sections having single-layered charge transfer electrodes for transferring charges generated in the photoelectric conversion sections, the method including formation of the charge transfer electrodes, wherein the formation of the charge transfer electrodes comprises the steps of: forming a conductive film on a surface of a semiconductor substrate having formed thereon a gate oxide film; forming a mask pattern on the conductive film; forming interelectrode spacings in the conductive film using the mask pattern as a mask to make a patterned conductive film; and forming an insulating film to fill in the interelectrode spacings by vacuum chemical vapor deposition.Type: GrantFiled: April 8, 2005Date of Patent: March 25, 2008Assignee: Fujifilm CorporationInventor: Hiroaki Takao
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Patent number: 7329557Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.Type: GrantFiled: February 10, 2006Date of Patent: February 12, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ken Mimuro, Mikiya Uchida, Mototaka Ochi
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Patent number: 7321141Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.Type: GrantFiled: April 18, 2006Date of Patent: January 22, 2008Assignee: United Microelectronics Corp.Inventor: Jhy-Jyi Sze
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Patent number: 7316937Abstract: Light detecting elements are formed in areas marked off by scribe lines on a semiconductor substrate, and color filters are deposited in such a manner as to cover the formed areas of the light detecting elements, and then an infrared cut-off filter, on which an infrared reflecting film is vapor-deposited in such a manner as to cover the formed areas of the light detecting elements, is firmly fixed to the surface of the semiconductor substrate through the interposition of a translucent resin layer, such as an epoxy adhesive, to thereby form a multilayered structure, and this multilayered structure is diced along scribe lines.Type: GrantFiled: June 28, 2004Date of Patent: January 8, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Kazuaki Kojima, Minoru Hamada
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Publication number: 20070296844Abstract: The solid-state imaging device in the present invention is a solid-state imaging device that includes plural pixel cells arranged on a semi-conductor substrate, and a driving unit installed on the semi-conductor substrate in order to drive each pixel cell, wherein each pixel cell includes: a photodiode which converts incident light into a signal charge; a transfer transistor which transfers the signal charge of the photodiode to a floating diffusion unit; the floating diffusion unit accumulates the transferred signal charge; and a control implantation layer which is positioned under a gate of the transfer transistor, and becomes a charge transfer path when the charge is transferred from the photodiode to the control implementation layer, wherein an impurity concentration of the control implantation layer is denser toward the bottom of the substrate than toward the surface of the semi-conductor substrate.Type: ApplicationFiled: June 5, 2007Publication date: December 27, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Syouzi TANAKA
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Patent number: 7312098Abstract: There is provided a CMOS image sensor comprises a LOCOS isolation film 6 formed on the surface of a semiconductor substrate 100 containing a peripheral circuit 31 and a photodiode region 15, a gate electrode 1 formed on the surface of the peripheral circuit 31, a surface-protecting film 8 deposited on at least a portion of the photodiode region 15, and a sidewall 19 of the gate electrode formed without damaging the portion of photodiode region 15 on which a surface-protecting film 8 is deposited, thereby eliminating etching damage on the surface of the substrate to be expected for a photodiode during blanket etch-back, and suppressing fixed pattern noise (FPN).Type: GrantFiled: October 5, 2001Date of Patent: December 25, 2007Assignee: Renesas Technology Corp.Inventor: Masatoshi Kimura
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Patent number: 7303938Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.Type: GrantFiled: February 5, 2004Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventors: Chandra Mouli, Howard Rhodes
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Patent number: 7303931Abstract: Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces are disclosed herein. In one embodiment, a method for forming microlenses includes forming a plurality of shaping members on a microfeature workpiece between adjacent pixels, reflowing the shaping members to form a shaping structure between adjacent pixels, depositing lens material onto the workpiece, removing selected portions of the lens material adjacent to the shaping structure such that discrete masses of lens material are located over corresponding pixels, and heating the workpiece to reflow the discrete masses of lens material and form a plurality of microlenses.Type: GrantFiled: February 10, 2005Date of Patent: December 4, 2007Assignee: Micron Technology, Inc.Inventors: Ulrich C. Boettiger, Jin Li
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Patent number: 7297570Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the efficiency in condensing the light by forming a multi-layered micro lens with various materials having different refractive indexes, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a first micro-lens layer on an entire surface of the color filter layers, to condense the light; and a plurality of second micro-lens layers on the first micro-lens layer in correspondence with the respective photosensitive devices, wherein the second micro-lens layer has the different refractive index from that of the first micro-lens layer.Type: GrantFiled: December 28, 2004Date of Patent: November 20, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Shang Won Kim
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Patent number: 7294872Abstract: PROBLEM To provide a high quality solid state image pickup device. SOLUTION Impurities are implanted into a semiconductor substrate to form vertical transfer channels for transferring electric charges in a first direction and to form a drain near each of the vertical transfer channels via a gate which forms a barrier. A first silicon oxide film, a silicon nitride film and a second silicon oxide film are deposited in this order from the bottom, on the surfaces of the vertical transfer channels, gates and drains. A first layer vertical transfer electrode is formed on the second silicon oxide film above the vertical transfer channel, and an insulating film if formed on the surface of the first layer vertical transfer electrode. The second silicon oxide film and silicon nitride film are etched in such a manner that the silicon nitride film covers the vertical transfer channel and extends above the gate excepting a portion near the drain.Type: GrantFiled: March 20, 2006Date of Patent: November 13, 2007Assignee: Fujifilm CorporationInventor: Masanori Nagase
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Patent number: 7294566Abstract: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and includes forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a material of the wiring pattern to an area surrounded by the bank to form a first wiring pattern; discharging a second functional liquid onto the first wiring pattern to form a second wiring pattern; and collectively baking the wiring pattern of a plurality of layers including the first wiring pattern and the second wiring pattern.Type: GrantFiled: October 17, 2005Date of Patent: November 13, 2007Assignee: Seiko Epson CorporationInventors: Katsuyuki Moriya, Toshimitsu Hirai
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Patent number: 7285438Abstract: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate (6) is constructed by laminating a support substrate (16) composed of silicon, a buffer layer (18), and a thin silicon layer (20) composed of single-crystal silicon. p? regions (26) (overflow barrier) and n-type regions (28) which function as transfer paths are formed under the optical sensors (4). The first and the second transfer electrodes (12 and 14) are disposed between the buffer layer (18) and the n-type regions (28), and an insulating film (30) is interposed between the n-type regions (28) and the first and the second transfer electrodes (12 and 14). In this structure, the light-receiving area is large since the transfer electrodes are not disposed in the front region.Type: GrantFiled: January 31, 2006Date of Patent: October 23, 2007Assignee: Sony CorporationInventor: Takashi Kasuga
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Patent number: 7217601Abstract: In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.Type: GrantFiled: October 22, 2003Date of Patent: May 15, 2007Assignee: Massachusetts Institute of TechnologyInventors: Barry E. Burke, Vyshnavi Suntharalingam
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Patent number: 7192884Abstract: Disclosed is a method for manufacturing a semiconductor laser device, comprising the steps of: (a) forming a first conductive-type clad layer, an active layer, and a second conductive-type clad layer on a first conductive-type semiconductor substrate; (b) forming a ridge structure by selectively etching the second conductive-type clad layer; (c) forming a current blocking layer around the ridge structure, the current blocking layer having protrusions on the upper surface thereof adjacent to the ridge structure, and an amorphous and/or polycrystalline layer on a partial area thereof; and (d) removing at least the amorphous and/or polycrystalline layer from the current blocking layer, and wet-etching the upper surface of the current blocking layer so that the protrusions are reduced in size.Type: GrantFiled: October 22, 2003Date of Patent: March 20, 2007Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Joon Kim, Byung Deuk Moon, Sang Heon Han
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Patent number: 7186583Abstract: A pixel of a semiconductor-based image detector includes a photodetector, at least one switching device serially connected to the photodetector and a bypass device interposed between the photodetector and a power supply voltage. Accordingly, even though excess charges may be generated in the photodetector, the excess charges flow into the power supply through the bypass device. Blooming can thereby be reduced or suppressed.Type: GrantFiled: February 7, 2006Date of Patent: March 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-Ha Lee
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Patent number: 7179675Abstract: A method for fabricating an image sensor includes forming a seed layer on a semiconductor substrate, forming a blocking layer on the seed layer, partially exposing a region for transistor in an active region of the semiconductor substrate by patterning the seed layer and the blocking layer, selectively forming a gate insulating material layer in a portion of the exposed region for transistor, filling a gate electrode material layer in the exposed region for transistor over the gate insulating material layer, forming a gate insulating layer pattern and a gate electrode pattern by selectively removing the blocking layer, the gate insulating material layer, the gate electrode material layer, and the seed layer, and forming source and drain diffusion layers and a photodiode on both sides of the gate insulating layer pattern and the gate electrode pattern by selectively doping impurity ions.Type: GrantFiled: December 30, 2004Date of Patent: February 20, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Hee Sung Shim
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Patent number: 7180151Abstract: An image sensing device includes a gate dielectric layer formed on a substrate and a transfer gate formed on the gate dielectric layer. A masking layer is formed on the transfer gate, the masking layer having a width smaller than a width of the transfer gate, such that a portion of the transfer gate protrudes laterally from under the masking layer. A photodiode is formed in the substrate to be self-aligned with the masking layer and to extending laterally under the transfer gate, that is, to overlap the transfer gate. Because of the overlap of the photodiode with the transfer gate, offset between the photodiode and the transfer gate is eliminated, such that an image lag phenomenon is eliminated.Type: GrantFiled: January 27, 2005Date of Patent: February 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Young Hoon Park
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Patent number: 7179676Abstract: A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.Type: GrantFiled: March 28, 2005Date of Patent: February 20, 2007Assignee: Kenet, Inc.Inventors: Gerhard Sollner, Lawrence J. Kushner, Michael P. Anthony, Edward Kohler, Wesley Grant
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Patent number: 7172922Abstract: A “black” pixel for measuring dark current is produced using carbon-based or pigment-based black photosensitive resist deposited on a support layer that is formed using negative-tone photosensitive resist, both being formed over the light sensitive portion of the black pixel. After an array of pixels is fabricated, a negative-tone resist layer is deposited on the upper insulator formed over the pixels, and a region of the negative-tone resist located over the black pixel is exposed using a first mask. A carbon-based resist layer is deposited on the negative-tone resist layer, and a region of the carbon-based resist located over the black pixel is exposed using a second mask. The negative-tone and carbon-based resists are then developed to remove portions of the layers not located over the black pixel.Type: GrantFiled: August 19, 2002Date of Patent: February 6, 2007Assignee: Tower Semiconductor Ltd.Inventors: Almog Benjamin, Hanan Wolf, Eyal Shevartzberg
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Patent number: 7166489Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a planarization layer on the color filter layers, and having first micro-lens by intaglio in correspondence with the respective photosensitive patterns to condense the light secondly; and a plurality of second micro-lens layers on the planarization layer in correspondence with the respective photosensitive devices, to condense the light firstly.Type: GrantFiled: December 28, 2004Date of Patent: January 23, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Shang Won Kim
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Patent number: 7135362Abstract: The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor. The isolation layer includes: a field insulating layer formed on a predetermined portion of a substrate in the logic area to thereby define an active area and a field area; a field stop ion implantation area formed on a predetermined portion of the substrate in the pixel area, the field stop ion implantation area having a predetermined depth from a surface of the substrate to define an active area and a field area; and an oxide layer deposited on a substrate surface corresponding to the field stop ion implantation area.Type: GrantFiled: June 30, 2004Date of Patent: November 14, 2006Assignee: Hynix Semiconductor Inc.Inventor: Kyung-Lak Lee
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Patent number: 7132724Abstract: A vertical-color-filter detector disposed in a semiconductor structure comprises a complete-charge-transfer detector comprising semiconductor material doped to a first conductivity type and has a horizontal portion disposed at a first depth in the semiconductor structure substantially below an upper surface thereof and a vertical portion communicating with the upper surface of the semiconductor structure. The complete-charge-transfer detector is disposed within a first charge container forming a potential well around it. The horizontal portion of the complete-charge-transfer detector has a substantially uniform doping density in a substantially horizontal direction and the vertical portion of the complete-charge-transfer detector has a doping density that is a monotonic function of depth and is devoid of potential wells. A first charge-transfer device is disposed substantially at an upper surface of the semiconductor structure and is coupled to the vertical portion of the complete-charge-transfer detector.Type: GrantFiled: April 11, 2003Date of Patent: November 7, 2006Assignee: Foveon, Inc.Inventor: Richard B. Merrill
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Patent number: 7127793Abstract: A producing method of producing a solid state pickup device is provided. Imaging elements are formed on a wafer in a matrix form. Each of the imaging elements has a light receiving surface and plural contact points. Receiving surface border portions are formed on a glass plate to protrude therefrom in a matrix form by etching. The receiving surface border portions are attached to the wafer to surround the light receiving surface in each of the receiving surface border portions. The light receiving surface is spaced from the glass plate. The glass plate is diced outside respectively the receiving surface border portions, to form shield glass for covering the light receiving surface. The wafer is diced for each of the imaging elements, to obtain the solid state pickup device having the shield glass and one of the imaging elements.Type: GrantFiled: April 24, 2003Date of Patent: October 31, 2006Assignee: Fuji Photo Film Co., Ltd.Inventors: Takeshi Misawa, Akihisa Yamazaki, Atsushi Misawa
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Patent number: 7125738Abstract: A method of fabrication of a photosensitive device is disclosed. A substrate with at least an insulator layer formed thereon is provided. The insulator layer comprises a plurality of photoreceiving regions, and a plurality of conductive patterns are formed thereon without covering the photoreceiving regions. A dielectric layer is formed on the insulator and the conductive patterns, and polished by CMP thereof. The dielectric layer comprises a first dielectric layer formed by PECVD and a second dielectric layer formed by HDPCVD.Type: GrantFiled: October 14, 2004Date of Patent: October 24, 2006Assignee: Powerchip Semiconductor Corp.Inventors: Ming-Jeng Huang, Chen-Chiu Hsue
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Patent number: 7125740Abstract: A method of fabricating a solid-state image pickup device comprising forming mask patterns corresponding to patterns of first and third transfer electrodes, which are to be alternately arranged in each vertical transfer register formation region and which are to extend in parallel to each other between light receiving portions adjacent to each other in the vertical direction, on a first electrode material layer. The method also includes forming side walls on each of the mask patterns. The method further includes patterning the first electrode material layer via the mask patterns having the side walls, to form first and third transfer electrodes formed by the first layer.Type: GrantFiled: July 12, 2004Date of Patent: October 24, 2006Assignee: Sony CorporationInventors: Junji Yamane, Kunihiko Hikichi
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Patent number: 7122397Abstract: A method for manufacturing a CMOS image sensor includes depositing a gate oxide film and polysilicon on a substrate, forming a gate electrode by patterning and etching the gate oxide layer and the polysilicon, wherein the polysilicon of the gate electrode extends to an active region of the substrate, forming spacers on the sidewalls of the gate electrode, forming a mask pattern having an opening over the active region, removing the spacers and the gate oxide layer thereunder in the active region, removing the mask pattern, depositing a protective layer on a pixel region of the substrate, and conducting a salicide formation process on the resulting structure.Type: GrantFiled: September 24, 2004Date of Patent: October 17, 2006Assignee: Dongbu Electronics Co., Ltd.Inventor: Keun Hyuk Lim
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Patent number: 7112466Abstract: An improved semiconductor device that reduces reverse bias junction leakage in a photodiode by using a junction isolation region to isolate the photodiode from a trench isolation region. The improved semiconductor device improves image quality for different applications such as stand-alone digital cameras and digital cameras embedded in other imaging devices such as cellular phones and personal digital assistants.Type: GrantFiled: November 13, 2002Date of Patent: September 26, 2006Assignee: ESS Technology, Inc.Inventor: Richard A. Mann
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Patent number: 7105373Abstract: A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.Type: GrantFiled: August 14, 2003Date of Patent: September 12, 2006Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Andy Strachan
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Patent number: 7098067Abstract: A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.Type: GrantFiled: December 13, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: James W. Adkisson, Mark D. Jaffe, Arthur P. Johnson, Robert K. Leidy, Jeffrey C. Maling
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Patent number: 7084000Abstract: A solid-state imaging device according to the present invention includes a semiconductor substrate; a photoelectric conversion portion formed on the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and covering the photoelectric conversion portion; a vertical transfer portion for transferring a charge generated at the photoelectric conversion portion in a vertical direction; and a multilayer transfer gate electrode for transferring the charge of the vertical transfer portion. At least one layer of the multilayer transfer gate electrode is made of at least two impurity doped amorphous silicon films of different impurity concentration.Type: GrantFiled: December 7, 2004Date of Patent: August 1, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Naoki Iwawaki
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Patent number: 7074638Abstract: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor substrate, bonding a translucent member to the surface of the semiconductor substrate in order to have a gap opposite to each light receiving region of the IT-CCD, and isolating a bonded member obtained at the bonding step for each of the IT-CCDs.Type: GrantFiled: July 14, 2003Date of Patent: July 11, 2006Assignee: Fuji Photo Film Co., Ltd.Inventors: Hiroshi Maeda, Kazuhiro Nishida, Yoshihisa Negishi, Shunichi Hosaka
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Patent number: 7074639Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.Type: GrantFiled: December 17, 2001Date of Patent: July 11, 2006Assignee: Massachusetts Institute of TechnologyInventors: Barry E. Burke, Eugene D. Savoye
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Patent number: 7071502Abstract: It is known to bring the surface into the inverted state in CCD imaging devices with buried channels during the integration period in order to keep the dark current low (All Gates Pinning). A desired potential profile, with wells in which the charge is integrated bounded by potential barriers, is obtained through, e.g. a doping profile in the channel. Line-shaped constrictions in the thickness or the doping concentration of the well enable charge-reset and function also as an anti-blooming barrier. In a charge coupled device according to the invention, the line-shaped constrictions in the thickness or the doping concentration of the second layer run perpendicular to the length direction of the channel and parallel to the gates and at least one line shaped constriction is positioned below each series of gates. In this way, an increased charge storage capacity and optical sensitivity are obtained while electronic shutter functionality is maintained.Type: GrantFiled: June 18, 2004Date of Patent: July 4, 2006Assignee: Dalsa CorporationInventors: Jan Theodoor Jozef Bosiers, Agnes Catherina Maria Kleimann
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Patent number: 7071020Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.Type: GrantFiled: May 11, 2005Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Sungkwon Hong
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Patent number: 7060592Abstract: An image sensor comprising an image sensing device layer, a silicon-on-insulator (SOI) layer, an optical device array and a substrate is provided. The SOI layer has a first surface and a second surface. The image sensing device layer is formed on the first surface of the SOI layer. The optical device array is formed on the second surface of the SOI layer. The substrate is disposed above the second surface of the SOI layer and the optical device array is disposed between the substrate and the SOI layer. An incident light coming from the outside environment, passes through the optical device array and the SOI layer, and is received by sensing devices formed in the image sensing device layer. In this manner, the probability of absorption or reflection of the incident light is reduced. Therefore, the sensing performance and the yield of the image sensor of the present invention is improved.Type: GrantFiled: September 15, 2004Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Cheng-Kuang Sun, Kuang-Chih Cheng, Kuang-Shin Lee
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Patent number: 7049167Abstract: The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively.Type: GrantFiled: December 23, 2003Date of Patent: May 23, 2006Assignee: Hynix Semiconductor Inc.Inventor: Won-Ho Lee