Reaction With Silicon Semiconductive Region (e.g., Oxynitride Formation, Etc.) Patents (Class 438/769)
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Publication number: 20090311857Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.Type: ApplicationFiled: August 24, 2009Publication date: December 17, 2009Applicant: ASM America, Inc.Inventors: Michael A. Todd, Keith D. Weeks, Christiaan J. Werkhoven, Christophe F. Pomarede
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Patent number: 7629270Abstract: A nitrogen precursor that has been activated by exposure to a remotely excited species is used as a reactant to form nitrogen-containing layers. The remotely excited species can be, e.g., N2, Ar, and/or He, which has been excited in a microwave radical generator. Downstream of the microwave radical generator and upstream of the substrate, the flow of excited species is mixed with a flow of NH3. The excited species activates the NH3. The substrate is exposed to both the activated NH3 and the excited species. The substrate can also be exposed to a precursor of another species to form a compound layer in a chemical vapor deposition. In addition, already-deposited layers can be nitrided by exposure to the activated NH3 and to the excited species, which results in higher levels of nitrogen incorporation than plasma nitridation using excited N2 alone, or thermal nitridation using NH3 alone, with the same process temperatures and nitridation durations.Type: GrantFiled: August 24, 2005Date of Patent: December 8, 2009Assignee: ASM America, Inc.Inventors: Johan Swerts, Hilde De Witte, Jan Willem Maes, Christophe F. Pomarede, Ruben Haverkort, Yuet Mei Wan, Marinus J. De Blank, Cornelius A. Van Der Jeugd, Jacobus Johannes Beulens
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Patent number: 7618901Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.Type: GrantFiled: May 4, 2007Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Gurtej Singh Sandhu, Randhir P S Thakur
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Patent number: 7618891Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: GrantFiled: May 1, 2006Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
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Publication number: 20090275212Abstract: A semiconductor wafer implanted with impurities is loaded into a chamber. After oxygen gas is introduced around the semiconductor wafer, the semiconductor wafer is irradiated with a flash of light from flash lamps for an irradiation time not shorter than 0.1 milliseconds and not longer than 100 milliseconds, to thereby momentarily raise the surface temperature of the semiconductor wafer up to not lower than 800° C. and not higher than 1300° C. Since the temperature rises in an extremely short time, it is possible to activate the impurities while suppressing thermal diffusion thereof. Further, since an extremely thin oxide film is formed on a surface of the semiconductor wafer, this film serves as a protection film in a subsequent cleaning process, to prevent removal of the impurities.Type: ApplicationFiled: March 16, 2009Publication date: November 5, 2009Inventor: Shinichi KATO
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Publication number: 20090263716Abstract: The present invention relates to methods for producing anode materials for use in nonaqueous electrolyte secondary batteries. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a solution containing metals ions and a dissolution component. When the anode material is contacted with the solution, the dissolution component dissolves a part of the semiconductor material in the anode material and deposit the metal on the anode material. After deposition, the anode material and metal are annealed to form a uniform metal-semiconductor alloy layer. The anode material of the present invention can be in a monolithic form or a particle form. When the anode material is in a particle form, the particulate anode material can be further shaped and sintered to agglomerate the particulate anode material.Type: ApplicationFiled: April 17, 2009Publication date: October 22, 2009Inventors: Murali Ramasubramanian, Robert M. Spotnitz
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Publication number: 20090250768Abstract: A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.Type: ApplicationFiled: March 20, 2009Publication date: October 8, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro SATO, Fumitaka ARAI, Yoshio OZAWA, Takeshi KAMIGAICHI
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Publication number: 20090233451Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.Type: ApplicationFiled: May 26, 2009Publication date: September 17, 2009Inventors: Yoshitaka Tsunashima, Seiji Ihumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
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Patent number: 7585729Abstract: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.Type: GrantFiled: October 5, 2007Date of Patent: September 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Kweon Baek, Bon-Young Koo, Chul-Sung Kim, Jung-Geun Jee, Young-Jin Noh
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Publication number: 20090215280Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.Type: ApplicationFiled: March 16, 2009Publication date: August 27, 2009Applicant: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Jason Patrick Henning, Andrew Mackenzie, Scott Allen, Scott Thomas Sheppard, Richard Peter Smith, Saptharishi Sriram, Allan Ward, III
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Patent number: 7563726Abstract: Disclosed are a semiconductor device with dual gate dielectric layers and a method for fabricating the same. The semiconductor device includes: a silicon substrate divided into a cell region where NMOS transistors are formed and a peripheral region where NMOS and PMOS transistors are formed; a targeted silicon oxide layer formed on the silicon substrate in the cell region; an oxynitride layer formed on the silicon substrate in the peripheral region; a first gate structure formed in the cell region; a second gate structure formed on the oxynitride layer in an NMOS region of the peripheral region; and a third gate structure formed on the oxynitride layer in a PMOS region of the peripheral region.Type: GrantFiled: September 16, 2005Date of Patent: July 21, 2009Assignee: Hynix Semiconductor Inc.Inventors: Heung-Jae Cho, Kwan-Yong Lim, Seung-Ryong Lee
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Publication number: 20090181548Abstract: A vertical plasma processing apparatus for a semiconductor process includes a process container having a process field configured to accommodate a plurality of target substrates at intervals in a vertical direction, and a marginal space out of the process field. In processing the target substrates, a control section simultaneously performs supply of a process gas to the process field from a process gas supply circuit and supply of a blocking gas to the marginal space from a blocking gas supply circuit to inhibit the process gas from flowing into the marginal space.Type: ApplicationFiled: March 25, 2009Publication date: July 16, 2009Inventors: Toshiki Takahashi, Kohei Fukushima, Koichi Orito, Jun Sato
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Patent number: 7557030Abstract: A method for fabricating a recess gate in a semiconductor device is provided. The method includes selectively etching an active region of a substrate to form a recess pattern, performing a post treatment on the recess pattern using a plasma, and forming a gate pattern in the recess pattern.Type: GrantFiled: November 8, 2006Date of Patent: July 7, 2009Assignee: Hynix Semiconductor Inc.Inventors: Seung-Bum Kim, Ki-Won Nam
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Patent number: 7550353Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.Type: GrantFiled: March 13, 2007Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hak Lee, Woong-Hee Sohn, Jae-Hwa Park, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park
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Patent number: 7547643Abstract: Adhesion of a porous low K film to an underlying barrier layer is improved by forming an intermediate layer lower in carbon content, and richer in silicon oxide, than the overlying porous low K film. This adhesion layer can be formed utilizing one of a number of techniques, alone or in combination. In one approach, the adhesion layer can be formed by introduction of a rich oxidizing gas such as O2/CO2/etc. to oxidize Si precursors immediately prior to deposition of the low K material. In another approach, thermally labile chemicals such as alpha-terpinene, cymene, and any other non-oxygen containing organics are removed prior to low K film deposition. In yet another approach, the hardware or processing parameters, such as the manner of introduction of the non-silicon containing component, may be modified to enable formation of an oxide interface prior to low K film deposition.Type: GrantFiled: January 28, 2005Date of Patent: June 16, 2009Assignee: Applied Materials, Inc.Inventors: Francimar Schmitt, Alexandros T. Demos, Derek R. Witty, Hichem M'Sadd, Sang H. Ahn, Lester A. D'Cruz, Khaled A. Elsheref, Zhenjiang Cui
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Publication number: 20090142899Abstract: A method of forming an interfacial layer for hafnium-based high-k/metal gate transistors comprises depositing a hafnium-based high-k dielectric layer on a semiconductor substrate and then annealing the high-k dielectric layer and the semiconductor substrate in a nitric oxide atmosphere for a time duration and at a temperature sufficient to drive at least a portion of the nitric oxide through the dielectric layer to an interface between the dielectric layer and the substrate. At this interface, the nitric oxide reacts with the substrate to form a silicon oxynitride interfacial layer.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Jacob M. Jensen, Huicheng Chang
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Patent number: 7541295Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and forminType: GrantFiled: October 30, 2006Date of Patent: June 2, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akiko Nomachi, Hideaki Harakawa
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Patent number: 7541246Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.Type: GrantFiled: August 11, 2006Date of Patent: June 2, 2009Assignee: Fujitsu LimitedInventors: Yasuyuki Tamura, Takaoki Sasaki
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Patent number: 7534729Abstract: Compositions and methods are provided herein that include modifications to at least one surface of a silicon-based semiconductor material. Modifications occur in a liquid and comprise alterations of surface states, passivation, cleaning and/or etching of the surface, thereby providing an improved surface to the semiconductor material. Modifications of surface states include reduction or elimination of an electrically active state of the surface, wherein, at the atomic level, the surface binding characteristics are changed. Passivation includes the termination of dangling bonds on the surface of the semiconductor material.Type: GrantFiled: August 21, 2006Date of Patent: May 19, 2009Assignee: Board of Regents, The University of Texas SystemInventors: Meng Tao, Muhammad Y. Ali
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Patent number: 7531427Abstract: The invention concerns a method for oxidizing a surface region of a SiGe layer that includes an oxidizing thermal treatment of the SiGe layer for oxidizing the surface region. The method includes two phases—a first phase of oxidizing thermal treatment, carried out directly on the SiGe layer, so as to obtain an oxidized region which is thick enough for forming a capping oxide which can protect the underlying SiGe from pitting during the subsequent second phase, but thin enough for keeping the thickness of the oxidized surface region under a threshold thickness range, corresponding to the generation of dislocations within the SiGe layer; and—a second phase of high temperature annealing in an inert atmosphere which is carried out on the SiGe layer after the first phase. The SiGe layer is capped with the oxidized region created during the first phase, and the high temperature annealing allows the diffusion of Ge from a Ge-enriched region into the underlying part of the SiGe layer.Type: GrantFiled: July 5, 2007Date of Patent: May 12, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Nicolas Daval
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Publication number: 20090117750Abstract: The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 ?.Type: ApplicationFiled: October 30, 2008Publication date: May 7, 2009Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)Inventors: Hui OuYang, Jean-Luc Everaert, Laura Nyns, Rita Vos
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Publication number: 20090102027Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.Type: ApplicationFiled: October 1, 2008Publication date: April 23, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi TORIUMI, Noriyoshi SUZUKI
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Patent number: 7521325Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: GrantFiled: July 28, 2005Date of Patent: April 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Patent number: 7521375Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.Type: GrantFiled: October 5, 2007Date of Patent: April 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
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Patent number: 7507676Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas, and a third process gas containing a carbon hydride gas. This method includes repeatedly performing supply of the first process gas to the process field, supply of the second process gas to the process field, and supply of the third process gas to the process field. The supply of the third process gas includes an excitation period of supplying the third process gas to the process field while exciting the third process gas by an exciting mechanism.Type: GrantFiled: January 16, 2007Date of Patent: March 24, 2009Assignee: Tokyo Electron LimitedInventors: Pao-Hwa Chou, Kazuhide Hasebe
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Patent number: 7501352Abstract: The present invention generally provides a method for preparing an oxynitride film on a substrate. A surface of the substrate is exposed to oxygen radicals formed by ultraviolet (UV) radiation induced dissociation of a first process gas comprising at least one molecular composition comprising oxygen to form an oxide film on the surface. The oxide film is exposed to nitrogen radicals formed by plasma induced dissociation of a second process gas comprising at least one molecular composition comprising nitrogen using plasma based on microwave irradiation via a plane antenna member having a plurality of slits to nitridate the oxide film and form the oxynitride film.Type: GrantFiled: March 30, 2005Date of Patent: March 10, 2009Assignees: Tokyo Electron, Ltd., International Business Machines Corporation (“IBM”)Inventors: Masanobu Igeta, Cory Wajda, David L. O'Meara, Kristen Scheer, Toshihara Eurakawa
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Publication number: 20090039406Abstract: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.Type: ApplicationFiled: April 14, 2006Publication date: February 12, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Junichi Kitagawa, Takashi Kobayashi
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Publication number: 20090023299Abstract: Methods for reducing defects on the surface of a silicon oxynitride film are disclosed. In one embodiment, the methods include forming a silicon oxynitride film on a semiconductor substrate and heating the silicon oxynitride film to increase a hydrophilicity of a surface of the silicon oxynitride film prior to treating the surface of the silicon oxynitride film with a hydrofluoric acid.Type: ApplicationFiled: December 20, 2007Publication date: January 22, 2009Inventor: Noriyuki Yokonaga
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Patent number: 7476627Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.Type: GrantFiled: May 9, 2006Date of Patent: January 13, 2009Assignee: ASM America, Inc.Inventors: Christophe F. Pomarede, Jeff Roberts, Eric J. Shero
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Publication number: 20090011611Abstract: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.Type: ApplicationFiled: May 30, 2008Publication date: January 8, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Mitsuhiro ICHIJO, Tetsuhiro TANAKA, Takashi OHTSUKI, Seiji YASUMOTO, Kenichi OKAZAKI, Shunpei YAMAZAKI, Naoya SAKAMOTO
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Patent number: 7470583Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.Type: GrantFiled: February 21, 2006Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventor: Ronald A. Weimer
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Patent number: 7459390Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region.Type: GrantFiled: March 20, 2006Date of Patent: December 2, 2008Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Reima Tapani Laaksonen
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Patent number: 7446052Abstract: In a process involving the formation of an insulating film on a substrate for an electronic device, the insulating film is formed on the substrate surface by carrying out two or more steps for regulating the characteristic of the insulating film involved in the process under the same operation principle. The formation of an insulating film having a high level of cleanness can be realized by carrying out treatment such as cleaning, oxidation, nitriding, and a film thickness reduction while avoiding exposure to the air. Further, carrying out various steps regarding the formation of an insulating film under the same operation principle can realize simplification of the form of an apparatus and can form an insulating film having excellent property with a high efficiency.Type: GrantFiled: March 31, 2003Date of Patent: November 4, 2008Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasakii, Seiji Matsuyama
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Patent number: 7432216Abstract: The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm?2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm?2 or more.Type: GrantFiled: August 15, 2006Date of Patent: October 7, 2008Assignee: Hitachi, Ltd.Inventors: Yasuhiro Shimamoto, Shinichi Saito, Shimpei Tsujikawa
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Patent number: 7429538Abstract: A method of forming a silicon oxynitride gate dielectric. The method includes incorporating nitrogen into a dielectric film using a plasma nitridation process to form a silicon oxynitride film. The silicon oxynitride film is annealed in a first ambient. The first ambient comprises an inert ambient with a first partial pressure of oxygen at a first temperature. The silicon oxynitride film is then annealed in a second ambient comprising a second partial pressure of oxygen at a second temperature. The second partial pressure of oxygen is greater than the first partial pressure of oxygen.Type: GrantFiled: June 27, 2005Date of Patent: September 30, 2008Assignee: Applied Materials, Inc.Inventor: Christopher S. Olsen
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Patent number: 7429369Abstract: A relatively thick electrode is positioned opposite the surface of a substrate/second electrode. The electrode and the substrate surface are both contacted by a solution including silicon nanoparticles. The substrate surface is completely immersed in the solution in a manner such that there is not an air/solution interface and there is no meniscus at the substrate surface. Application of electrical potential between the electrode and the substrate creates a film of silicon nanoparticles on the substrate. Drying of the film induces the film to roll up and form a silicon nanoparticle nanotube material. A film may be subdivided into an array of identical portions, and the identical portions will roll into identical tubes having same length and diameter. A silicon nanoparticle nanotube material of the invention includes nanotubes formed of silicon nanoparticles.Type: GrantFiled: June 9, 2004Date of Patent: September 30, 2008Assignee: The Board of Trustees of the University of IllinoisInventors: Munir H. Nayfeh, Sahraoui Chaieb
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Patent number: 7429539Abstract: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.Type: GrantFiled: December 26, 2006Date of Patent: September 30, 2008Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
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Patent number: 7429540Abstract: A method for processing a semiconductor substrate in a chamber includes forming a silicon oxynitride film using a two-step anneal process. The first anneal step includes annealing the silicon oxynitride film in the presence of an oxidizing gas that has a partial pressure of about 1 to about 100 mTorr, and the second anneal step includes annealing the silicon oxynitride film with oxygen gas that has a flow rate of about 1 slm. The first anneal step is performed at a higher chamber temperature and higher chamber pressure than the second anneal step.Type: GrantFiled: April 3, 2006Date of Patent: September 30, 2008Assignee: Applied Materials, Inc.Inventor: Christopher S. Olsen
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7413998Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present invention.Type: GrantFiled: September 16, 2005Date of Patent: August 19, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
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Patent number: 7410911Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: October 17, 2005Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7402472Abstract: A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.Type: GrantFiled: February 25, 2005Date of Patent: July 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Sangwoo Lim, Paul A. Grudowski, Tien Ying Luo, Olubunmi O. Adetutu, Hsing H. Tseng
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Patent number: 7396776Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: July 10, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 7387972Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.Type: GrantFiled: March 1, 2006Date of Patent: June 17, 2008Assignee: Promos Technologies Pte. Ltd.Inventors: Zhong Dong, Chiliang Chen, Ching-Hwa Chen
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Publication number: 20080138994Abstract: A starting substrate can be appropriately oxidized, while oxidation of the starting substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a starting substrate to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the starting substrate to form a plasma discharge, and processing the starting substrate by the hydrogen plasma.Type: ApplicationFiled: March 14, 2006Publication date: June 12, 2008Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
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Patent number: 7384880Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.Type: GrantFiled: October 12, 2004Date of Patent: June 10, 2008Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Robert S. Chau
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Publication number: 20080128869Abstract: A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer.Type: ApplicationFiled: December 15, 2006Publication date: June 5, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Hok Min Ho, Ching Tien Ma, Woei Ji Song
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Patent number: 7381657Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present inention.Type: GrantFiled: October 1, 2004Date of Patent: June 3, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
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Publication number: 20080124942Abstract: A bi-layer anti-reflective coating for use in photolithographic applications, and specifically, for use in ultraviolet photolithographic processes. The bi-layered anti-reflective coating is used to minimize pattern distortion due to reflections from neighboring features in the construction of microcircuits. The bi-layer anti-reflection coating features a first layer, an absorption layer, disposed on a second layer, a dielectric layer, which is then disposed between a substrate and a photoresist layer. The dielectric/absorption layer comprises one combination selected from Ta/Al2O3, Ta/SiO2, Ta/TiO2, Ta/Ta2O5, Ta/Cr2O3, Ta/Si3N4, Ti/Al2O3, Ti/SiO2, Ti/TiO2, Ti/Ta2O5, Ti/Cr2O3, Ti/Si3N4, Cr/Al2O3, Cr/SiO2, Cr/TiO2, Cr/Ta2O5, Cr/Cr2O3, Cr/Si3N4, Al/Al2O3, Al/TiO2, Al/Ta2O5, Al/Cr2O3, Al/Si3N4, Ni/Al2O3, Ni/SiO2, Ni/TiO2, Ni/Ta2O5, Ni/Cr2O3, Ni/Si3N4, Ir/Al2O3, Ir/SiO2, Ir/TiO2, Ir/Ta2O5, Ir/Cr2O3, and Ir/Si3N4. At least the absorption and dielectric layers can be formed using vacuum deposition.Type: ApplicationFiled: January 24, 2008Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Bernard Kruger, Clinton David Snyder, Patrick Rush Webb, Howard Gordon Zolla
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Patent number: 7378319Abstract: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.Type: GrantFiled: December 29, 2005Date of Patent: May 27, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Soo Ahn