Abstract: A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.

Abstract: To provide a method for the formation of oxide films to form with advantage a high-quality oxide film having excellent uniformity in film thickness and film quality over the entire wafer. The method for the formation of oxide films comprises: the pretreatment process of forming a protective oxide film on the surface of a wafer positioned in a reaction vessel by performing oxidation treatment with radical oxidative species or an atmosphere containing radical oxidative species under depressurized conditions; and the oxide-film-formation process of forming an oxide film on the wafer by performing oxidation treatment at a predetermined temperature under depressurized conditions. The oxide-film-formation process is preferably performed following the pretreatment process in a continuous manner in the reaction vessel in which the pretreatment process is performed.

Abstract: In a mass flow sensor having a layered structure on the upper side of a silicon substrate (1), and having at least one heating element (8) patterned out of a conductive layer in the layered structure, thermal insulation between the heating element (8) and the silicon substrate (1) is achieved by way of a silicon dioxide block (5) which is produced beneath the heating element (8) either in the layered structure on the silicon substrate (1) or in the upper side of the silicon substrate (1). As a result, the sensor can be manufactured by surface micromechanics, i.e. without wafer back-side processes.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: Multi-level structures are formed in a semiconductor substrate by first forming a pattern of lines or structures of different widths. Width information on the pattern is decoded by processing steps into level information to form a MEMS structure. The pattern is etched to form structures having a first floor. The structures are oxidized until structures of thinner width are substantially fully oxidized. A portion of the oxide is then etched to expose the first floor. The first floor is then etched to form a second floor. The oxide is then optionally removed, leaving a multi-level structure. In one embodiment, high aspect ratio comb actuators are formed using the multi-level structure process.

Abstract: A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.

Abstract: A method for oxidizing a nitride film is disclosed, which includes the steps of: providing a nitride film formed on an electrically conductive substrate; irradiating the nitride film with a light beam and getting close to the nitride film with a electrically conductive probe; and exerting a bias between the electrically conductive substrate and the electrically conductive probe. The method can oxidize the nitrides quickly and reduce the cost building a nano-structure in the nitride film. An apparatus for oxidizing a nitride film is also disclosed herewith.

Abstract: Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.

Abstract: Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.

Abstract: This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the dielectric layer. A patterned masking layer with an opening is formed overlying the polysilicon layer. Through the opening, the polysilicon layer is oxidized to form a first silicon oxide layer at the bottom of the opening. Thereafter the masking layer is removed and the polysilicon layer is exposed. The exposed polysilicon layer is then etched through using the first silicon oxide layer as a mask to form MOS floating gates. The first silicon oxide layer is then removed. A second conductor layer is then deposited overlying the MOS floating gates for forming control gates.

Abstract: A method for forming strain-relaxed SiGe films comprises depositing a graded strained SiGe layer on a substrate in which the concentration of Ge is greater at the interface with the substrate than at the top of the layer. The strained SiGe film is subsequently oxidized, producing a strain-relaxed SiGe film with a substantially uniform Ge concentration across the thickness of the film. The relaxed SiGe layer may be used to form a strained silicon layer on a substrate.

Abstract: A method of making a semiconductor device having a silicon dioxide based gate with improved dielectric properties including providing a silicon based substrate having active areas defined therein. Thermally growing a silicon dioxide based gate from the silicon based substrate. Nitriding the silicon dioxide based gate to provide a nitrided silicon dioxide based gate and to increase the dielectric constant of the silicon dioxide based gate without substantially increasing thickness of the silicon dioxide based gate.

Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.

Abstract: Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.

Abstract: A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density.

Abstract: This invention provides a steam oxidation method of a matter to be oxidized with proper controllability and reproducibility. It is provided a steam oxidation method, where a semiconductor substrate (a matter to be oxidized) is housed in a steam oxidation reactor and is subjected to: a first step of supplying N2 gas to the reactor housing the semiconductor substrate and substituting the inside of the reactor with N2 gas; a second step of stopping supply of the N2 gas and supplying a steam-accompanied N2 gas, in which the N2 gas is accompanied with steam, to the reactor; a third step of increasing a temperature of the semiconductor substrate to 450° C. (a steam oxidation temperature) while supplying the steam-accompanied N2 gas; and a fourth step of holding the semiconductor substrate for a predetermined time at 450° C.

Abstract: A method for treatment of the surface of a CdZnTe (CZT) crystal that provides a native dielectric coating to reduce surface leakage currents and thereby, improve the resolution of instruments incorporating detectors using CZT crystals. A two step process is disclosed, etching the surface of a CZT crystal with a solution of the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, passivating the CZT crystal surface with a solution of 10 w/o NH4F and 10 w/o H2O2 in water.

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

Abstract: The method for manufacturing a shallow trench isolation (STI) in a semiconductor device with an enhanced gap-fill property and without a detrimental effect of fluorine by introducing a two-stage thermal process. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming a trench structure in the semiconductor substrate; forming a hydrogen (H2)-based high density plasma (HDP) oxide layer over a first resultant structure; forming a nitrogen trifluoride (NF3)-based HDP oxide layer into the trench structure with a predetermined depth; carrying out a two-stage thermal process for removing fluorine in the NF3-based HDP oxide layer; and forming a helium (He)-based HDP oxide layer over a second resultant structure.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract: A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high-k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.

Abstract: A method of forming a contact opening is provided. First, a substrate having a plurality of conductive structures formed thereon is provided. An ion implantation is performed. Thereafter, a thermal treatment is carried out to form a liner layer on the sidewall of the conductive structure and the exposed substrate. The liner layer on the sidewall of the conductive structure has a thickness smaller than the liner layer on the substrate surface. A spacer is formed on each side of the conductive structure and then an insulation layer is formed over the substrate. The insulation layer is patterned to form a contact opening between two neighboring conductive structures. Since the liner layer on the sidewall of the conductive structures is already quite thin, there is no need to reduce thickness through an etching operation and uniformity of the liner layer on the substrate can be ensured.

Abstract: A manufacturing method for a semiconductor integrated circuit device comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.

Abstract: In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an in-oxidiz-able gas atmosphere, a silicon nitride layer (14) segregates out at the interface of the silicon substrate (10) and the silicon oxide film (13). After this, the unnecessary silicon oxide film (13) on the silicon nitride layer (14) is removed, and a silicon oxide layer (15) is formed beneath the exposed silicon nitride layer (14) with oxygen passing through the exposed silicon nitride layer (14). Whereby, a gate electrode (16) is formed on the gate insulating film consisting of the silicon nitride layer (14) and the silicon oxide layer (15).

Abstract: The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N2O which redistributes the incorporated species to produce a uniform nitrogen concentration.

Abstract: A method of manufacturing an element having a microstructure of an excellent grating groove pattern or the like is obtained. This method of manufacturing an element having a microstructure comprises steps of forming a metal layer on a substrate, forming a dot column of concave portions on the surface of the metal layer and anodically oxidizing the surface of the metal layer formed with the dot column of concave portions while opposing this surface to a cathode surface thereby forming a metal oxide film having a grating groove pattern. When the interval between the concave portions of the dot column is reduced, therefore, a linear grating groove pattern having a large depth with a uniform groove width along the depth direction is easily formed in a self-organized manner.

Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 ?m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

Abstract: To provide a method for manufacturing a magnetic recording medium which creates anodically oxidized aluminum nanoholes so as to have a rectangular or elliptical sectional shape and gives shape anisotropy to a magnetic material filled in the nanoholes to thereby always fix a relative positional relation between magnetizations of the magnetic material and a magnetic head that detects the magnetizations. The method for manufacturing a magnetic recording medium includes: preparing a member having regularly arranged plural pits; subjecting the member to anodic oxidation treatment so that formation of holes is started with the pits as starting points, and a porous region, which has a first portion where the holes are formed without branching and a second portion where branched holes are formed, is formed; filling a magnetic material in the formed holes; and removing the non-branching portions of the holes.

Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.

Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes: a semiconductor substrate; a patterned floating gate formed on the semiconductor substrate, the patterned floating gate having upper and side parts and corners; and a dielectric layer containing a first oxide layer, a nitride layer and a second oxide layer deposited over the semiconductor substrate and the floating gate. The ratio of the thickness of the first oxide layer in the upper and side parts of the patterned floating gate to the thickness of the first oxide layer in the corners of the patterned floating gate does not exceed 1.4. The semiconductor device has an improved coupling coefficient, and reduced leakage current.

Abstract: A method for adjusting the thickness of a thin semiconductor material layer. The method includes measuring the layer to establish a thickness profile, determining thickness adjustment specifications from the measured thickness profile, and adjusting the thickness of the layer in accordance with the specifications by sacrificial oxidation. An apparatus for adjusting the thickness of a thin layer of semiconductor material according to this method is also disclosed.

Abstract: A method of forming an interlayer insulation film on a semiconductor substrate using plasma CVD includes introducing a source gas into a reaction chamber, applying radio-frequency power after the source gas is brought in, introducing an oxidizing gas with or without an additive gas into the reaction chamber after the completion of supplying the source gas and applying the radio-frequency power, and applying the radio-frequency power again. The concentration of the oxidizing gas may be 0.3% or higher and a processing time period by the oxidizing gas may be three seconds or longer.

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract: A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to oxidizing conditions. In addition, the method may include comparing thickness measurements of total dielectric above the underlying layer taken before and after exposing the topography to oxidizing conditions . In some cases, the comparison may include plotting pre-oxidation thickness measurements versus post-oxidation measurements. In other embodiments, the comparison may include determining differences between the pre-oxidation and post-oxidation thickness measurements and correlating the differences to concentrations of the impurity. In some cases, such a correlation may include subtracting a concentration of the impurity at a first location along the semiconductor topography from a concentration of the impurity at a second location along the semiconductor topography.

Abstract: A semiconductor device is produced by forming a gate oxide film on a silicon substrate, forming a gate electrode on the gate oxide film, forming a nitrogen-containing oxide film on the silicon substrate and gate electrode in an N2O gas or an NO gas, forming a BPSG film on the nitrogen-containing oxide film, and carrying out a reflow process on the BPSG film in a water vapor atmosphere. During the reflow process, the nitrogen-containing oxide film that has no hydrogen atoms prevents the penetration and diffusion of oxygen and hydrogen atoms into the silicon substrate and gate electrode, thereby preventing the oxidization of the silicon substrate and gate electrode. No hydrogen atoms diffuse into the gate oxide film, and therefore, the reliability of the gate oxide film is secured.