Oxidation Patents (Class 438/770)
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Publication number: 20080268654Abstract: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a supplying unit of an oxidative gas being provided at one end of the processing container, a plurality of supplying units of a reducing gas being provided at a plurality of positions in a longitudinal direction of the processing container; an atmosphere forming step of supplying the oxidative gas and the reducing gas into the processing container in order to form an atmosphere having active oxygen species and active hydroxyl species in the processing container; and an oxidizing step of oxidizing surfaces of the plurality of objects to be processed in the atmosphere.Type: ApplicationFiled: June 24, 2008Publication date: October 30, 2008Inventors: Keisuke Suzuki, Toshiyuki Ikouchi, Kota Umezawa
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Patent number: 7442571Abstract: Provided are a semiconductor probe having a resistive tip, a method of fabricating the semiconductor probe, and a method of recording and reproducing information using the semiconductor probe. The semiconductor probe includes a tip and a cantilever. The tip is doped with first impurities. The cantilever has an end portion on which the tip is positioned. The tip includes a resistive area, and first and second semiconductor electrode areas. The resistive area is positioned at the peak of the tip and lightly doped with second impurities that are different from the first impurities. The first and second semiconductor electrode areas are heavily doped with the second impurities and contact the resistive area.Type: GrantFiled: September 27, 2006Date of Patent: October 28, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sik Park, Hyun-Jung Shin, Ju-Hwan Jung
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Patent number: 7442655Abstract: The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The substrate has first and second different oxidizable materials. The substrate is therein exposed to a gas mixture comprising an oxidizer and a reducer under conditions effective to selectively grow an oxide layer on the first material relative to the second material. The oxidizer oxidizes the first and second materials under the conditions. The reducer reduces oxidized second material under the conditions back to the second material. After selectively growing the oxide layer on the first material relative to the second material, partial pressure of the oxidizer and the reducer is reduced within the chamber by flowing an inert gas to the chamber while chamber pressure and chamber temperature are at or above those of the conditions during the exposing. Other aspects and implementations are contemplated.Type: GrantFiled: July 18, 2006Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventor: Don Carl Powell
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Patent number: 7439165Abstract: A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer.Type: GrantFiled: April 6, 2005Date of Patent: October 21, 2008Assignee: Agency for Sceince, Technology and ReasearchInventors: Patrick Guo Oiang Lo, Lakshmi Kanta Bera, Wei Yip Loh, Balakumar Subramanian, Narayanan Balasubramanian
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Patent number: 7435691Abstract: A micromechanical component having a silicon substrate; a cavity provided in the substrate; and a diaphragm, provided on the surface of the substrate, which closes the cavity; the diaphragm featuring a silicon-oxide layer having an opening that is formed by silicon-oxide wedges pointing to each other; and the diaphragm having at least one closing layer which closes the opening. Also, a suitable manufacturing method.Type: GrantFiled: September 7, 2005Date of Patent: October 14, 2008Assignee: Robert Bosch GmbHInventor: Heribert Weber
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Patent number: 7435690Abstract: Method of preparing a silicon dioxide layer by high-temperature oxidation on a substrate of formula Si1-xGex in which x is greater than 0 and less than or equal to 1, the said method comprising the following successive steps: a) at least one additional layer of thickness hy and of overall formula Si1-yGey, in which y is greater than 0 and less than x, is deposited on the said substrate of formula Si1-xGex; and b) the high-temperature oxidation of the said additional layer of overall formula Si1-yGey is carried out, whereby the said additional layer is completely or partly converted into a layer of silicon oxide SiO2. Method of preparing an optical or electronic component, comprising at least one step for preparing an SiO2 layer using the method described above.Type: GrantFiled: March 25, 2005Date of Patent: October 14, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Pierre Mur
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Patent number: 7429539Abstract: A substrate processing method comprises the step of forming an oxide film on a silicon substrate surface, and introducing nitrogen atoms into the oxide film by exposing the oxide film to nitrogen radicals excited in plasma formed by a microwave introduced via a planar antenna.Type: GrantFiled: December 26, 2006Date of Patent: September 30, 2008Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
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Publication number: 20080224145Abstract: A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.Type: ApplicationFiled: October 11, 2007Publication date: September 18, 2008Applicants: TOKYO ELECTRON LIMITEDInventors: Tadahiro Ohmi, Shigetoshi Sugawa, Katsuyuki Sekine, Yuji Saito
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Patent number: 7425480Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.Type: GrantFiled: April 23, 2007Date of Patent: September 16, 2008Assignee: Kabushiki Kaisha TohisbaInventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Publication number: 20080200038Abstract: A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing gas and a deoxidizing gas to the process field while heating the process field, thereby causing the oxidizing gas and the deoxidizing gas to react with each other to generate oxygen radicals and hydroxyl group radicals, and performing oxidation on the process object layer of the target substrates by use of the oxygen radicals and the hydroxyl group radicals. Then, the method includes heating the process object layer processed by the oxidation, within an atmosphere of an annealing gas containing ozone or oxidizing radicals, thereby performing annealing on the process object layer.Type: ApplicationFiled: February 6, 2008Publication date: August 21, 2008Inventors: Toshiyuki Ikeuchi, Kota Umezawa, Tetsuya Shibata
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Patent number: 7410910Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. The lanthanum aluminum oxynitride film may be formed by atomic layer deposition.Type: GrantFiled: August 31, 2005Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7410911Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: October 17, 2005Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Publication number: 20080188089Abstract: A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.Type: ApplicationFiled: February 6, 2007Publication date: August 7, 2008Applicant: International Business Machines CorporationInventors: Anthony I. Chou, Sadanand V. Deshpande, Renee T. Mo, Shreesh Narasimha, Katsunori Onishi, Dominic Schepis
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Publication number: 20080179714Abstract: A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.Type: ApplicationFiled: January 25, 2007Publication date: July 31, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Renee T. Mo, Shreesh Narasimha
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Publication number: 20080176411Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Applicant: International Business Machines CorporationInventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20080176381Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.Type: ApplicationFiled: July 13, 2007Publication date: July 24, 2008Applicant: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Bernard Aspar, Chrystelle Lagahe Blanchard, Nicolas Sousbie
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Patent number: 7396729Abstract: A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is thicker on the beveled surfaces of the trench than on other surfaces of the trench.Type: GrantFiled: August 31, 2005Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Chul Jeong, Wook-Hyoung Lee
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Patent number: 7387972Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.Type: GrantFiled: March 1, 2006Date of Patent: June 17, 2008Assignee: Promos Technologies Pte. Ltd.Inventors: Zhong Dong, Chiliang Chen, Ching-Hwa Chen
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Publication number: 20080132083Abstract: A method is provided for using a film formation apparatus including a process container having an inner surface, which contains as a main component a material selected from the group consisting of quartz and silicon carbide. The method includes performing a film formation process to form a silicon nitride film on a product target substrate inside the process container, and then, unloading the product target substrate from the process container. Thereafter, the method includes supplying an oxidizing gas into the process container with no product target substrate accommodated therein, thereby performing an oxidation process to change by-product films deposited on the inner surface of the process container into a composition richer in oxygen than nitrogen, at a part of the by-product films from a surface thereof to a predetermined depth.Type: ApplicationFiled: November 27, 2007Publication date: June 5, 2008Inventor: Hiroyuki Matsuura
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Publication number: 20080132045Abstract: A metallic, semiconductor, dielectric or oxide layer, such as a thin gate oxide, is formed by supplying a wafer in a processing chamber with thermal energy to heat the wafer and light energy, such as laser light at a selected wavelength, to improve the quality of the resulting layer. The laser light may be focused and/or scanned to control the depth and spatial extent of laser processing.Type: ApplicationFiled: April 27, 2007Publication date: June 5, 2008Inventor: Woo Sik Yoo
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Patent number: 7381657Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present inention.Type: GrantFiled: October 1, 2004Date of Patent: June 3, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
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Patent number: 7381658Abstract: This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.Type: GrantFiled: July 5, 2005Date of Patent: June 3, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Peter Mardilovich, Pavel Komilovich, Randy Hoffman
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Patent number: 7381620Abstract: A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.Type: GrantFiled: March 9, 2006Date of Patent: June 3, 2008Assignee: Spansion LLCInventors: Boon-Yong Ang, Hidehiko Shiraiwa, Simon S. Chan, Harpreet K. Sachar, Mark Randolph
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Patent number: 7378319Abstract: A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.Type: GrantFiled: December 29, 2005Date of Patent: May 27, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Yong Soo Ahn
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Patent number: 7371630Abstract: Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.Type: GrantFiled: September 24, 2004Date of Patent: May 13, 2008Assignee: Intel CorporationInventors: Gilroy J. Vandentop, Rajashree Baskaran
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Patent number: 7368400Abstract: The present invention relates to a method for forming an oxide film in semiconductor devices. According to the present invention, after an oxide film is formed, interface trap charge and oxide trap charge can be reduced through a high-temperature thermal treatment process and a pre-treatment thermal process. Further, as an oxide film of a high quality whose trap charge is reduced is formed, reliability of a device is improved and variation in the threshold voltage is prevented.Type: GrantFiled: December 9, 2004Date of Patent: May 6, 2008Assignees: Hynix Semiconductor Inc., STMicroelectronics S.r.l.Inventor: Seung Woo Shin
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Patent number: 7365028Abstract: The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing material and/or at least one semimetal-and-halogen-containing material over a semiconductor substrate surface. The material can be subjected to aminolysis followed by oxidation to convert the material to metal oxide and/or semimetal oxide. The aminolysis and oxidation can be separate ALD steps relative to one another, or can be conducted in a reaction chamber in a common processing step.Type: GrantFiled: September 23, 2005Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Publication number: 20080095678Abstract: An oxidation apparatus for a semiconductor process includes a gas supply system configured to supply an oxidizing gas and a deoxidizing gas to the process field of a process container through a gas supply port disposed adjacent to target substrates on one side of the process field. The gas supply port includes a plurality of gas spouting holes arrayed over a length corresponding to the process field in a vertical direction. A heater is disposed around the process container and configured to heat the process field. A control section is preset to perform control such that the oxidizing gas and the deoxidizing gas are caused to react with each other, thereby generating oxygen radicals and hydroxyl group radicals within the process field, and an oxidation process is performed on the surfaces of the target substrate by use of the oxygen radicals and the hydroxyl group radicals.Type: ApplicationFiled: October 18, 2007Publication date: April 24, 2008Inventors: Kazuhide Hasebe, Takehiko Fujita, Shigeru Nakajima, Jun Ogawa
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Patent number: 7358171Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.Type: GrantFiled: August 30, 2001Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Don Carl Powell
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Patent number: 7351668Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a carbon hydride gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field while stopping supply of the second process gas to the process field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field. The fourth step stops supply of the first to third process gases to the field.Type: GrantFiled: March 7, 2006Date of Patent: April 1, 2008Assignee: Tokyo Electron LimitedInventors: Pao-Hwa Chou, Kazuhide Hasebe
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Patent number: 7338850Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.Type: GrantFiled: November 30, 2004Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventor: Sang Don Lee
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Publication number: 20080050918Abstract: The disclosure relates to a method for producing a microelectronic device comprising one or more Si1-zGez-based semiconductor wire(s) (with 0<z?1), including the steps of: a) thermal oxidation of at least a portion of a Si1-xGex-based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si1-yGey-based semiconductor zone (with 0<y<1 and x<y), b) lateral thermal oxidation of the sides of the second Si1-yGey-based semiconductor zone so as to reduce the second zone in at least one direction parallel to the main plane of the support and to form one or more Si1-zGez-based semiconductor wire(s) (with 0<y<1 and y<z).Type: ApplicationFiled: August 2, 2007Publication date: February 28, 2008Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventor: Jean-Francois Damlencourt
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Patent number: 7335606Abstract: A NiSi layer over silicon that is thermally stable and can form even in the presence of oxides. The method of fabricating the nickel silicide layer includes providing a substrate comprising silicon, depositing a layer of at least a 3-component metal alloy comprising nickel on a surface of the substrate, and annealing the alloy and the substrate. The annealing temperature is less than 1000° C. The 3-component metal alloy can include Ni, Ti and Pt.Type: GrantFiled: March 15, 2004Date of Patent: February 26, 2008Assignee: Agency for Science, Technology and ResearchInventors: Dongzhi Chi, Tek Po Rinus, Soo Jin Chua
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Publication number: 20080032510Abstract: A method of forming a layer comprising silicon and nitrogen on a substrate is provided. The layer may also include oxygen and be used as a silicon oxynitride gate dielectric layer. In one aspect, forming the layer includes exposing a silicon substrate to a plasma of nitrogen and a noble gas to incorporate nitrogen into an upper surface of the substrate, wherein the noble gas is argon, neon, krypton, or xenon. The layer is annealed and then exposed to a plasma of nitrogen to incorporate more nitrogen into the layer. The layer is then further annealed.Type: ApplicationFiled: June 17, 2007Publication date: February 7, 2008Inventor: Christopher Olsen
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Publication number: 20080003750Abstract: A method of manufacturing a non-volatile memory device includes providing a floating gate layer over a semiconductor substrate. The floating gate layer and the semiconductor substrate are etched to form a trench. An isolation structure is formed in the trench. An upper portion of the isolation structure is etched, wherein an upper sidewall of the floating gate layer is exposed by the etching of the upper portion of the isolation structure. An oxide layer is formed on the floating gate layer to round an upper corner of the floating gate layer. A control gate layer is formed over the floating gate layer.Type: ApplicationFiled: December 12, 2006Publication date: January 3, 2008Applicant: Hynix Semiconductor Inc.Inventors: Jum Soo Kim, Hee Hyun Chang
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Publication number: 20080003783Abstract: A method of smoothening a surface of a semiconductor structure comprises exposing the surface of the semiconductor structure to a reactant. A chemical reaction between a material of the semiconductor structure and the reactant is performed. In the chemical reaction, a layer of a reaction product is formed on at least a portion of the surface of the semiconductor structure. The layer of the reaction product is selectively and completely removed.Type: ApplicationFiled: January 18, 2007Publication date: January 3, 2008Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
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Patent number: 7312139Abstract: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.Type: GrantFiled: January 3, 2005Date of Patent: December 25, 2007Assignee: United Microelectronics Corp.Inventors: Yu-Ren Wang, Ying-Wei Yen, Michael Chan
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Patent number: 7307026Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.Type: GrantFiled: February 25, 2004Date of Patent: December 11, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Christof Streck, Guido Koerner, Thorsten Kammler
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Patent number: 7304002Abstract: A method for oxidation of an object to be processed is provided wherein an oxide film can provide favorable film quality and a laminate structure of nitride film and oxide film can be obtained by a thermal oxidation of a nitride film. In a method for oxidation of a surface of an object to be processed in a single processing container 8 which can contain a plurality of objects to be processed, at least a nitride film is exposed on said surface, and said oxidation is performed by mainly using active hydroxyl/oxygen species in a vacuum atmosphere, setting a processing pressure to 133 Pa or below, and setting a processing temperature to 400° C. or above. Under these conditions, high interplanar uniformity is maintained and oxide films with favorable film quality are obtained by oxidizing nitride films on the surfaces of a plurality of objects to be processed.Type: GrantFiled: July 7, 2003Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Tatsuo Nishita, Tsukasa Yonekawa, Keisuke Suzuki, Toru Sato
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Patent number: 7303946Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.Type: GrantFiled: April 27, 2000Date of Patent: December 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
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Patent number: 7304003Abstract: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a main supplying unit of an oxidative gas and a supplying unit of a reducing gas being provided at one end of the processing container, a sub supplying unit of the oxidative gas being provided on a way in a longitudinal direction of the processing container; an atmosphere forming step of supplying the oxidative gas and the reducing gas into the processing container in order to form an atmosphere having active oxygen species and active hydroxyl species in the processing container; and an oxidizing step of oxidizing surfaces of the plurality of objects to be processed in the atmosphere.Type: GrantFiled: March 23, 2005Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kimiya Aoki
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Patent number: 7300847Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.Type: GrantFiled: December 27, 2005Date of Patent: November 27, 2007Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
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Publication number: 20070264842Abstract: A thin-film deposition method for a semiconductor device includes injecting a process gas into a process chamber to deposit a thin film and forming a plasma atmosphere inside the process chamber while injecting the process gas to deposit a thin film on a semiconductor substrate. The thin film is formed by a reaction between the process gas and the plasma.Type: ApplicationFiled: October 17, 2006Publication date: November 15, 2007Applicant: Samsung Electronics Co., Ltd.Inventor: Yong-Geun Kim
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Patent number: 7291566Abstract: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to erosion by the plasma, and a bonding layer that improves the adhesion of the protective layer to the processing element to mitigate possible process contamination by failure of the protective layer.Type: GrantFiled: March 18, 2004Date of Patent: November 6, 2007Assignee: Tokyo Electron LimitedInventors: Gary Escher, Mark A. Allen
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Patent number: 7288490Abstract: Method and system for fabricating an array of two or more carbon nanotube (CNT) structures on a coated substrate surface, the structures having substantially the same orientation with respect to a substrate surface. A single electrode, having an associated voltage source with a selected voltage, is connected to a substrate surface after the substrate is coated and before growth of the CNT structures, for a selected voltage application time interval. The CNT structures are then grown on a coated substrate surface with the desired orientation. Optionally, the electrode can be disconnected before the CNT structures are grown.Type: GrantFiled: December 7, 2004Date of Patent: October 30, 2007Assignee: United States of America as Represented by the Administrator of the National Aeronautics and Space Administration (NASA)Inventor: Lance D. Delzeit
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Patent number: 7282457Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: March 2, 2001Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7282131Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7279435Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: September 2, 2004Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: Daniel F. Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7273819Abstract: Substrates in a reaction chamber are sequentially exposed to at least three gas atmospheres: a first atmosphere of a first purge gas, a second atmosphere of a process gas and a third atmosphere of a second purge gas. The gases are introduced into the reaction chamber from one end of the chamber and exit from the opposite end. Successive gases entering the chamber are selected so that a stable interface with the immediately preceding gas can be maintained. For example, when the gases are fed into the chamber at the chamber's top end and are exhausted at the bottom end, the gases are chosen with successively lower molecular weights. In effect, each gas atmosphere stays on top of and pushes the previous gas atmosphere out of the chamber from the top down. Advantageously, the gases can be more effectively and completely removed from the chamber.Type: GrantFiled: February 1, 2005Date of Patent: September 25, 2007Assignee: ASM International N.V.Inventors: Theodorus G. M. Oosterlaken, Frank Huussen, Menso Hendriks