Oxidation Patents (Class 438/770)
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Patent number: 7611579Abstract: A system for synthesizing nanostructures using chemical vapor deposition (CVD) is provided. The system includes a housing, a porous substrate within the housing, and on a downstream surface of the substrate, a plurality of catalyst particles from which nanostructures can be synthesized upon interaction with a reaction gas moving through the porous substrate. Electrodes may be provided to generate an electric field to support the nanostructures during growth. A method for synthesizing extended length nanostructures is also provided. The nanostructures are useful as heat conductors, heat sinks, windings for electric motors, solenoid, transformers, for making fabric, protective armor, as well as other applications.Type: GrantFiled: January 14, 2005Date of Patent: November 3, 2009Assignee: Nanocomp Technologies, Inc.Inventors: David Lashmore, Joseph J. Brown, Robert C. Dean, Jr., Peter L. Antoinette
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Patent number: 7605095Abstract: A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing gas and a deoxidizing gas to the process field while heating the process field, thereby causing the oxidizing gas and the deoxidizing gas to react with each other to generate oxygen radicals and hydroxyl group radicals, and performing oxidation on the process object layer of the target substrates by use of the oxygen radicals and the hydroxyl group radicals. Then, the method includes heating the process object layer processed by the oxidation, within an atmosphere of an annealing gas containing ozone or oxidizing radicals, thereby performing annealing on the process object layer.Type: GrantFiled: February 6, 2008Date of Patent: October 20, 2009Assignee: Tokyo Electron LimitedInventors: Toshiyuki Ikeuchi, Kota Umezawa, Tetsuya Shibata
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Patent number: 7598140Abstract: A semiconductor device having excellent characteristics is provided without deteriorated film quality. A first oxide film is divided into three regions A, B and C. Lengths I, II and III of the regions A, B and C in a plane direction of the silicon substrate are set equal to each other. In the first oxide film, a thermal treatment is carried out such that the film thicknesses of the regions A and C are increased. The thermal treating time, the thermal treating temperature and other parameters are adjusted such that sectional areas of the regions A and C become 1.5 times of a sectional area of the region B, while a film thickness of the region B is maintained.Type: GrantFiled: September 29, 2005Date of Patent: October 6, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Yuki Saito, Yasutaka Kobayashi
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Patent number: 7598145Abstract: A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0<y?1) that have different respective Germanium contents.Type: GrantFiled: June 11, 2007Date of Patent: October 6, 2009Assignees: Commissariat a l 'Energie Atomique, STMicroelectronics SAInventors: Jean-Francois Damlencourt, Yves Morand, Laurent Clavelier
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Publication number: 20090239387Abstract: Disclosed is a producing method of a semiconductor device produced by transferring a plurality of substrates into a processing chamber, supplying oxygen-containing gas and hydrogen-containing gas into the processing chamber which is in a heated state to process the plurality of substrates by oxidation, and transferring the plurality of the oxidation-processed substrates out from the processing chamber, wherein the hydrogen-containing gas is supplied from a plurality of locations of a region corresponding to a substrate arrangement region in which the plurality of substrates are arranged in the processing chamber.Type: ApplicationFiled: March 13, 2009Publication date: September 24, 2009Inventors: Takashi OZAKI, Kazuhiro Yuasa, Kiyohiko Maeda
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Publication number: 20090233452Abstract: Disclosed is a producing method of a semiconductor device produced by transferring a plurality of substrates into a processing chamber, supplying oxygen-containing gas and hydrogen-containing gas into the processing chamber to process the plurality of substrates by oxidation, and transferring the plurality of the oxidation-processed substrates out from the processing chamber, wherein in the oxidation-processing, the hydrogen-containing gas is supplied from a plurality of locations of a region which is in proximity to the inner wall of the processing chamber and which corresponds to a substrate arrangement region in which the plurality of substrates are arranged in the processing chamber.Type: ApplicationFiled: March 13, 2009Publication date: September 17, 2009Inventors: Takashi Ozaki, Kazuhiro Yuasa, Kiyohiko Maeda
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Patent number: 7569494Abstract: An apparatus for forming a multicomponent thin film, such as a superconducting thin film, on a substrate includes a holder for holding at least one substrate and a deposition/reaction vessel. The deposition/reaction vessel has at least three zones, each zone being separated from adjacent zones by a wall. The zones include at least two deposition zones, where each deposition zone is configured and arranged to deposit a deposition material on the at least one substrate, and at least one reaction zone for reacting the deposition material with a reactant. The apparatus is configured and arranged to rotate the at least one substrate sequentially through the plurality of zones to form a thin film on the substrate. In some embodiments of the apparatus, the deposition/reaction vessel includes a same number of deposition zones and reaction zones which may be alternating deposition and reaction zones.Type: GrantFiled: November 19, 2002Date of Patent: August 4, 2009Assignee: Conductus, Inc.Inventors: Vladimir Matijasevic, Todd Kaplan
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Patent number: 7569487Abstract: A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing an oxidizing species into the chamber. The method includes treating the upper surface of the semiconductor substrate to remove the one or more carbon bearing species and form a particle film of silicon dioxide overlying the upper surface. The method includes introducing an inert gas into the chamber to purge the chamber of the oxidizing species and other species associated with the one or more carbon bearing species. A reducing species is introduced into the chamber to strip the particle film of silicon dioxide to create a substantially clean surface treated with hydrogen bearing species. The method includes performing another process (e.g.Type: GrantFiled: September 28, 2006Date of Patent: August 4, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Fumitake Mieno
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Publication number: 20090186489Abstract: A thermal treatment apparatus, a method for manufacturing a semiconductor device, and a method for manufacturing a substrate, wherein the occurrence of slip dislocation in a substrate during heat treatment is reduced, and a high-quality semiconductor device can be manufactured, are intended to be provided. A substrate support 30 is formed from a main body portion 56 and a supporting portion 58. In the main body portion 56, a plurality of placing portions 66 extend parallel, and supporting portions 58 are provided on the placing portions 66. A substrate 68 is placed on the supporting portion 58. The supporting portion 58 has a smaller area than an area of a flat face of the substrate, and is formed from a silicon plate having a thickness larger than thickness of the substrate, so that deformation during heat treatment is reduced. The supporting portion 58 is made of silicon, and a layer coated with silicon carbide (SiC) is formed on a substrate-placing face of the supporting portion 58.Type: ApplicationFiled: March 16, 2009Publication date: July 23, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Naoto Nakamura, Iwao Nakamura, Tomoharu Shimada, Kenichi Ishiguro, Sadao Nakashima
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Patent number: 7563697Abstract: Hydrogen gas is ion-implanted into a silicon wafer for active layer via an insulating film, and thus ion-implanted wafer is then bonded with a supporting wafer via an insulating film interposed therebetween. This bonded wafer is heated to 500° C., so that a part of the bonded wafer is cleaved and separated, thereby producing an SOI wafer. Subsequently, thus-obtained SOI wafer is subjected to a heat treatment in an argon gas atmosphere. After that, the SOI wafer is subjected to an oxidation process in an oxidizing atmosphere, and thus formed oxide film is removed using an HF solution. Consequently, the surface of the SOI wafer is recrystallized and thus planarized.Type: GrantFiled: September 3, 2004Date of Patent: July 21, 2009Assignee: Sumco CorporationInventors: Nobuyuki Morimoto, Hideki Nishihata
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Patent number: 7563628Abstract: Disclosed is a method of fabricating an optical waveguide device including the steps of forming a mask over a waveguide core material layer so as to leave a portion of the layer exposed, and exposing the structure to an oxidizing environment to form an oxide layer on the waveguide core material layer at least in the exposed portion thereby defining the lateral dimension of the waveguide core. The resulting waveguide core has extremely smooth surfaces for low optical losses.Type: GrantFiled: November 3, 2005Date of Patent: July 21, 2009Assignee: Lehigh UniversityInventors: Thomas L. Koch, Robert M. Pafchek, Mark A. Webster
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Publication number: 20090179253Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: ApplicationFiled: June 13, 2007Publication date: July 16, 2009Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
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Publication number: 20090176181Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for controlling oxide formation using pressure. The present invention, in one or more implementations, includes a pressure stabilization system to dynamically adjust scavenger pressure in a furnace during wafer fabrication in relation to a pressure formation range, value, or one or more pressure indicators in a wafer fabrication process.Type: ApplicationFiled: November 12, 2007Publication date: July 9, 2009Applicant: MICREL, INC.Inventor: Miles DUDMAN
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Publication number: 20090170340Abstract: A method of forming dielectric films including a metal silicate on a silicon substrate comprises a first step of oxidizing a surface layer portion of the silicon substrate and forming a silicon dioxide film; a second step of irradiating ion on the surface of the silicon dioxide film and making the surface layer portion of the silicon dioxide film into a reaction-accelerating layer with Si—O cohesion cut; a third step of laminating a metal film on the reaction-accelerating layer in a non-oxidizing atmosphere; and a fourth step of oxidizing the metal film and forming a metal silicate film that diffuses a metal from the metal film to the silicon dioxide film.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Hideo Kitagawa, Naomu Kitano
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Publication number: 20090170341Abstract: A process for forming dielectric films containing at least metal atoms, silicon atoms, and oxygen atoms on a silicon substrate comprises a first step of oxidizing a surface portion of the silicon substrate to form a silicon dioxide film; a second step of forming a metal film on the silicon dioxide film in a non-oxidizing atmosphere; a third step of heating in a non-oxidizing atmosphere to diffuse the metal atoms constituting the metal film into the silicon dioxide film; and a fourth step of oxidizing the silicon dioxide film containing the diffused metal atoms to form the film containing the metal atoms, silicon atoms, and oxygen atoms.Type: ApplicationFiled: December 23, 2008Publication date: July 2, 2009Applicant: CANON KABUSHIKI KAISHAInventors: Naomu Kitano, Yusuke Fukuchi, Nobumasa Suzuki, Hideo Kitagawa
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Patent number: 7553704Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).Type: GrantFiled: June 28, 2005Date of Patent: June 30, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
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Publication number: 20090163036Abstract: A substrate processing method includes the step of forming an oxide film by oxidizing a silicon substrate surface and the step of nitriding the oxide film to form an oxynitride film, wherein there is provided a step of purging oxygen after the oxidizing step but before said nitriding step from an ambient in which said nitriding processing is conducted.Type: ApplicationFiled: February 25, 2009Publication date: June 25, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
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Publication number: 20090152629Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Yongjun Jeff Hu, Allen McTeer, Naga Chandrasekaran
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Patent number: 7541297Abstract: A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.Type: GrantFiled: October 22, 2007Date of Patent: June 2, 2009Assignee: Applied Materials, Inc.Inventors: Abhijit Basu Mallick, Jeffrey C. Munro, Linlin Wang, Srinivas D. Nemani, Yi Zheng, Zheng Yuan, Dimitry Lubomirsky, Ellie Y. Yieh
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Patent number: 7541295Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and forminType: GrantFiled: October 30, 2006Date of Patent: June 2, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Akiko Nomachi, Hideaki Harakawa
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Patent number: 7541246Abstract: A gate insulating film and a gate electrode are formed on a silicon substrate. The gate insulating film contains at least hafnium, oxygen, fluorine, and nitrogen. The fluorine concentration is high in the vicinity of an interface with the silicon substrate and progressively decreases with decreasing distance from the gate electrode. The nitrogen concentration is high in the vicinity of an interface with the gate electrode and progressively decreases with decreasing distance from the silicon substrate. The fluorine concentration in the vicinity of the interface with the silicon substrate is preferably 1×1019 cm?3 or more. The nitrogen concentration in the vicinity of the interface with the gate electrode is preferably 1×1020 cm?3 or more.Type: GrantFiled: August 11, 2006Date of Patent: June 2, 2009Assignee: Fujitsu LimitedInventors: Yasuyuki Tamura, Takaoki Sasaki
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Publication number: 20090137131Abstract: In a manufacturing method of a thin film transistor (1), the oxide film forming step is performed whereby: a process-target substrate (2) having a surface on which a gate oxide film (4) should be formed is immersed in an oxidizing solution containing an active oxidizing species; and a gate oxide film (4) is formed through direct oxidation of polycrystalline silicon (51) on the process-target substrate (2). With this step, a silicon dioxide film (42) is formed while growing a silicon dioxide film (41) on the process-target substrate 2. Accordingly, the interface between the polycrystalline silicon (51) and the gate oxide film (4) is kept clean. The gate oxide film (4) is uniformly formed with excellent quality in insulation tolerance and other properties. Therefore, the thin film transistor (1) contains a high quality oxide film with excellent insulation tolerance and other properties which can be formed at low temperature.Type: ApplicationFiled: December 17, 2008Publication date: May 28, 2009Applicants: Sharp Kabushiki Kaisha, Hikaru KobayashiInventors: Shigeki IMAI, Kazuhiko INOGUCHI, Hikaru KOBAYASHI
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Patent number: 7538008Abstract: A layer structure comprising a smoothed interlayer and an overlying layer applied on the interlayer, wherein the interlayer is treated with a gaseous etchant containing hydrogen fluoride, a material removal being obtained thereby and the interlayer being smoothed.Type: GrantFiled: May 3, 2007Date of Patent: May 26, 2009Assignee: Siltronic AGInventors: Diego Feijoo, Guenter Schwab, Thomas Buschhardt
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Patent number: 7534730Abstract: Disclosed is a method for manufacturing a semiconductor device which comprises a step for carrying a plurality of substrates (1) in a process chamber (4), a step for supplying an oxygen-containing gas from the upstream side of the substrates (1) carried in the process chamber (4), a step for supplying a hydrogen-containing gas from at least one location corresponding to a position within the region where substrates (1) are placed in the process chamber (4), a step for oxidizing the substrates (1) by reacting the oxygen-containing gas with the hydrogen-containing gas in the process chamber (4), and a step for carrying the thus-processed substrates (1) out of the process chamber (4).Type: GrantFiled: August 25, 2004Date of Patent: May 19, 2009Assignee: Hitachi Kokusai Electric In.Inventors: Takashi Ozaki, Kazuhiro Yuasa, Kiyohiko Maeda
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Patent number: 7534731Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5 ×10 12 per cc.Type: GrantFiled: March 30, 2007Date of Patent: May 19, 2009Assignee: Tokyo Electron LimitedInventors: Kimberly G. Reid, Anthony Dip
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Patent number: 7531431Abstract: Methods of processing a semiconductor structure including a metal layer in the presence of organic material include flowing an aqueous mixture including an oxidizing agent over the semiconductor structure during processing of the semiconductor structure. Processing the semiconductor structure may include sawing the semiconductor structure and/or scrubbing the semiconductor structure with pressurized water. The oxidizing agent may include a peroxide, such as hydrogen peroxide, or another oxidizing agent.Type: GrantFiled: May 19, 2006Date of Patent: May 12, 2009Assignee: Cree, Inc.Inventors: Barry Rayfield, Chris Fanelli, Mitch Jackson
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Patent number: 7528015Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.Type: GrantFiled: June 28, 2005Date of Patent: May 5, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
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Patent number: 7528041Abstract: A method of manufacturing a semiconductor device, including including preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film having openings over the second active region and the field oxide which adjoins the second active region, over the semiconductor substrate; forming the first gate insulator on the second active region; removing the protective film; forming second gate insulators thinner than the first gate insulators on the first, third and fourth active regions, respectively; forming gate electrodes on the first gate insulator over the first active region and on the second gate insulator over the second active region; and forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.Type: GrantFiled: March 15, 2006Date of Patent: May 5, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Toshihiro Honma
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Patent number: 7524745Abstract: Method and device for doping or diffusion, or oxidation of silicon wafers (4), the wafers being introduced into the chamber (2) of an oven (1) wherein is introduced at least a gas for performing the doping or diffusion or oxidation process. The method comprises simultaneously with the introduction and passage of gas into the chamber (2) of the oven (1), continuously subjecting the latter to a depression of constant value. The device comprises an oven (1) provided with a chamber (2) wherein are introduced the wafers, the oven including at least an inlet tube (5a, 5b, 5c) for introducing at least a gas into the chamber (2) to carry out the processes and at least an outlet tube (6) for extracting the gas whereto is connected a suction unit (7) for generating in the chamber (2) a constant and controlled depression.Type: GrantFiled: May 14, 2002Date of Patent: April 28, 2009Assignee: Semco Engineering SAInventor: Yvon Pellegrin
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Patent number: 7524744Abstract: The present invention provides a method of producing an SOI wafer, comprising at least steps of forming an oxygen ion-implanted layer by implanting oxygen ions into a silicon wafer from one main surface thereof, subjecting the silicon wafer to oxide film-forming heat treatment to convert the oxygen ion-implanted layer into a buried oxide film, and thereby producing an SOI wafer having an SOI layer on the buried oxide film, wherein when the buried oxide film is formed in the silicon wafer, the buried oxide film is formed so that a thickness thereof is thicker than a thickness of the buried oxide film which the SOI wafer to be produced has, and thereafter the silicon wafer in which the thicker buried oxide film is formed is subjected to a heat treatment to reduce the thickness of the buried oxide film.Type: GrantFiled: February 13, 2004Date of Patent: April 28, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Isao Yokokawa, Hiroji Aga, Kiyotaka Takano, Kiyoshi Mitani
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Patent number: 7521325Abstract: A permeation preventing film of a silicon nitride film 16 is inserted between a silicon substrate 10 and a High-k gate insulation film 18 to thereby prevent the High-k gate insulation film 18 from being deprived of oxygen, while oxygen anneal is performed after a gate electrode layer 20 has been formed to thereby supplement oxygen. The silicon nitride film 16, which is the permeation preventing film, becomes a silicon oxide nitride film 17 without changing the film thickness, whereby characteristics deterioration of the High-k gate insulation film 18 due to the oxygen loss can be prevented without lowering the performance of the transistor. The semiconductor device having the gate insulation film formed of even a high dielectric constant material can be free from the shift of the threshold voltage.Type: GrantFiled: July 28, 2005Date of Patent: April 21, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tsunehisa Sakoda, Masaomi Yamaguchi, Hiroshi Minakata, Yoshihiro Sugita, Kazuto Ikeda
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Patent number: 7521375Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.Type: GrantFiled: October 5, 2007Date of Patent: April 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
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Patent number: 7517813Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).Type: GrantFiled: October 6, 2005Date of Patent: April 14, 2009Assignee: X-FAB Semiconductor Foundries AGInventors: Ralf Lerner, Uwe Eckoldt
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Patent number: 7514315Abstract: A multilayer electrode structure has a conductive layer including aluminum, an oxide layer formed on the conductive layer, and an oxygen diffusion barrier layer. The oxide layer includes zirconium oxide and/or titanium oxide. The oxygen diffusion barrier layer is formed at an interface between the conductive layer and the oxide layer by re-oxidizing the oxide layer. The oxygen diffusion barrier layer includes aluminum oxide.Type: GrantFiled: April 11, 2007Date of Patent: April 7, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Kyoung-Ryul Yoon, Ki-Vin Im, Jae-Hyun Yeo, Eun-Ae Chung, Jin-Il Lee
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Patent number: 7507676Abstract: An insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding gas, and a third process gas containing a carbon hydride gas. This method includes repeatedly performing supply of the first process gas to the process field, supply of the second process gas to the process field, and supply of the third process gas to the process field. The supply of the third process gas includes an excitation period of supplying the third process gas to the process field while exciting the third process gas by an exciting mechanism.Type: GrantFiled: January 16, 2007Date of Patent: March 24, 2009Assignee: Tokyo Electron LimitedInventors: Pao-Hwa Chou, Kazuhide Hasebe
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Patent number: 7498270Abstract: A method for forming a densified silicon oxynitride film with tensile stress and a semiconductor device including the densified silicon oxynitride film. The densified silicon oxynitride film can be formed by depositing a porous SiNC:H film on a substrate in a LPCVD process, and exposing the porous SiNC:H film to an oxygen-containing gas to incorporate oxygen into the SiNC:H film, thereby forming a densified SiONC:H film having a greater density than the porous SiNC:H film. The densified silicon oxynitride film can be included on a substrate including the semiconductor device.Type: GrantFiled: September 30, 2005Date of Patent: March 3, 2009Assignee: Tokyo Electron LimitedInventor: John Gumpher
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Publication number: 20090050898Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).Type: ApplicationFiled: August 22, 2006Publication date: February 26, 2009Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
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Patent number: 7494940Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.Type: GrantFiled: January 17, 2006Date of Patent: February 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-Joo Doh, Hyung-suk Jung, Nae-in Lee, Jong-ho Lee, Yun-seok Kim
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Patent number: 7491656Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.Type: GrantFiled: September 20, 2004Date of Patent: February 17, 2009Assignee: Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
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Publication number: 20090042404Abstract: Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.Type: ApplicationFiled: August 10, 2007Publication date: February 12, 2009Inventor: Shyam Surthi
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Patent number: 7488652Abstract: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist layer 16 as a mask via the oxidation film 14a. When the oxidation films 14a and 14b are used as sacrificing oxidation films, gate oxidation films are formed in the element holes 12a and 12b after removing the resist film 16 and the oxidation films 14a and 14b. When the oxidation films 14a and 14b are used as gate oxidation films, the oxidation films are once thinned by etching and then thickened after removing the resist layer 16. The gate oxidation film 14a is thicker than the gate oxidation film 14b by forming the ion implantation layer 18.Type: GrantFiled: June 9, 2005Date of Patent: February 10, 2009Assignee: Yamaha CorporationInventor: Syuusei Takami
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Publication number: 20090004883Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.Type: ApplicationFiled: September 16, 2005Publication date: January 1, 2009Inventors: Mrinal K. Das, Anant K. Agarwal, John W. Palmour, Dave Grider
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Publication number: 20080318382Abstract: A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention, the dangling bonds between silicon oxide in a tunneling oxide layer and silicon adjacent to a semiconductor substrate interface are terminated by performing a annealing on a tunneling oxide layer, thereby improving the erase rate of the tunneling oxide layer.Type: ApplicationFiled: December 13, 2007Publication date: December 25, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Peigang Dai, Xiaopeng Yu, Jing Lin, Hualong Song
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Publication number: 20080318438Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed to a carbon layer; annealing the SiC layer to activate the impurity with covering the SiC layer with the carbon layer; removing the carbon layer; and performing a sacrifice oxidation process. The performing the sacrifice oxidation process includes: forming a sacrifice oxide film; and removing the sacrifice oxide film. The forming the oxide film is performed after the performing the sacrifice oxidation process.Type: ApplicationFiled: May 29, 2008Publication date: December 25, 2008Applicant: DENSO CORPORATIONInventors: Hiroki Nakamura, Hideki Kawahara
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Publication number: 20080308831Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.Type: ApplicationFiled: August 22, 2008Publication date: December 18, 2008Applicant: International Business Machines CorporationInventors: Nestor Alexander Bojarczuk, JR., Douglas Andrew Buchanan, Supratik Guha, Vijay Narayanan, Lars-Ake Ragnarsson
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Publication number: 20080299780Abstract: A method and apparatus using electromagnetic radiation and gas to create oxidation and reduction reactions on a device, such as a semiconductor wafer surface. In one embodiment, a scanned laser and gas may be employed in a number of oxidation and/or reduction reactions in a single system without using multiple pieces of equipment, corrosive chemicals and gases, high temperature and pressure chamber environments, waste treatment processes, and/or extra process steps typically required in existing processes.Type: ApplicationFiled: June 1, 2007Publication date: December 4, 2008Applicant: UV Tech Systems, Inc.Inventors: David J. Elliott, Victoria M. Chaplick
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Publication number: 20080293255Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.Type: ApplicationFiled: May 21, 2008Publication date: November 27, 2008Inventor: Krishnaswamy Ramkumar
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Publication number: 20080280456Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.Type: ApplicationFiled: May 8, 2007Publication date: November 13, 2008Inventors: Zhonghui Alex Wang, Tiruchirapalli Arunagiri, Fritz C. Redeker, Yezdi Dordi, John Boyd, Mikhail Korolik, Arthur M. Howald, William Thie, Praveen Nalla
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Patent number: 7446052Abstract: In a process involving the formation of an insulating film on a substrate for an electronic device, the insulating film is formed on the substrate surface by carrying out two or more steps for regulating the characteristic of the insulating film involved in the process under the same operation principle. The formation of an insulating film having a high level of cleanness can be realized by carrying out treatment such as cleaning, oxidation, nitriding, and a film thickness reduction while avoiding exposure to the air. Further, carrying out various steps regarding the formation of an insulating film under the same operation principle can realize simplification of the form of an apparatus and can form an insulating film having excellent property with a high efficiency.Type: GrantFiled: March 31, 2003Date of Patent: November 4, 2008Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasakii, Seiji Matsuyama
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Publication number: 20080268653Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.Type: ApplicationFiled: June 5, 2008Publication date: October 30, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-seok KIM, Hong-bae PARK, Bong-hyun KIM, Sung-tae KIM, Jong-wan KWON, Jung-hyun LEE, Ki-chul KIM, Jae-soon LIM, Gab-jin NAM, Young-sun KIM