Testing System Patents (Class 702/108)
  • Patent number: 6442498
    Abstract: An portable apparatus and method for troubleshooting and determining the integrity of cables and wiring harnesses requiring connection to only one end of the cable or wiring harness to be tested. A series of tests are conducted to determine the integrity of each wire within the cable or wiring harness. The data is then evaluated and compared to the data of a known good cable or wiring harness stored in a memory device or CD-ROM. The faulty cable or wiring harness, if any, are displayed along with a list of shorts or opens present between cables or between a cable and aircraft ground, and the exact distance to any detected fault.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: August 27, 2002
    Inventor: Henrick Youval Krigel
  • Publication number: 20020111697
    Abstract: A system and method for minimizing total cost of interaction among components of a computer program which are each characterized by at least one implementation property. A implementation property may, for example, be a choice of string representation (e.g. ASCII, UNICODE, EBCDIC or choice of data structure (e.g. hash, tree, compressed). The method comprises the steps of: carrying out a run of the program; monitoring that run to measure an amount of interaction between each pair of components; determining a cost of interaction between each pair of interacting components; determining a choice of implementation properties which minimizes total cost of the run; and assigning choices of implementation properties to said components for a future run of the program.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 15, 2002
    Applicant: International Business Machines Corporation
    Inventors: Douglas N. Kimelman, Vadakkedathu T. Rajan, Tova Roth, Vugranam C. Sreedhar, Mark N. Wegman
  • Patent number: 6434499
    Abstract: The present invention provides a portable on-site tester to test a disc drive at a location remote from the disc drive manufacturer. The tester supports multiple disc drive interfaces by supporting multiple drive initiator cards, one of which is selected for use at a time. A tester which controls operation of the tester is attached to a local computer via a tester interface. The proper drive initiator card is selected for connection to the tester interface such that the drive initiator card supports the disc drive interface format of the disc drive to be tested. The tester may be configured to support different disc drive interfaces by connection of various drive initiator cards to the tester. The drive initiator cards are mounted to one or more drive initiator card supports, which are oriented in the tester such that the selected drive initiator card is electrically connected to the tester.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: August 13, 2002
    Assignee: Seagate Technology LLC
    Inventors: Scott D. Ulrich, Cary D. Johnson, Morse Magnuson, Peter A. Sherrard
  • Patent number: 6418389
    Abstract: Test system and test method for testing the operability of test samples (7). A selection can be made in a user-specific manner from a plurality of test modules (2a-2c) which are made available, which can be assembled together to a desired test specification. A control module (1) carries out the overall test corresponding to the user-specific test specification, and controls individual selected test modules (2a-2c) in the desired sequence in correspondence to this test specification. Advantageously, there is produced automatically a test report on the test results of the individual selected test modules (2a-2c), which reports in particular embedded in the user-specific test specification.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: July 9, 2002
    Assignee: Omicron Electronics GmbH
    Inventors: Winfried Peter, Thomas Hensler
  • Publication number: 20020087282
    Abstract: A system and method for computer network testing using a production machine and client to playback edited network information to a target machine. In general, the system of the present invention includes a target machine, a production machine, a playback file, a playback machine, a playback controller and a network information editor. The playback file includes network information collected by the production machine in a production environment and edited by the network information editor. The playback machine reads the playback file and send the edited network information (such as network requests) contained in the playback file to the target machine. The playback controller initiates and coordinates the playback of the playback file on the playback machine. The present invention can also perform stress testing of the target machine by altering the amount of network information sent to the target machine within a given time.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventor: Adam C. Millard
  • Publication number: 20020081757
    Abstract: The system for providing information on quality and reliability according to the present invention comprises: a first information communication terminal for outputting at least one of step information (A), step information (B), step information (C) and step information (D) as information on the side of a maker producing an optical semiconductor device; a second information communication terminal for outputting at least one of step information (E), step information (F), and step information (G) as information on the side of an user using the device; and an information processing apparatus connected to the first and second information communication terminals through a communication network, wherein the information processing apparatus computes a rate of change in the characteristic of the device from the steps on the maker side to the steps on the user side on the basis of information outputted from the first and second information terminals, and outputs a signal for representing an abnormality to at least one
    Type: Application
    Filed: November 28, 2001
    Publication date: June 27, 2002
    Inventor: Shigemitsu Shiba
  • Patent number: 6405147
    Abstract: A signal transfer device measurement system and method of the present invention measures the signal transfer characteristics of a device under test (DUT) having an analog input port and either an analog output port or a digital output port. The measurement system and method comprise a stimulus waveform generator that produces a stimulus waveform. The stimulus waveform comprises a time sequence of pairs of narrow bandwidth, modulated signals. The stimulus waveform is applied to the input port of the DUT thereby producing an output response signal at the output port of the DUT. For a DUT with an analog output port, the measurement system and method further comprise an analog-to-digital converter (ADC) for digitizing the output response signal and producing digital data and a signal processor for processing the digital data thereby producing measured results.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: June 11, 2002
    Assignee: Condor Systems, Inc.
    Inventor: Peter P. Fera
  • Patent number: 6401049
    Abstract: A process of testing individual components of a system in an automotive vehicle, wherein the system comprises at least one software-operated controller and the controller is adapted to be connected to an input station, with software being adapted to be uploaded to the input station from the controller and a test software being uploaded from the input station to the controller prior to a check of the components of the system.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 4, 2002
    Assignee: Continental Teves AG & Co., OHG
    Inventor: Norbert Ehmer
  • Patent number: 6393371
    Abstract: A method and apparatus for operating an integrated circuit in an electronic device by controlling the supply voltage to the integrated circuit (IC). A parameter of the IC is measured and used to adjust the supply voltage of the IC. The measured parameter is indicative of the effective channel mobility of the IC. One purpose of adjusting the voltage is to modify the effective channel mobility such that the individual channel currents are substantially constant over a predetermined operating temperature range of the IC. The modification of channel mobility is chosen to set the individual channel currents at levels that either maximizes operating speed, minimizes power consumption, extends the range of operating temperature, or increases the operational reliability of the IC.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: May 21, 2002
    Assignee: Hewlett-Packard Company
    Inventors: James F. Bausch, Andrew L. Van Brocklin, Chadwick W. Stryker
  • Patent number: 6389370
    Abstract: The present invention is generally directed to a system and method for determining whether components of a computer system should be analyzed for updates and repairs. In accordance with one aspect of the invention, a method evaluates a configuration object containing an identification of components installed on the computer system. The method also evaluates an analyzer object, containing information about an analyzer, to determine whether the analyzer operates upon the system, based on the characteristics of the system and the characteristics sought by the analyzer. Then, the method evaluates an update object, containing information identifying the last time that the components of the computer system were analyzed by the analyzer, to determine whether the analyzer should be run again. The method also evaluates a global data source. The result of this evaluation determines which additional systems should be analyzed.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: May 14, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Kurt A. Delaney, Paul L. Dineen
  • Patent number: 6377898
    Abstract: A method of analyzing and classifying defects on semiconductor wafers during a semiconductor manufacturing process using a comparator die selector system wherein an automatic defect classification review tool compares defects on a die location with an identical location on an identical die. The automatic defect classification review tool locates identical die with information from the comparator die selector system.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul J. Steffan, Allen S. Yu
  • Publication number: 20020040279
    Abstract: The method comprises:
    Type: Application
    Filed: September 25, 2001
    Publication date: April 4, 2002
    Inventor: Hans Jedlitschka
  • Publication number: 20020038191
    Abstract: A writer coil in a data head of a data storage system is tested by coupling detection circuitry to the writer coil and driving the writer coil with a periodic pulse signal generated by the detection circuitry. As a result, voltage is generated, with the detection circuitry, as a function of an inductance of the writer coil. An inductance of the writer coil is calculated as a function of the generated voltage. Electrical short circuits and discontinuities in the writer coil are identified as a function of the calculated inductance.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 28, 2002
    Inventors: Beng Theam Ko, Eng Hock Lim, Myint Ngwe, Kah Liang Gan, Beng Wee Quak
  • Patent number: 6360180
    Abstract: A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: March 19, 2002
    Assignee: Teradyne, Inc.
    Inventor: Peter Breger
  • Patent number: 6344749
    Abstract: A test system for measuring a frequency response of a signal path 148 by transmitting a short duration burst test signal 234 from a remote point 152, capturing an impaired burst test signal 432 on a digital signal acquisition unit 416, and analyzing the received signal by digitally processing it with an unimpaired burst test signal 434. A dynamic range test can also be performed with the same burst test signal by removing the energy in a part of the frequency band with a notch filter 232, and then increasing the power of the burst test signal level until non-linear distortion occurs. The distortion products will fill-in the notch, allowing the clipping threshold of the signal path to be measured. A burst trigger signal 244 generated by the transmitter device 201 causes a digital signal acquisition unit to acquire an impaired burst test signal.
    Type: Grant
    Filed: December 6, 1997
    Date of Patent: February 5, 2002
    Inventor: Thomas H. Williams
  • Publication number: 20020004709
    Abstract: Test system and test method for testing the operability of test samples (7). A selection can be made in a user-specific manner from a plurality of test modules (2a-2c) which are made available, which can be assembled together to a desired test specification. A control module (1) carries out the overall test corresponding to the user-specific test specification, and controls individual selected test modules (2a-2c) in the desired sequence in correspondence to this test specification. Advantageously, there is produced automatically a test report on the test results of the individual selected test modules (2a-2c), which reports in particular embedded in the user-specific test specification.
    Type: Application
    Filed: August 2, 1999
    Publication date: January 10, 2002
    Inventors: WINFRIED PETER, THOMAS HENSLER
  • Patent number: 6334092
    Abstract: A measurement device for measuring an internal quality of a fruit or vegetable with light is intended to be able to obtain the internal quality at higher speed and with accuracy. In the measurement device of the internal quality, transmitted light through the fruit or vegetable is split into a plurality of frequency regions and the measurement device is provided with a plurality of processing circuits for carrying out intensity data calculating operations simultaneously and in parallel for the respective frequency regions.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: December 25, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Hirotsugu Hashimoto, Toyohiko Aoki
  • Patent number: 6324485
    Abstract: An application specific automated test equipment system for source synchronous bus interface devices is described. A native interface board is provided to interface an automated test unit and a device under test. The native interface board is configured with devices selected to recreate a native environment of the device under test. A first clock drives the devices on the native interface board. A second clock drives the device under test. The second clock signal is derived from the first clock signal to form a substitute clock signal that can be adjusted in relation to the first clock signal. Input and output timing relationships of the device under test are determined by altering the arrival time of the substitute clock at the device under test with respect to the timing of the first clock signal.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: November 27, 2001
    Assignee: NewMillennia Solutions, Inc.
    Inventor: James M. Ellis
  • Patent number: 6324168
    Abstract: The location of a termination in a properly terminated LAN can be remotely detected. The cable's skin effect produces a detectable signature at the sending-end when a step function, for example, reaches the termination. Accordingly, a network analysis device is connected to the network to inject the step function onto the network cabling. The voltage response of the cabling to this is first digitally sampled and then analyzed in a system controller. The system controller reviews the sampled data for an inflection point and then locates the termination by reference to the delay between when the signal was placed on the cable and the detection of the inflection point.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: November 27, 2001
    Assignee: Vigilant Networks LLC
    Inventor: William M. Richardson
  • Patent number: 6321173
    Abstract: An equivalence checking system and method efficiently determine whether different circuit models are functionally equivalent. The equivalence checking system first verifies the functional equivalence of a first circuit model to a second circuit model. In verifying this equivalence, the equivalence checking system produces mapping point pairs. The equivalence checking system utilizes these mapping point pairs in determining whether other models of the circuit are equivalent to the first model. Since the mapping point pairs are reused by the equivalence checking system, the number of new mapping point pairs needed to verify the functional equivalence of the other models is reduced or eliminated. Accordingly, the overall efficiency of the equivalence checking system is increased.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: November 20, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Harry D. Foster
  • Patent number: 6321174
    Abstract: An apparatus is provided to test a device, i.e. an interface card to a computer system or an IC chip. The apparatus communicates with the computer system via a first bus and communicates with the device via a second bus. The first and second buses are standard bus such as ISA bus, EISA bus, PCI bus, and AGP bus, etc. In the apparatus, three switch circuits respectively making connection of data/address lines, power lines and a reset line of the first bus to the second bus are provided. A test program executed in the computer generates a plurality of control signal to the apparatus. A control circuit, responsive to the plurality of control signals, controls individually and selectively the turn-on of three switch circuits. By test program running in the computer system, the function test of the device can be accomplished automatically without time-consuming power-off and re-initialization of the computer system.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: November 20, 2001
    Assignee: Winbond Electronics Corp.
    Inventors: Jao-Ching Chen, Shu-Yi Yen, Peter Chang
  • Patent number: 6314470
    Abstract: A system for providing a graphics tool access to a computer graphics system to evaluate and control a graphics application executing on the computer graphics system. The system includes application program interface (API) event generators for performing predetermined operations relating to a graphics library function call and for generating a hook event containing results of the predetermined operations; dispatch table manger for selecting an active dispatch table from a normal operations dispatch table having function pointer to the graphics library finctions and a hooks dispatch table having pointer to the API event generators; and hook event manager for enabling and configuring selected ones of the API event generators in response to a graphics tool event request. The system further includes internal event generators, integrated along various locations of a graphics pipeline managed by the graphics library, for performing predetermined diagnostic operations in the graphics system.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: November 6, 2001
    Assignee: Hewlett Packard Company
    Inventors: Alan D. Ward, Rex A. Barzee, Kevin T. Lefebvre, Don W. Dyer, James G. Dugger
  • Publication number: 20010025226
    Abstract: A medical screening apparatus and method includes a housing containing a user interface, an automatic medical test apparatus and a transmitting means for communicating the output of the medical test apparatus to a remote site for analysis. In one aspect, the user interface is a video display terminal capable of receiving user data and for displaying the medical test output. Preferably, the test output is automatically transmitted via a global telecommunication network, such as the Internet, to the remote site.
    Type: Application
    Filed: February 14, 2001
    Publication date: September 27, 2001
    Inventor: Kevin T. Lavery
  • Patent number: 6289292
    Abstract: With the present invention, a component may be identified based upon selected physical characteristics of the component. In one embodiment, a system is provided for storing information pertaining to components within a set of components. A characterization function, which is a function of relevant physical characteristics shared by each component within the set of components, is associated with the set of components. The system includes a characterization value test station and a database. The characterization value test station is used to determine the characterization values of the components pursuant to the characterization function. The database stores information that pertains to each component with the component's characterization value linked as an identifier to the information. In this manner, information pertaining to a component may be retrieved from the database based on the component's characterization value.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: September 11, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Dave E. Charlton, Roland Ochoa
  • Patent number: 6278920
    Abstract: A computerized method for quantifying confidence in a replacement schedule for components that must be routinely replaced within a fleet of aircraft or like equipment includes programming a computer to accept predetermined input data, including anticipated life expectancy T, indicated reliability R1, the population P of the component in the fleet, and the number of failed units F replaced over a time increment t. The method computes the minimum-mean-time-between-removals &thgr;1, and the upper limit on unreliability Pu based upon such input data. The computer compares two or more of such factors to a series of Gamma Confidence Level look-up tables, and either determines a Gamma Confidence Level for the user, or prompts the user to modify the input data so that a Gamma Confidence Level can be determined. If the resulting Gamma Confidence Level is too low, the anticipated life expectancy T is reduced, and the method is repeated.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: August 21, 2001
    Inventor: James O. Hebberd
  • Patent number: 6278956
    Abstract: A method for locating a failing latch in a defective shift register having P latches connected in series fabricated in an integrated circuit chip. The chip is depassivated to expose its upper metalized layer, and it is in the chamber of a scanning electron microscope (SEM) having sharp voltage contrast capabilities. Clock signals are generated to properly exercise the shift register. A string of N latches, wherein 1≦N≦P, typically N=P/2 is first selected and the stimuli are applied to the latches to allow the output net of the last latch of the string to toggle at a frequency of about 1 Hz. The SEM beam is focused on the area which encompasses the last latch, so that, if the latch output net blinks on the SEM screen, the string under observation is deemed to be good. Then, another, more extended string is selected and the above procedure is repeated.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: August 21, 2001
    Assignee: International Business Machines Corporation
    Inventors: Alain Leroux, Dominique Petit, Sylvain Posson
  • Patent number: 6272442
    Abstract: A method and system to enable extended testing of computer system drives that allows concurrent processing of input/output requests directed at the physical drive being tested, the computer system having a plurality of drives, a drive testing program stored in the computer's memory, and a drive exchange program stored in the computer's memory. The drive exchange program includes the steps of a) copying information and writes from a drive to be tested to a spare drive, b) logically replacing the drive to be tested with the spare drive, c) interfacing with the drive testing program, and d) allowing the drive testing program to test the drive to be tested.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: August 7, 2001
    Assignee: Dell USA, L.P.
    Inventor: Ken Jeffries
  • Publication number: 20010005817
    Abstract: According to the preferred embodiments of the present invention, a method of creating and accessing additional test points after circuit board design has been completed is disclosed. The apparatus and methods of the present invention provide test engineers with the ability to leave any circuit interconnections located on the exterior surfaces of a PCB exposed. These exposed circuit interconnections may be identified as access or test points and the apparatus of the present invention is specifically adapted to access, probe, and evaluate these access or test points. To allow the exposed circuit interconnections to be tested without damaging them, the invention includes a new type of probe for use in contacting the exposed traces. The preferred embodiments of the test probe apparatus of the present invention has a relatively flat head to reduce pressure on the circuit interconnections and is coated with dendrites to enhance electrical connectivity between the circuit interconnections and the probe.
    Type: Application
    Filed: February 13, 2001
    Publication date: June 28, 2001
    Inventors: Raymond J. Caggiano, Charles Colpo, Jeffrey A. Hatley, W. Peter Soroka, Rondell K. Watts
  • Patent number: 6198273
    Abstract: In an integrated-circuit tester which is provided with a contact failure analysis/storage part for counting and storing the number of failures occurring at each contact, an automatic stop part for deciding contact as defective based on the numbers of failures stored in the storage part and for stopping a handler, an automatic turn-OFF part by which, upon each operation of the automatic stop part, contacts having met the stop condition are automatically put in their unused state, and a defective contact display for displaying the number of contacts put in the unused state upon each automatic stop of the handler, an operator checks the number of contacts put in the unused state upon each automatic stop of the handler, then decides whether or not all the contacts used are to be replaced, and performs the necessary operations for resuming the test.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: March 6, 2001
    Assignee: Advantest Corporation
    Inventors: Takeshi Onishi, Minoru Yatsuda, Katsuhiko Suzuki
  • Patent number: 6188938
    Abstract: A method of incorporating customer feedback into correcting vehicle vibration begins by interviewing a vehicle owner concerning an objectionable vehicle vibration. The dealer then connects a vibration analyzer to the vehicle with the objectionable vibration through an OBD-II connector. This allows the vibration analyzer to monitor engine rpm, engine type, vehicle speed, vehicle type, and tire size. The dealer then drives the vehicle at a full range of speeds in a controlled sequence with the vehicle owner to reproduce the objectionable vehicle vibration. While the vehicle is driven, the vibration analyzer detects any vehicle vibration generated. The vibration analyzer then compares the vehicle vibration in conjunction with engine rpm, engine type, vehicle speed, vehicle type, and tire size when the vehicle owner identifies the objectionable vibration. The vibration analyzer then determines a probably cause for the vehicle vibration and generates a cause report.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: February 13, 2001
    Assignee: Ford Motor Company
    Inventors: Gerard Paul Silka, Kenneth Alan Ward
  • Patent number: 6178308
    Abstract: A system and method for providing interactive computer assisted teaching. The system is premised on and extends the ubiquitous nature of paper in classroom environments to be an interaction medium with a computer based system. By utilizing intelligent form and embedded data processing, highly interactive and customized teaching applications can be created. A student and other members of the educational community interacts with the system by making marks on an educational material and then scanning that educational material back into the system. Intelligent forms processing techniques are used to identify the marks made and pass them on to a teaching application. The teaching application will then determine an appropriate course of interaction, which may include having a responsive educational material printed out for the student. The system provides for having a single computer in a classroom, wherein students can use a familiar medium, paper, to interact with the computer.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: January 23, 2001
    Assignee: Xerox Corporation
    Inventors: Daniel G. Bobrow, John O. Everett
  • Patent number: 6098028
    Abstract: A novel graphical user interface for test device applications which permits simultaneous display of system status and alarm information while supporting graphically based test device I/O and configuration. The present invention also includes a novel graphical representation I/O scheme whereby test device configuration is accomplished through intuitive manipulation of an image of the test device. The present invention also includes embedded menuing features and a "one button down" user input section which facilitates ease of operation of the system. The present invention may be advantageously applied to a test device designed to extract and process telecommunications signals such as DS1, DS3, SONET, and ATM communication protocols.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: August 1, 2000
    Assignee: Digital Lightwave, Inc.
    Inventors: Bryan J. Zwan, Kenneth T. Myers
  • Patent number: 6098027
    Abstract: A charge mode open/short test circuit comprises at least two charge capacitors. A plurality of signal traces under test are connected to the test circuit first through a plurality of test tips on a test prober and then a plurality of transmission gates in a test circuit. In a load mode, reference data are loaded. In a test mode, a charge capacitor is sequentially selected and discharged into the parasitic capacitor corresponding to a sequentially selected signal trace under test for generating a charge balance signal. The signal is amplified and compared with the loaded reference data in either a digital or an analog manner. The compared pass/fail output related to the property of the signal trace is stored in a memory. In a following read mode, the stored pass/fail output is read out to an external unit for further processing.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: August 1, 2000
    Assignee: Industrial Technology Research Institute
    Inventor: Steven J. R. Yang
  • Patent number: 6090147
    Abstract: A computer program media embodies a program of instructions executable by a computer to perform method steps for simulating the dynamic response of a structural-acoustic system over a broad range of frequencies. The method includes the steps of wavenumber partioning a design of the structural-acoustic system into large-scale behavior and small-scale behavior; determining the large-scale behavior; and determining the small-scale behavior.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: July 18, 2000
    Assignee: Vibro-Acoustics Sciences, Inc.
    Inventors: Paul M. Bremner, Robin S. Langley
  • Patent number: 6078875
    Abstract: The present invention provides automated systems for performing electrostatic discharge (ESD) device efficacy verification and recording the results for an ESD auditing program. Systems of the present invention comprise at least one ESD device testing unit. The testing unit may include sensors and circuits for identifying particular worker who are performing the test. The testing unit includes a testing circuitry for periodic verification of the efficacy of the ESD device. A communication system allows the testing unit to communicate with a central computer which collects, stores and allows the manipulation of the test data. Systems of the present invention are therefore useful in testing the ESD devices, documenting their performance, and controlling access to particular work areas based on testing results.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: June 20, 2000
    Assignee: Semtronics Corporation
    Inventors: Bradford Tyler Jubin, Michael Albert Sanchez, Albert C. Breidegam, Edwin B. Bradley
  • Patent number: 6018617
    Abstract: A method and system for generating and formatting information, specifically test questions, in a desirable and predetermined manner. The system has dynamic-content and dynamic-presentation capabilities so that a wide variety of test problems and, ultimately, tests which consist of test problems can be created. The system includes a data processor such as a personal computer having a means for storing at least one computer program and a means for printing indicia such as a laser printer. The software component of the system includes an authoring tool which is used to create generalized expressions of a problem. A variation rules module or engine stores the variations rules which are a language for describing how to create varying questions from the generalized expression or definition of and a problem created in the authoring tool. Then another component of the software, the print engine interprets the variation rules and produces screen displays or printed tests.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: January 25, 2000
    Assignee: Advantage Learning Systems, Inc.
    Inventors: Keith R. Sweitzer, Karl E. Sweitzer
  • Patent number: 5978743
    Abstract: The method of self-calibrating for a sensor without using an additional device by using data sampling, an approximate value of linear errors obtained by performing the numerical integration of approximate values of a linear-error derivative, correcting the approximate value of the input value at each sampling point, and repeating the processing for correcting the approximate value of the linear error by necessary times.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: November 2, 1999
    Assignee: Mitutoyo Corporation
    Inventor: Satoshi Kiyono
  • Patent number: 5953684
    Abstract: Methods and structure for storing context data regarding electronic test equipment and the device under test or stimulus sources in a manner integrated with the capture and storage of test data as well as test setup data associated with a test environment. The context data may include information regarding parameters of the test environment (e.g., test equipment or test bench set points and configurations, configuration information regarding the device under test, etc.). The context data may be provided in the form of standard textual data as well as user voice sequences to be recorded. The context data is associated with any stored test data or test setup data so as to be easily retrieved along with the retrieval of the associated data. The data are associated by any of several methods including file naming conventions, structured files, table lookups, etc.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: September 14, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Jay A. Alexander
  • Patent number: 5950144
    Abstract: A system for testing the electrical components of vehicles during manufacturing includes a hand held tester to which a translator unit can be detachably engaged and with which the tester is in RF communication. The translator unit can be detached from the tester and plugged into a test receptacle under a vehicle's dashboard to communicate with the vehicle by translating computer formatted data from the tester to vehicle bus-formatted data, and vice-versa. Then, the vehicle's VIN is scanned into the tester or manually input into the tester, and the tester transmits the VIN via an RF link in the assembly plant to a computer in the plant. Based on the VIN, the computer determines the electric equipment that the vehicle has, and the computer transmits this information back to the tester. The tester then determines which tests to execute, and the tester causes the translator unit to undertake these tests.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: September 7, 1999
    Assignee: Chrysler Corporation
    Inventors: Michael Hall, Ben So, Mark A. Desjardins
  • Patent number: 5940782
    Abstract: A method of calibrating a linear driver system including a linear driver circuit, logic means connected to an input line of the linear driver circuit, and information storage means associated with the logic means, involves testing the linear driver circuit once assembled. A predetermined test load and a test electrical energy source are connected to the linear driver circuit. A first input test voltage is applied to the input line of the linear driver circuit and a corresponding first current level through the test load is measured. A second input test voltage is applied to the input line of the linear driver circuit and a corresponding second current level through the test load is measured. The two measured current levels are stored in the information storage means for later retrieval during operation of the linear driver system.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: August 17, 1999
    Assignee: Caterpillar Inc.
    Inventors: Paul C. Gottshall, Brian G. McGee
  • Patent number: 5937366
    Abstract: A smart built-in-test device for classifying fault behavior in electronic systems comprising a temporal monitor monitoring fault, classifying fault behavior and generating fault behavior data as the system operates in real time; one or more sensors for measuring environmental stress conditions in real-time and outputting environmental stress condition data. A fault correlator device for receiving the fault behavior data and the environmental stress condition data and correlating fault behavior to environmental stress conditions to determine if significant correlation exists.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: August 10, 1999
    Assignee: Northrop Grumman Corporation
    Inventors: John Zbytniewski, Charles H. Cooper
  • Patent number: 5909657
    Abstract: A semiconductor device testing apparatus in which ICs to be tested are loaded on a test tray in a loader section, the test tray is transported into a test section to test the ICs, after the completion of the test, the tested ICs on the test tray are transferred from the test tray onto a general-purpose tray in an unloader section, the test tray which has been emptied of the tested ICs is transported to the loader section, and the above operation is repeated, and which can detect a failure of an IC carrier mounted to the test tray independently of detection of a failure IC socket is provided. An IC carrier failure analysis memory is provided which has storage addresses the number of which is equal to the number of IC carriers mounted to each of the test trays, and the number of ICs as determined to be defective is stored and accumulated in each of the storage addresses of the IC carrier failure analysis memory.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 1, 1999
    Assignee: Advantest Corporation
    Inventors: Takeshi Onishi, Katsuhiko Suzuki
  • Patent number: 5884237
    Abstract: An automatic door system includes a door which id driven to open and close by a motor. A sensor senses an object which approaches or leaves the door. A control section controls the motor in accordance with a signal supplied from the sensor. The control section includes a CPU which examines the motor, the sensor and the control section for failure or malfunction, and also an EEPROM which stores the result of examination made by the CPU. The result of examination stored in the EEPROM is outputted to a Handy Terminal or a personal computer.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: March 16, 1999
    Assignee: Nabco Limited
    Inventors: Hisayuki Kanki, Naoki Taguchi
  • Patent number: 5845233
    Abstract: A method for calibrating a circuit analyzer includes determining a plurality of initial technology parameters characterizing the circuit according to a timing model of the circuit. A delay along an entire logic path of the circuit is expressed as a function of the technology parameters. A benchmark set of circuit paths is determined which has fixed topology, device sizes, and wire capacitances. The technology parameters are then optimized to minimize error over the set of circuit paths to obtain optimized parameters for use in the timing model. The optimized technology parameters minimize the average error for the benchmark set of paths relative to SPICE or physical measurements. Average error is significantly reduced on a representative set of paths when compared to the conventional approach of separately measuring each parameter.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: December 1, 1998
    Assignee: Lucent Technologies, Inc.
    Inventor: John Philip Fishburn
  • Patent number: 5832419
    Abstract: An apparatus identifies an integrated circuit. The apparatus includes a portable housing that has mounted thereto a processing circuit for reading identification data stored in the integrated circuit. A communication device is mounted to the housing and couples the identification data from the integrated circuit to the processing circuit. A display device that is mounted to the housing and is coupled to the processing circuit displays the identification data.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: November 3, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Thomas W. Voshell, Lisa J. Davis
  • Patent number: 5822714
    Abstract: A data processing system and method are implemented for determining when a portion of RFID tags in a read volume cannot be fully accessed by a RFID tag reader. In the data processing system, multiple known RFID tags are placed around a perimeter of a three-dimensional read volume. A RFID tag reader interrogates each of the RFID tags to determine whether all the perimeter RFID tags can be accessed before the reader attempts to access the contents of the read volume. If the reader is unable to interrogate all of the perimeter RFID tags, then it is likely that a blockage of radio frequency signals within the read volume exists. Therefore, an RFID tag within the read volume cannot be accessed because the RF signals are unable to reach the RFID tag due to blockage. In this situation, a system operator would be alerted that an RFID reader is unable to accurately access a number of RFID tags within the read volume. The system operator would also be alerted as to a location of the blockage within the read volume.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: October 13, 1998
    Assignee: International Business Machines Corporation
    Inventor: Robert Thomas Cato
  • Patent number: 5822717
    Abstract: Methods and apparatus are disclosed for testing integrated circuits at the wafer level and for integrating test results, calculation of lifetimes and generation of trend charts in a common database following testing. A wafer tester controller is supplemented with additional hardware and software to avoid data transfer errors and facilitate processing and storage of test results. The data base is available over a network to all areas of an organization.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: October 13, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jerry Tsiang, Mikkel Lantz, Yeng-Kaung Peng, Ying Shiau
  • Patent number: 5781445
    Abstract: A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: July 14, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Yun Shiue, Sung-Mu Hsu