Testing System Patents (Class 702/108)
  • Patent number: 7003419
    Abstract: A card for testing functions of the card interface of an electronic device is provided. The testing card includes a converting circuit, a latch circuit, a data processor, a signal generator, an oscillation combination circuit, and a reset circuit is provided. The converting circuit is coupled to the card interface. The latch circuit receives the data signal fed in from the card interface, latches the data signal and outputs it to the data processor afterwards. Having received the signal sent from the converting circuit and the latch circuit, the data processor is able to proceed with testing. The signal generator can output the mode selection signal and the interrupt signal to the card interface to test the functions of mode selection and interrupt signals. Furthermore, the oscillation combination circuit can generate a wait signal and feed the wait signal to the card interface for the wait test.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: February 21, 2006
    Assignee: High Tech Computer Corp.
    Inventors: Jen-De Chen, Yung-Ming Lu
  • Patent number: 7003471
    Abstract: A system that determines if mail contains life-harming materials before the mail enters the interior of a receptacle, i.e., mail box. This invention accomplishes the foregoing by issuing stamps that uniquely identify the stamp and identify the mailer to whom the stamp was issued; having a scanner at a receptacle read the stamp and send the unique identifying code contained in the stamp to a data center that checks if the stamp is genuine; and stores the stamps unique code before mail is permitted to enter the interior of the receptacle.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: February 21, 2006
    Assignee: Pitney Bowes Inc.
    Inventor: Ronald P. Sansone
  • Patent number: 6992576
    Abstract: A test device for testing an electronic device having a plurality of device terminals that receive a signal, includes: an operating condition outputting unit for outputting an operating condition indicating an operation of a signal to be supplied to a device terminal to be associated with said device terminal; and a test module for supplying a test signal used in a test of the electronic device to the electronic device based on the operation indicated by the operating condition.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 31, 2006
    Assignee: Advantest Corporation
    Inventor: Nobuei Washizu
  • Patent number: 6992491
    Abstract: A cable tester tests cable and determines a cable pass/fail status. A pretest module senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, and calculates a cable length. The cable status includes an open status, a short status, and a normal status. The test module determines the cable status of the cable based on the cable at least one of passing and failing A out of B cable tests. The test module determines the cable status for each of the B tests based on the measured amplitude and the calculated cable length.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: January 31, 2006
    Assignee: Marvell International, Ltd.
    Inventors: William Lo, Yiqing Guo, Tak Tsui, Tsin-Ho Leung, Runsheng He, Eric Janofsky
  • Patent number: 6983216
    Abstract: A test automation tool is provided which is operable to integrate a set of dynamic attributes and values into tests to be performed on a computing environment. The test automation tool includes a job submission engine (JSE) operable to receive input regarding first attributes unchanged from a first computing environment and second attributes representing change from the first computing environment. A job control file generator (JCFG) is provided in electronic communication with the job submission engine and is operable to automatically generate job control files (JCFs) for controlling testing of the computing environment according to attribute values including first attribute values and second attribute values. First attribute values are generated based on an automatic sampling of values of first attributes. The JSE is further operable to automatically submit the JCFs to the computing environment for execution and to automatically monitor execution according to the JCFs.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: January 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thanh V. Lam, Giampaolo Lauria
  • Patent number: 6983393
    Abstract: A method for operating a system that includes several subsystems may involve establishing one or more synchronized timelines for the system; allocating timeslots within each of the timelines for operation of one or more devices in the system; detecting an input event asynchronously to the timeline; generating a timestamp indicative of the time at which the input event is detected relative to the timeline; performing a processing task in response to the input event during a time slot allocated to the processing task; and inhibiting generation of an output event until a second time relative to the timelines. Performing the processing task may generate data representative of the output event as well as data representative of the second time. The second time may be a pre-determined time interval after the input event detection time.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: January 3, 2006
    Assignee: National Instruments Corporation
    Inventors: James J. Truchard, Brian Keith Odom
  • Patent number: 6983221
    Abstract: A computer-assisted system, medium and method of providing a risk assessment of a target system. The method includes providing one or more test requirements categories, associating one or more first data elements with each requirements category, associating one or more second data elements with a degree of exposure of the target system to the one or more threats, comparing the first data elements to the second data elements to determine, based on predetermined rules, composite data elements for each requirements category; and selecting, based upon predetermined rules, a level of risk of the composite data elements as a baseline risk level for each requirements category.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: January 3, 2006
    Assignee: Telos Corporation
    Inventors: Richard P. Tracy, Hugh Barrett, Gary M. Catlin
  • Patent number: 6973402
    Abstract: A system for testing integrated circuits by testing the change of integrated circuits under various temperatures comprises: at least one two-dimensional matrix testing module which includes a testing section having arrays for plugging integrated circuits to be tested, a heating section corresponding with the above testing section for heating integrated circuits respectively; a computer mainframe for connecting said two-dimensional matrix testing module and controlling the whole operations of the testing system, and a database. With the above-described structure, said database and said two-dimensional matrix testing module can be connected with the computer mainframe such that the temperature control information can be transmitted to provide each heater of said heating section to generate a suitable temperature, heat the integrated circuit to be tested, and store the test information.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: December 6, 2005
    Assignee: PROGenic Technology Co., Ltd.
    Inventor: Yih-Min Lin
  • Patent number: 6968284
    Abstract: In a method for the analysis and evaluation of measured values of an open test system, a test piece is monitored during a test run by at least one signal channel which sends a signal to an evaluation unit for further processing whereby at least one plausibility node is coupled with at least one signal channel. In order to allow a statement to be made about the value of plausibility nodes and their results in relation to a specific measuring task, an evaluated plausibility is ascertained for at least one of the measured values from the type and number of plausibility nodes as well as their possible, variable interconnection.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 22, 2005
    Assignee: AVL List GmbH
    Inventors: Klaus-Christoph Harms, Christian Beidl
  • Patent number: 6963907
    Abstract: A method of operating an Internet device, includes downloading via the Internet a medical testing program from a server. At least one sensor is coupled to the Internet device. The sensor is attached or otherwise coupled to a patient. The Internet device executes the test program to obtain test measurement data from the at least one sensor. The test measurement data is uploaded to the server via the Internet. The Internet device receives processed test data from the server as a download from the server via the Internet. The Internet device displays the processed data.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: November 8, 2005
    Assignee: Cardiobeat.com
    Inventors: George McBride, Robert Royce
  • Patent number: 6961668
    Abstract: Exemplary embodiments of the present invention include methods for evaluating a test action for a user. Such methods include creating, within a network, a user metric vector in dependence upon a plurality of disparate user metrics, selecting a test action in dependence upon the user metric vector, executing the test action within the network, and determining a user reaction. Many embodiments also include adding the test action to a user's action list in dependence upon the user reaction. Other embodiments often include deleting the test action from an test action list in dependence upon the user reaction.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: November 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Kress Bodin, Michael John Burkhart, Daniel G. Eisenhauer, Daniel Mark Schumacher, Thomas J. Watson
  • Patent number: 6957161
    Abstract: An information handling system (IHS) is provided which includes a power supply with a self diagnostics feature. The power supply supplies power to a test load resistor for a predetermined brief test period. The test period selected is sufficiently short so that a relatively small power rating load resistor is not overheated during the load test. A first indicator is activated if power good is indicated after the load test. This provides a notification that the power supply is operating properly. If power good is not indicated after the load test then a test is conducted to see if the supply is connected to the system board. If the supply is not connected to the system board and power good is not indicated, then a second indicator is activated to conclusively notify of power supply failure However, if the supply is found to be connected to the system board and power good is not indicated, then a third indicator is activated to notify the user that the source of failure is undetermined.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: October 18, 2005
    Assignee: Dell Products L.P.
    Inventors: Robert Allen, William O. Bain
  • Patent number: 6950779
    Abstract: An apparatus for detecting incorrect connector insertion. The apparatus includes a first member including a first connector; a second member including a second connector; a test signal output processing unit that outputs a first test signal to the first member and the second member; a first determination signal outputting portion that outputs a first determination signal in accordance with outputting the first test signal to the first member; and a second determination signal outputting portion that outputs a second determination signal in accordance with outputting the first test signal to the second member. The apparatus further includes a connector-connected state determination processing unit that determines the connected state of the first connector and the second connector based on the first determination signal and the second determination signal.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: September 27, 2005
    Assignee: Aisin AW Co., Ltd.
    Inventor: Yoshihiko Minatani
  • Patent number: 6944553
    Abstract: Systems, methods, and computer program products are provided that can facilitate providing test data for communications cables to remotely located customers. A customer accesses a server of a cable manufacturer via a client program executing on a client device. The server accepts entry of identification information for a communications cable (e.g., a unique identifier printed on the cable at predetermined intervals) via the remotely located client device. The server retrieves test data for the communications cable based on the entered information and provides the retrieved test data to the client device.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: September 13, 2005
    Assignee: CommScope Properties, LLC
    Inventor: Scott Jeffrey Minch
  • Patent number: 6941529
    Abstract: A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: September 6, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shivananda Shetty, W. Eugen Hill, Mehrdad Mahanpour
  • Patent number: 6937956
    Abstract: A testing unit is provided with a test data communication port adapted to output test data to a device being tested. The testing unit also has an expected test result data communication port adapted to output expected test result data to the device. The device being tested generates test result data in response to the test data, and compares the test result data with the expected test result data to generate test status data, such as a pass or fail indication.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: August 30, 2005
    Assignee: Intel Corporation
    Inventor: Baruch Schnarch
  • Patent number: 6934655
    Abstract: A method and system for performing sequence time domain reflectometry to determine the location of line anomalies in a communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over a channel that is the subject of the sequence time domain reflectometry analysis. The system monitors for and receives one or more reflections, collectively a reflection signal, and presents the reflection signal to a reflection processing module. In one embodiment, the reflection signal is correlated with the original sequence signal to generate a correlated signal. The system may perform signal analysis on the correlated signal to determine a time value between the start of the reflection signal and the subsequent points of correlation. Based on the time value and the rate of propagation of the signals through the channel, the reflection processing module determines a distance to a line anomaly.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: August 23, 2005
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Keith R. Jones, William W. Jones, Ragnar H. Jonsson
  • Patent number: 6931359
    Abstract: A method and apparatus for measuring one or more physical conditions of a computer operator and for automatically inputting signals corresponding to the physical conditions into a computer (12) for control and monitoring purposes.
    Type: Grant
    Filed: August 5, 2001
    Date of Patent: August 16, 2005
    Inventor: Ken Tamada
  • Patent number: 6928376
    Abstract: Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 9, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: John Anthony Rodriguez, Vijay Reddy
  • Patent number: 6920410
    Abstract: Disclosed are systems and methods for testing a network service. In one embodiment, a system and a method pertain to sending an initial request to the network service, redirecting a related request sent by the network service to an actual network service such that the related request does not reach the actual network service, emulating operation of the actual network service, and returning at least one response to the network service being tested, the at least one response being responsive to the related request.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: July 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Blaine R. Southam, David Christopher Davidson, Jay D. Knitter, Donna J. Grush, Terry M. Martin, Mark L. Sabiers
  • Patent number: 6914944
    Abstract: The invention pertains in general to the testing of the operation of radio and other data transmission apparatus. In particular the invention pertains to the testing of the operation of a digital radio apparatus on the basis of error statistics. In order to test functions relating to data transmission, a simulation system produces a pseudorandom bit sequence or some other test sequence which is packed into downlink frames and sent to the data transmission apparatus tested. In accordance with the invention, a known number of errors are generated in the test sequence. As the data transmission apparatus tested compares the received test sequence to the sequence it has produced, it detects the errors in the received sequence and compiles various error statistics, e.g., in the form of bit error ratio (BER) or frame erasure ratio (FER).
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: July 5, 2005
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Esa Nokkonen, Jussi Numminen, Markku Lintinen, Jukka Kinnunen, Juha Savolainen, Pekka Jokitalo
  • Patent number: 6907378
    Abstract: A test method for the detection of redundant tests and inefficient tests (RITs) used for testing integrated circuits (ICs) and a subsequent optimization of test complexity and test time duration. Empirical data from an execution of all tests of interest in a test plan, flow or suite of tests is collected. The empirical data is collected without stopping at errors. This empirical data is then used to determine the identity of one or more redundant and/or inefficient tests in the test plan. In order to reduce testing time and optimize the test flow, one of more of the following occurs. Redundant tests may be selectively removed, inefficient tests may be re-ordered to allow more efficient tests to be executed earlier in the test flow of the ICs, or some combination of this. RIT information is thus used to optimize the test flow, resulting in a reduction in test complexity and in test duration.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: June 14, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Susan Stirrat, Kang Wu
  • Patent number: 6904380
    Abstract: A test system (10) is coupled to a control system (20) in a manner which allows the test system to communicate with and drive the control system by sending and receiving signals via both the controller-I/O communication channel (160) and the field I/O connectors (225). The test system (10) is used to both simulate a plant to be controlled and to monitor, validate, and/or modify the internal state of the control system controller and possibly the control system I/O interface (220). Plant simulation is accomplished by simulating the I/O devices to which the control system (20) is coupled (and hence the plant processes) when installed in the operational environment. In addition to the simulation of I/O devices, the test system (10) takes advantage of the fact that many commonly used controller and I/O interfaces are capable of communication with other devices by using such communications ability to provide instructions to or obtain information from a control system's controller(s) and I/O interface(s).
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: June 7, 2005
    Assignee: Fluor Technologies Corporation
    Inventors: D. Dwight Brayton, Stephen G. Romero, Christopher S. Ghormley, Mark E. Dallas
  • Patent number: 6904381
    Abstract: A user interface is presented for a tester that tests a frequency converter having an input port, an output port and a local oscillator port. In a first area, a user can specify frequency for an input signal to be placed on the input port. In a second area, the user can specify frequency for a local oscillator signal to be placed on the local oscillator port. The tester calculates expected frequency values of an output signal on the output port output based on values entered in the first area and the second area.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: June 7, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Eric Alan Shank, Alan B. Sauls, Niels Jensen
  • Patent number: 6898542
    Abstract: A process control or safety system within a process plant uses one or more testing blocks to effect the timely and safe operation of on-line testing routines within field devices, such as valves, used in the process control or safety system. These testing blocks, which are easy to implement and to place in the process control or safety system, enable the periodic or on-demand testing of field devices to be integrated into the normal and on-going operation of the process control or safety system without causing scheduling or connection problems and without the need to rely on maintenance or other personnel, thereby providing better monitoring of the operational status of the field devices used within the process control and safety systems.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: May 24, 2005
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Michael G. Ott, Gary Law, Dennis Stevenson, Riyaz Ali, Mark Nixon, Tim Forsythe
  • Patent number: 6895563
    Abstract: The invention includes a main circuit board which is coupled by a 68 pin SCSI-2 connector to a National Instruments DAQ (PCI-6024E or equivalent) which resides in an expansion slot of a personal computer running National Instruments LABVIEW software which has been modified to include a custom communications driver. The main circuit board includes a communications module, a manual control module, a function generator, an analog I/O module, a current amplifier and frequency calibration module, and an address and status module. The main circuit board is also provided with a first edge connector for receiving a removable protection board which has a second edge connector for receiving a removable prototyping breadboard. The protection board protects the main circuit board and the DAQ from circuit faults on the prototyping breadboard. The main circuit board communicates with the DAQ via 8 digital I/O lines.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: May 17, 2005
    Inventors: Paul K. Dixon, Tim Usher
  • Patent number: 6895352
    Abstract: A simultaneous rapid open and closed loop bode measurement plot is described in which testing of the servo controlled instrument occurs under closed loop conditions using a binary pseudo-random sequence. The binary pseudo-random sequence is injected into the servo while the system under test is operating closed loop in order to generate bode plots for open loop and closed loop conditions. The present invention provides measurement results approximately 1,000 times faster than a swept sinusoid approach and provides superior dynamic range as compared to random white noise test input sources.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: May 17, 2005
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Robert H. Josselson, Joe P. Predina
  • Patent number: 6892154
    Abstract: A system and method for generating a test case for testing a device to be connected to a computer is disclosed. A base test object is provided. The base test object defines test properties for a device. The base test object includes a transaction generator that generates transactions. An extending test object is created, the extending test object defines test properties for a distinct configuration of the device. The extending test object also inherits at least one test property of the base test object. The transaction generator is executed to generate several transactions for the test case, each of the transactions defining a stimulus being specifically designed to stimulate at least one test property of the distinct configuration of the device.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: May 10, 2005
    Assignee: Adaptec, Inc.
    Inventor: Douglas Lee
  • Patent number: 6892155
    Abstract: A system and a general method estimate figures of merit based on nonlinear modeling and nonlinear time series analysis. Terms in a nonlinear behavioral model that depend on nonlinear combinations of a fixed input signal value are precomputed, optimizing the behavioral model such that figures of merit are evaluated from a single short stimulus vector. The optimized nonlinear behavioral model can then be applied to evaluate figures of merit for multiple devices under test (DUTs) in a manufacturing line. A process continually verifies and adjusts the nonlinear behavioral model based on sub-sampling multiple DUTs in a manufacturing line and comparing their figures of merit based on nonlinear modeling with those based on conventional measurement procedures.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 10, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin Gee, Nicholas B. Tufillaro
  • Patent number: 6890773
    Abstract: A method and an apparatus for sorting between actual and perceived errors related to processing of semiconductor wafers. A plurality of semiconductor wafers are processed. Fault data relating to the processed semiconductor wafers is acquired. A trend associated with the fault data is determined. A determination is made whether the fault data relates to an actual fault associated with the semiconductor wafers or to a calibration error, based upon the trend. A component is notified of the calibration error in response to the determination that the fault data relates to the calibration error.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: May 10, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Edward C. Stewart
  • Patent number: 6885960
    Abstract: A highly time resolved impedance spectroscopy that enhances the measurement of the dynamics of non-stationary systems with enhanced time resolution. The highly time resolved impedance spectroscopy includes an optimized, frequency rich a.c., or transient, voltage signal is used as the perturbation signal, non-stationary time to frequency transformation algorithms are used when processing the measured time signals of the voltage and current to determine impedance spectra which are localized in time; and the system-characterizing quantities are determined from the impedance spectra using equivalent circuit fitting in a time-resolution-optimized form. Methods and apparatus for processing impedance spectra data are also provided.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: April 26, 2005
    Assignee: Zyomyx, Inc.
    Inventors: Peter Wagner, Gerald Wiegand
  • Patent number: 6868309
    Abstract: A method and control system computing platform for a dialysis machine that uses Symmetric Multi-Processing (SMP) architecture. The SMP architecture tightly couples multiple (e.g., 2) independent processors by sharing memory between the processors. A single shared memory is used by both processors in order to facilitate communication between the processors and reduce cost by eliminating the expense of redundant memory. In this way, the two, or in general “N” processors, increase processor throughput by allowing the execution of N processes in parallel while without requiring extra memory and without having a single point of failure in the computer. In the event of a bus failure on the circuit card, the computer is reset using distributed hardware watchdogs. The watchdog reset signal is also sent to the hardware components of the dialysis machine in order to place the system in a safe.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 15, 2005
    Assignee: Aksys, Ltd.
    Inventor: Jamie Begelman
  • Patent number: 6868357
    Abstract: A frequency domain reflectometer that is in electrical communication with a cable under test in order to determine cable characteristics including cable length and load characteristics such as capacitance, inductance, resistance, impedance (which is characterized as an open or short circuit condition), and the location of an open or short circuit, wherein the FDR cable testing is performed in-situ when the system is installed at the time of installation of the cable to thereby enable testing of cable without having to remove it and risk damage, wherein FDR cable testing is performed passively so as not to interfere with normal operation of the cable even if the FDR cable testing system should fail, wherein a system is taught that can detect faults that are difficult to detect out of an operating environment, and wherein FDR cable testing is performed to detect cable fray conditions, wherein the cable may be grounded or coupled to air.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: March 15, 2005
    Inventor: Cynthia M. Furse
  • Patent number: 6853940
    Abstract: A device and method for detecting islanding of a grid connected inverter makes use of an injected white noise as a perturbing force on the output voltage of the inverter. The white noise is injected at least once in every cycle and can be generated at different rates in implementation. On loss of the grid, a frequency drift of the output voltage is detected and a positive feedback is activated that accelerates the drift.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 8, 2005
    Assignee: Ballard Power Systems Corporation
    Inventor: Anil Tuladhar
  • Patent number: 6853939
    Abstract: The winding testing unit provides systems and methods for determining normal and/or abnormal characteristic signatures of same-voltage windings residing in a device, such as transformer, without the need for a comparison to past historical data. A plurality of characteristic signatures [H(f)'s] are determined for each of a plurality of windings. A plurality of differential characteristic signatures [H(f)'s] are then determined from a plurality of H(f) pairs selected from the plurality of H(f)'s. The differential H(f)'s are compared and at least one significant asymmetry is identified between the differential H(f)'s.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 8, 2005
    Assignee: Georgia Tech Research Corporation
    Inventor: Larry T. Coffeen
  • Patent number: 6853930
    Abstract: In order to provide an operation and maintenance planning aiding system for a power generation installation which prepares an operation plan for a plurality of power generation units by making use of actual plant data and based on a total judgement including a variety of circumstances of the machine and apparatus or the parts thereof in the power generation units, in the system the plurality of power generation units 41, 42, 51 and 52, a power supply command center 3 and a service center 1 are arranged and connected via a communication network 6, the service center 1 obtains the plant data via the communication network 6 from the plurality of power generation units 41, 42, 51 and 52, calculates in real time a power generation efficiency of a concerned power generation unit for every plurality of power generation units 41, 42 51 and 52 by making use of the obtained plant data and design data of the concerned power generation unit and prepares an operation and maintenance plan for each of the power generation u
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: February 8, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Hayashi, Hidekazu Fujimura, Masao Furukawa, Katsuhito Shimizu, Yasushi Hayasaka
  • Patent number: 6847909
    Abstract: One embodiment comprises testing an electrical device using a combination of values of first and second parameters corresponding to a selected operating point comprising an origin of an R, ? polar coordinate plane; if the electrical device is determined to function in a passing manner at the selected operating point, updating the value of the polar coordinate R by incrementing the value thereof by a predetermined amount ?R; otherwise, updating the value of the polar coordinate R by decrementing the value thereof by ?R; if the updated value of the polar coordinate R is determined to be beyond an edge of a defined plot region, updating the value of the polar coordinate ? by a predetermined amount ??; and identifying an operating point corresponding to at least one of the updated values of the polar coordinates R and ?.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: January 25, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Christopher Todd Weller
  • Patent number: 6847916
    Abstract: A system and method for monitoring, diagnosing and/or testing a control network using portable, wireless equipment includes computerized display device connected to a wireless intermediary device for allowing a wireless connection to be made to a control network. The computerized diagnostic device may be embodied as a personal digital assistant (PDA) having a graphical screen display, on which may be displayed the network nodes and connections of the control network presented against a backdrop of a transit vehicle or other facility shown in three-dimensional, rotatable images. The wireless equipment may allow the operator to force individual system components to output states, and provide for real time monitoring. The portable, wireless equipment is programmed with information pertaining to the connections and locations of the components in the control network, thereby simplifying diagnosis or testing by the operator.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: January 25, 2005
    Assignee: I/O Controls Corporation
    Inventor: Jeffrey Ying
  • Publication number: 20040267476
    Abstract: A method for processing system test data is provided. The data is received in digital format in response to a system test and parsed to extract information relating to a system test site and a system component at the test site in need of maintenance. The parsed data is saved as new data to a previously populated database containing old data. The database is queried to compare the new data against the old data, and a report is generated that identifies a difference between the new data and the old data, thereby identifying a newly added data entry representative of a component in need of maintenance.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventor: Matthew Traye Kenerly
  • Publication number: 20040267477
    Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.
    Type: Application
    Filed: April 2, 2004
    Publication date: December 30, 2004
    Inventors: Michael J. Scott, Jacky Gorin, Paul Buxton, Eric Paul Tabor
  • Patent number: 6834259
    Abstract: The guard tour system of the present invention is comprised of a central computer which runs a computer program that enables a variety of electronic hardware components to function as the guard tour system. As a guard progresses through a guard tour, he or she uses a touch button reader to read information stored within a plurality of touch memory buttons located along the patrol route. At the end of the patrol, the guard places the touch button reader in a downloader that transfers the stored data to the central computer which processes the data and generates reports summarizing the patrol data. The computer program of the present invention provides a novel method of organizing security information in heirarchical categories. Further, the guard tour system of the present invention uses a novel method to determine the number of times a guard visited a location in a given time period.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: December 21, 2004
    Assignee: TimeKeeping Systems, Inc.
    Inventors: Barry Markwitz, Mike O'Flaherty, Jay Cross, Scott Boswell, Dean Chriss, Tom Dutton, Michael Gribov, Tom Morman, Jim Nicholson
  • Publication number: 20040243334
    Abstract: A test component and method of operation thereof are provided, the test component being arranged in a test environment to issue a test sequence over a bus to a device under test. A configuration file is provided to specify the behaviour of the test component, the configuration file comprising a plurality of regions with each region specifying attributes for use in determining the test sequence. A number of the regions specify constraint attributes defining allowable test sequences. The method of the present invention comprises the steps of: (a) when a test sequence is required to be issued, causing the test component to select, based on predetermined criteria, one of a number of regions provided by the configuration file; and (b) using the constraint attributes for that selected region to generate the test sequence to be issued on to the bus.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicant: ARM LIMITED
    Inventors: Christopher E. Wrigley, Daniel J. Coley, Andrew M. Nightingale
  • Publication number: 20040236529
    Abstract: The present invention provides a device for determining the dynamics of a tool sited in a CNC machine, as encapsulated by the Frequency Response Function. The device uses an actively controlled electromagnet to excite forces on the tool. The force is excited in a non-contact manner, allowing the force to be applied to both a stationary and a rotating tool. The displacement is measured by standard means, such as accelerometers, optical displacement or capacitance sensors. The ratio of the force and the displacement in the frequency domain is the Frequency Response Function. The force may be applied as a pure sine wave, providing the Frequency Response Function at the frequency of the sine wave. Varying the frequency of the sine wave provides the Frequency Response Function over the range of frequencies of interest. The control of the force profile is handled entirely by the automated controls and requires no special skills, training or manual interaction by the user.
    Type: Application
    Filed: March 19, 2004
    Publication date: November 25, 2004
    Inventor: Donald M. Esterling
  • Patent number: 6823280
    Abstract: A requirements database and test generator generates tests for functional and field testing and generates requirements documentation, user manuals, operational procedures, instrument data sheets, instrument indices, instrument loop diagrams, validation reports, and test reports, including exception and passing reports. A portable process control simulator (120) system which provides control system (900) users with scenarios that mirror field operation as defined.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: November 23, 2004
    Assignee: Fluor Corporation
    Inventors: D. Dwight Brayton, Paul G. Scharold, Shane R. Addleman, Christopher S. Ghormley, Mark Dallas, Eric D. Johnson, Stephen G. Romero
  • Publication number: 20040220764
    Abstract: An improved apparatus and method for tuning a device under test uses a spider diagram-like chart that provides the operator with visual cues as to the tuning status of a device under test (DUT). The spider diagram may be displayed on a graphical user interface (GUI), along with various adjustment points or potentiometers. The spider diagram includes a unit circle that represents the acceptable bounds for each measured parameter. Overlaying the unit circle is a polygon of three or more sides, with a vertex of each angle of the polygon representing a measured parameter. The polygon changes shape as the various potentiometers are adjusted. When a measured parameter value is at the center of its allowable range, the vertex of the angle corresponding to that measurement lies near the center of the unit circle. When a measured parameter is at its upper or lower bound, the vertex lies on the unit circle.
    Type: Application
    Filed: June 3, 2004
    Publication date: November 4, 2004
    Inventor: James Thomas Bachmann
  • Publication number: 20040220763
    Abstract: A test apparatus for testing an electric device includes a plurality of signal input-output units for inputting and/or outputting test signals in response to each of a plurality of terminals included by the electric device, a channel selection memory for storing pieces of channel selection information indicating whether each of the signal input-output units should perform setting based on a setting condition or not, a setting condition memory for storing the setting condition with regard to the signal input-output unit, and a controlling means for retrieving and supplying the setting condition stored in the setting condition memory and the channel selection information stored in the channel selection memory to the signal input-output units based on a setting instruction, when receiving the setting instruction to set the setting condition of the signal input-output unit, wherein when at least one of the signal input-output units is selected by the channel selection information supplied from the controlling mea
    Type: Application
    Filed: June 1, 2004
    Publication date: November 4, 2004
    Inventor: Takeshi Yaguchi
  • Patent number: 6810718
    Abstract: The present invention is an apparatus and method for analyzing a fluid used in a machine or in an industrial process line. The apparatus has at least one meter placed proximate the machine or process line and in contact with the machine or process fluid for measuring at least one parameter related to the fluid. The at least one parameter is a standard laboratory analysis parameter. The at least one meter includes but is not limited to viscometer, element meter, optical meter, particulate meter, and combinations thereof.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 2, 2004
    Assignee: Battelle Memorial Institute
    Inventors: Bary W. Wilson, Timothy J. Peters, Chester L. Shepard, James H. Reeves
  • Publication number: 20040204887
    Abstract: In automatic test equipment (ATE), the current state of all configurable hardware components is maintained in one or more status registers. A configuration interface operates between the ATE test program and the hardware components. The test program issues instructions for configuring the hardware components to the configuration interface, which considers the current configuration status of each hardware component stored in the status registers. When a hardware component is instructed to assume a specific configuration for a given task, the configuration interface compares the target configuration with the current configuration status and forwards the instruction only if they are different, i.e., if the current hardware configuration must be updated. The associated wait times for instructions issued where the target configuration matches the current configuration status are avoided, decreasing setup time.
    Type: Application
    Filed: March 28, 2003
    Publication date: October 14, 2004
    Applicant: Mitsubishi Electric & Electronics U.S.A., Inc.
    Inventor: Jay Klinck
  • Publication number: 20040199351
    Abstract: A process control or safety system within a process plant uses one or more testing blocks to effect the timely and safe operation of on-line testing routines within field devices, such as valves, used in the process control or safety system. These testing blocks, which are easy to implement and to place in the process control or safety system, enable the periodic or on-demand testing of field devices to be integrated into the normal and on-going operation of the process control or safety system without causing scheduling or connection problems and without the need to rely on maintenance or other personnel, thereby providing better monitoring of the operational status of the field devices used within the process control and safety systems.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 7, 2004
    Inventors: Michael G. Ott, Gary Law, Dennis Stevenson, Riyaz Ali, Mark Nixon, Tim Forsythe
  • Patent number: 6795788
    Abstract: Method and apparatus for discovery of operational boundaries for shmoo tests. Specifically, a method of testing operational boundaries is described in one embodiment of the present invention. The method discloses the discovery of an operational range for a hardware device over a plurality of varying operating parameters. The operational range is discovered by testing points, as defined by the plurality of varying operating parameters, to discover an operational boundary of the device. The operational boundary comprises a plurality of boundary points that lie just outside of the operational range of the device. The operational boundary is discovered automatically and without testing all of a plurality of interior operational points within the operational boundary.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: September 21, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul A. Thatcher, Gopikrishna Jandhyala