Circuit Simulation Patents (Class 703/14)
-
Patent number: 8473270Abstract: Software for controlling processes in a heterogeneous semiconductor manufacturing environment may include a wafer-centric database, a real-time scheduler using a neural network, and a graphical user interface displaying simulated operation of the system. These features may be employed alone or in combination to offer improved usability and computational efficiency for real time control and monitoring of a semiconductor manufacturing process. More generally, these techniques may be usefully employed in a variety of real time control systems, particularly systems requiring complex scheduling decisions or heterogeneous systems constructed of hardware from numerous independent vendors.Type: GrantFiled: October 23, 2007Date of Patent: June 25, 2013Assignee: Brooks Automation, Inc.Inventors: Patrick D. Pannese, Vinaya Kavathekar, Peter van der Meulen
-
Patent number: 8473269Abstract: Various approaches for co-simulating an electronic system design are described. In one approach, a hardware design function block in the design is instantiated, along with a specification of a software execution platform including external ports and software to execute on the platform. In response to a user instruction to import the software execution platform into the design, a software execution platform interface block is automatically instantiated. A first simulation model is generated from the hardware design function block and the software execution platform interface block and a second simulation model is generated from the software execution platform. The design is co-simulated using the first and second simulation models. Data is communicated between the first simulation model and the second simulation model via the interface block.Type: GrantFiled: February 27, 2007Date of Patent: June 25, 2013Assignee: Xilinx, Inc.Inventors: Jingzhao Ou, Roger B. Milne
-
Patent number: 8473882Abstract: A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.Type: GrantFiled: March 9, 2012Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Hari Mony, Viresh Paruthi
-
Patent number: 8473271Abstract: A lithography model uses a transfer function to map exposure energy dose to the thickness of remaining photoresist after development; while allowing the flexibility to account for other physical processes. In one approach, the model is generated by fitting empirical data. The model may be used in conjunction with an aerial image to obtain a three-dimensional profile of the remaining photoresist thickness after the development process. The lithography model is generally compact, yet capable of taking into account various physical processes associated with the photoresist exposure and/or development process for more accurate simulation.Type: GrantFiled: March 12, 2010Date of Patent: June 25, 2013Assignee: Synopsys, Inc.Inventors: Artak Isoyan, Lawrence S. Melvin, III
-
Patent number: 8471592Abstract: A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.Type: GrantFiled: December 13, 2011Date of Patent: June 25, 2013Assignee: Texas Instruments IncorporatedInventors: Paul G. Hlebowitsh, Robert A. Neidorff
-
Publication number: 20130158973Abstract: A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Inventor: Christopher E. Hsiong
-
Publication number: 20130158972Abstract: Disclosed are various embodiments for simulating distribution electric circuit models containing simulated software intelligent electronic devices. The distribution circuit and intelligent electronic simulator application facilitates the creation of user created software intelligent electronic devices. The software intelligent electronic devices imitate the operation of actual intelligent electronic devices on a power line. Communication between the software intelligent electronic devices and the automated recovery system can be captured using the distribution circuit and intelligent electronic device simulator application.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: Southern Company Services, Inc.Inventor: Malcolm Linn Fry, JR.
-
Patent number: 8468007Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.Type: GrantFiled: August 12, 2011Date of Patent: June 18, 2013Assignee: Google Inc.Inventors: Jean Baptiste Maurice Queru, Christopher L. Tate
-
Patent number: 8468005Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.Type: GrantFiled: August 12, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Thomas W. Aarts, Ched D. Hays, Michael C. Hollinger, Jason S. Ma, Jose L. Ortiz, Gundam Raghuswamyreddy
-
Publication number: 20130151225Abstract: A method for verifying a circuit is provided. A first portion of a simulation of the circuit is executed within a hardware description language (HDL) environment so as to generate a first data set. A tool (which is external to the HDL environment) is called using a system task within the HDL environment. The tool is then executed on the first data set to generate a second data set, and a second portion of the simulation of the circuit is executed within the HDL environment using the second data set.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: Texas Instruments IncorporatedInventor: Venkata Krishnan Kidambi Srinivasan
-
Publication number: 20130151226Abstract: By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.Type: ApplicationFiled: December 3, 2012Publication date: June 13, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: RENESAS ELECTRONICS CORPORATION
-
Patent number: 8463587Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.Type: GrantFiled: July 28, 2009Date of Patent: June 11, 2013Assignee: Synopsys, Inc.Inventors: Ningjia Zhu, James Bair, Zhishi Peng
-
Publication number: 20130144588Abstract: A spiral resonator is analyzed by modeling a set of loops of the spiral resonator with a model of a circuit including a set of units, wherein each unit includes a resistor and an inductor to model one loop of the spiral resonator. Values of the resistor and the inductor of each unit are based on properties of a corresponding loop. Electrical connection of the loops is modeled by electrically connecting the units in a corresponding order of the loops. A capacitive coupling in the spiral resonator is modeled by connecting adjacent units with at least one capacitor having a value based on the capacitive coupling between two corresponding adjacent loops. An inductive coupling in the spiral resonator is modeled based on inductive coupling between pairs of loops. The operation of the spiral resonator is simulated with the model of the circuit.Type: ApplicationFiled: March 27, 2012Publication date: June 6, 2013Inventors: Bingnan Wang, David Ellstein, Koon Hoo Teo
-
Publication number: 20130144589Abstract: Systems and methods for specifying, modelings simulating, and implementing a circuit design using a circuit design database comprising re-usable program elements to represent circuit design elements. The re-usable program elements may be used to build an overall circuit design description in the database. In example embodiments, the circuit design may be structured as a computer program and library to deterministically specify the circuit design elements to be used. Circuit synthesis functionality and circuit simulation functionality may be embedded as part of the re-usable program elements. Libraries may be compiled with the computer program instructions specifying the circuits to generate an executable that can be used for synthesis and simulation The combined executable code may be executed on an instruction set processor directly or through an interpreter.Type: ApplicationFiled: June 3, 2011Publication date: June 6, 2013Inventor: Delon Levi
-
Patent number: 8458544Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.Type: GrantFiled: December 2, 2011Date of Patent: June 4, 2013Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Hao-Jan Chao, Shianling Wu
-
Patent number: 8457943Abstract: Techniques for simulating a multiprocessor system. Aspects of the present invention are based on such an observation that most memory accesses from different simulated processors do not conflict, and therefore the conservative policy for performing synchronization of all the memory accesses can waste a large amount of processing time. By identifying possibly conflicting memory accesses and only performing synchronization of these memory accesses, the synchronization cost can be reduced considerably. Since the function simulator is able to operate faster and to perform the same memory accesses, the possibly conflicting memory accesses can be identified by first executing the function simulator.Type: GrantFiled: February 27, 2008Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Huayong Wang, Kun Wang, Honesty C. Young
-
Publication number: 20130138417Abstract: Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: Sigrity, Inc.Inventors: Jian LIU, Xiao Lin, Anyu Kuo, Jiayuan Fang
-
Publication number: 20130138248Abstract: Systems and methods are provided for controlling a multiple degree-of-freedom system. Plural stimuli are provided to a user, and steady state visual evoked response potential (SSVEP) signals are obtained from the user. The SSVEP signals are processed to generate a system command. Component commands are generated based on the system command, the plurality of components commands causing the multiple degree-of-freedom system to implement the system command.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Santosh Mathan, Kevin J. Conner, Deniz Erdogmus
-
Patent number: 8452441Abstract: The invention discloses a process quality prediction system and a method thereof. When a processing apparatus performs a process on a target, the process is measured by a measurement apparatus to receive a process value. The process value and several previous quality data collected from the measurement apparatus are used to predict the quality of the product which is processing inline. The method is composed of a moving window, a stepwise regression scheme and an analysis of covariance (ANCOVA). The drift and shift of process are overcome by the moving window. A key variable set is selected by the stepwise regression scheme and a virtual model is identified by the analysis of covariance.Type: GrantFiled: August 10, 2010Date of Patent: May 28, 2013Assignee: National Tsing Hua UniversityInventors: Shi-Shang Jang, Tain-Hong Pan, Shan-Hill Wong
-
Patent number: 8453078Abstract: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.Type: GrantFiled: November 9, 2011Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: David Goren, Ullrich R. Pfeiffer, Benny Sheinman, Shlomo Shlafman
-
Patent number: 8452581Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.Type: GrantFiled: May 5, 2009Date of Patent: May 28, 2013Assignee: Oracle America, Inc.Inventors: Krishnan Sundaresan, Pravin Chander Chandran
-
Patent number: 8452582Abstract: A method and system are provided for parametrically adapting a behavioral model pre-configured for a preset supply reference level to fluctuations therein. The behavioral model is adaptively scaled for deviation of the electronic system supply reference from its preset level. The scaling includes reconstructing a surrogate device parametrically representative of a portion of the behavioral model's undisclosed circuit. The reconstruction includes pre-setting a transistor type for the surrogate device, such that the surrogate device is configured with a conductive channel current-voltage characteristic of the preselected transistor type. Device-specific properties for the surrogate device are generated based on selective cross-correlation of operating points between the conductive channel current-voltage characteristic and V-t and I-V curves associated with the behavioral model.Type: GrantFiled: December 29, 2010Date of Patent: May 28, 2013Assignee: Cadence Design Systems, Inc.Inventors: Feras Al-Hawari, Taranjit Singh Kukal, Dennis Nagle, Raymond Komow, Jilin Tan
-
Patent number: 8453100Abstract: A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region.Type: GrantFiled: September 1, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Richard Q. Williams
-
Patent number: 8453081Abstract: A method for electrical design space exploration includes receiving a template for an electrical design. Design component parameters associated with at least one component in the electrical design are also received. Weighted factors are assigned to design complexity parameters of the electrical design. The parameters of the complexity can include at least one of following: whether the electrical design is known, a number of the design component parameters, a level of interaction among the design component parameters, a time constraint and a memory restriction of a simulation, and whether a statistical analysis or a worst case approach is used to analyze an output of the simulation. A simulation approach for design space exploration of the electrical design is selected based on the weighted factors for the parameters of the complexity of the electrical design. The simulation is performed based on the selected simulation approach.Type: GrantFiled: May 20, 2010Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Moises Cases, Jinwoo Choi, Bhyrav M. Mutnury, Caleb J. Wesley
-
Publication number: 20130132056Abstract: A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.Type: ApplicationFiled: May 13, 2011Publication date: May 23, 2013Inventors: Tadanobu Toba, Kenichi Shimbo, Hidefumi Ibe, Hideki Osaka
-
Patent number: 8447582Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.Type: GrantFiled: March 23, 2010Date of Patent: May 21, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Fumie Fujii, Sadayuki Yoshitomi, Naoki Wakita, Yuka Itano
-
Patent number: 8447581Abstract: During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.Type: GrantFiled: September 15, 2009Date of Patent: May 21, 2013Assignee: Xilinx, Inc.Inventors: David Roth, Hem C. Neema
-
Patent number: 8448109Abstract: Systems and techniques for evaluating assertions during circuit verification are described. During operation, m semantically equivalent assertions can be identified, wherein each of the m semantically equivalent assertions is evaluated using n logical expressions. Next, a set of vectors based on the m semantically equivalent assertions can be determined, wherein each vector element corresponds to a logical expression that is used for evaluating one of the m semantically equivalent assertions. The m semantically equivalent assertions can then be evaluated, in parallel, using the set of vectors.Type: GrantFiled: January 31, 2012Date of Patent: May 21, 2013Assignee: Synopsys, Inc.Inventors: Eduard Cerny, Surrendra A. Dudani, Samik Sengupta
-
Patent number: 8446224Abstract: A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.Type: GrantFiled: July 12, 2011Date of Patent: May 21, 2013Assignee: eSilicon CorporationInventors: Jordi Cortadella, Luciano Lavagno, Emre Tuncer
-
Patent number: 8447580Abstract: Methods and systems for modeling a multiprocessor system in a graphical modeling environment are disclosed. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements.Type: GrantFiled: May 31, 2005Date of Patent: May 21, 2013Assignee: The MathWorks, Inc.Inventor: John Ciolfi
-
Publication number: 20130124181Abstract: Method, system, and computer readable medium are disclosed for analyzing electrical properties of a circuit. The method may comprise: providing a network model including at least one network parameter, the network parameter being defined over a frequency range; converting the network parameter into an intermediate network parameter having first and second portions; identifying first and second frequencies defining a frequency sub-range; replacing the first portion of the intermediate network parameter with a DC value when a frequency associated with the intermediate network parameter is lower than the first frequency; replacing the first portion of the intermediate network parameter with a transitional value when the frequency associated with the intermediate network parameter is within the frequency sub-range; and converting the intermediate network parameter with the replaced first portion into an updated network parameter.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: Sigrity, Inc.Inventors: Jian LIU, Kaiyu MAO, Jiayuan FANG
-
Publication number: 20130124183Abstract: Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation.Type: ApplicationFiled: October 9, 2012Publication date: May 16, 2013Inventors: Gunnar Braun, Olaf Zorres, Achim Nohl, Andreas Hoffmann
-
Publication number: 20130124182Abstract: According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Kayser, Helmut Kohler, Norbert Schumacher
-
Patent number: 8443318Abstract: The junction comprising a stack of at least two magnetic layers, a first layer, for example a soft magnetic layer with controllable magnetization, and a second layer, for example a hard magnetic layer with fixed magnetization, the magnetization of the soft layer being described by a uniform magnetic moment, the dynamic behavior of the junction being modeled by an equivalent electrical circuit comprising at least two coupled parts: a first part representing the stack of the layers, through which a current flows corresponding to the polarized current flowing through said layers whose resistance across its terminals depends on three voltages representing the three dimensions of the magnetic moment along three axes, modeling the tunnel effect; a second part representing the behavior of the magnetic moment, comprising three circuits each representing a dimension of the magnetic moment by the three voltages, each of the three voltages depending on the voltages in the other dimensions and on the voltage across the tType: GrantFiled: December 16, 2008Date of Patent: May 14, 2013Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Centre National de la Recherche ScientifiqueInventors: Guillaume Prenat, Wei Guo
-
Patent number: 8439745Abstract: A system, apparatus, and method are disclosed wherein a reveal request is initiated through a result reveal station by a person (user) who has previously made some purchase or donation and has been assigned one or more sweepstakes entries in an assignment order from a set of available sweepstakes entries for a sweepstakes game. This reveal request represents a request to reveal one or more of the results associated with the corresponding sweepstakes entries that have been assigned to the user. The reveal station employs a game presentation including various graphics and audio effects to show sweepstakes results in an entertaining fashion. In response to the reveal request, or perhaps even prior to the reveal request, one or more sweepstakes entries are selected to be revealed for the reveal request. The sweepstakes entries are selected in an order different from the order in which the sweepstakes entries were assigned to the user.Type: GrantFiled: December 19, 2010Date of Patent: May 14, 2013Assignee: Multimedia Games, Inc.Inventors: Clifton E. Lind, Jefferson C. Lind, Brian A. Watkins, Eric W. Brown
-
Patent number: 8438000Abstract: Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between template instructions in the layout test template. The test is generated by a test generator which may simulate a state of a target computerized system executing the test. The simulation may be performed during generation of the test. The test generator may further verify previously generated instructions. The test generator may further generate instructions associated with leftover template instructions.Type: GrantFiled: November 29, 2009Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Yoav A. Katz, Ron Maharik
-
Patent number: 8437988Abstract: Methods, computer systems, and computer readable media are provided for simulation of a model of a system by detecting a violation of a cross condition while iteratively refining a first solution of a system of nonlinear algebraic equations at a current time point, and responsive to the detecting, predicting a crossing time step, projecting an initial guess for a second solution of the system of nonlinear algebraic equations at the crossing time point, and iteratively refining the second solution and the crossing time step by jointly solving an equation for the cross condition with the system of nonlinear algebraic equations as a coupled nonlinear system in which the crossing time step is treated as an unknown to compute changes to the second solution and the crossing time step in each iteration.Type: GrantFiled: June 26, 2009Date of Patent: May 7, 2013Assignee: Texas Instruments IncorporatedInventor: Gang Peter Fang
-
Patent number: 8438519Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.Type: GrantFiled: March 4, 2008Date of Patent: May 7, 2013Assignee: Texas Instruments IncorporatedInventor: Young-Joon Park
-
Patent number: 8438002Abstract: A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are converted into multiple numerical equations where each equation corresponds to a component in the system being simulated or a topology equation for the system model. Each numerical equation is numerically analyzed in order to identify illegal configurations in the system. Upon detection of an error, an error message listing the components associated with the illegal configuration is generated for the user.Type: GrantFiled: April 12, 2011Date of Patent: May 7, 2013Assignee: The MathWorks, Inc.Inventors: Joseph Daniel Kanapka, Nathan E. Brewton
-
Patent number: 8437870Abstract: System and method for implementing a VM APC platform are described. In one embodiment, the VM APC system comprises a process tool for processing a plurality of wafers, a metrology tool for measuring a sample wafer of the plurality of wafers and generating actual metrology data therefor, and a VM model for predicting metrology data for each of the plurality of wafers. The actual metrology data is received from the metrology tool and used to update the VM model. Key variables of the virtual metrology model are updated only in response to a determination that the VM model is inaccurate and parameters of the VM model are updated responsive to receipt of the actual metrology data for the sample wafer of the plurality of wafers. The system also includes an APC controller for receiving the predicted metrology data and the actual metrology data and controlling an operation of the process tool based on the received data.Type: GrantFiled: June 5, 2009Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Feng Tsai, Andy Tsen, Jin-Ning Sung
-
Patent number: 8438001Abstract: Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.Type: GrantFiled: May 7, 2008Date of Patent: May 7, 2013Assignee: International Business Machines CorporationInventors: Anita Natarajan, Ronald D. Rose, Sanjay Upreti
-
Publication number: 20130110488Abstract: A method for utilizing a physical device to generate processed data and a simulated device to output the processed data to the application program making the request. The simulated device is generated according to a simulated bus of the computer architecture, and comprises physical characteristics such as vendor identification (VID) and product identification (PID). When the simulated device is generated, the simulated device is perceived as a real physical device being installed, and the simulated device can be accessed by multiple applications at the same time.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Inventors: MingXiang Shen, ZhiQiang Zheng
-
Publication number: 20130110487Abstract: An unchecked signal detection mechanism runs simulation tests of circuit designs that normally pass. Before a simulation test is run, noise is injected into one randomly chosen signal. A random constant value is assigned to the randomly chosen signal. The constant random value is forced on the selected signal for the duration of the simulation test. Signals for which simulation tests always pass, even when their value is forced, are likely not checked and declared as suspect. The subset of suspect signals is then checked to determine whether their checkers are indeed missing or defective. Any verification flaws (holes) found are then fixed.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Mark A. Mostow
-
Patent number: 8434032Abstract: The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.Type: GrantFiled: November 19, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yun-Han Lee, Wei-Li Chen, Tan-Li Chou, Kheng-Guan Tan, Shi-Hung Wang
-
Patent number: 8433552Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.Type: GrantFiled: September 15, 2010Date of Patent: April 30, 2013Assignee: Renesas Electronics CorporationInventor: Kenta Yamada
-
Patent number: 8434045Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.Type: GrantFiled: March 14, 2011Date of Patent: April 30, 2013Assignee: Tabula, Inc.Inventors: Herman Schmit, Daniel J. Pugh, Steven Teig
-
Publication number: 20130103377Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.Type: ApplicationFiled: September 14, 2012Publication date: April 25, 2013Applicant: GOOGLE INC.Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
-
Patent number: 8429581Abstract: A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result.Type: GrantFiled: August 23, 2011Date of Patent: April 23, 2013Assignee: Apple Inc.Inventor: Fritz A. Boehm
-
Patent number: 8429592Abstract: A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor.Type: GrantFiled: October 20, 2011Date of Patent: April 23, 2013Assignee: Texas Instruments IncorporatedInventors: Yong Liu, Keith R. Green, Marie Denison, Yizhong Xie
-
Patent number: 8428928Abstract: A system for dynamically representing repetitive loads of a circuit during simulation includes a simulator module having one or more computer programs for 1) identifying one or more driver circuits for driving a plurality of repetitive receiver circuits, where each driver circuit has an output port and each repetitive receiver circuit has an input port, 2) creating a branch node driver for connecting the input ports of the plurality of repetitive receiver circuits and the output ports of the one or more driver circuits, 3) creating a shared load for representing aggregated input port loads of the plurality of receiver circuits having a substantially same isomorphic behavior, 4) creating a port connectivity interface for communicating changes of signal conditions between the output ports of the one or more driver circuits and the corresponding input ports of the plurality of repetitive receiver circuits, and 5) simulating the one or more driver circuits and the plurality of repetitive receiver circuits in accoType: GrantFiled: November 13, 2003Date of Patent: April 23, 2013Assignee: Cadence Design Systems, Inc.Inventor: Bruce W. McGaughy