Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.

Abstract: An equivalent circuit includes: a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second drain electrode, and a second source electrode electrically connected to the first drain electrode; and a charging and discharging circuit which includes a first capacitor having a terminal electrically connected to the second gate electrode and another terminal electrically connected to the second source electrode, and charges and discharges the first capacitor with predetermined time constants.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: A design support apparatus includes: a logical expression substitution unit to substitute a part of the logical expression, which includes a function expression of the design variables and a quantifier attached to the design variable, with a substitution variable; a quantifier elimination unit to generate a relational expression including the substitution variable and design variables without the quantifier by eliminating the design variable to which the quantifier is attached from the logical expression; a sampling point generation unit to generate a plurality of sampling points corresponding to the design variables and the substitution variable included in the relational expression; a possible range computation unit to compute, for each of the sampling points, a possible range that the relational expression may take, by calculating values of remaining design variables included in the relational expression based on the relational expression; and a possible range display unit to display the possible range.

Abstract: A system and method for determining satisfiability of a bounded model checking instance by restricting the decision variable ordering of the SAT solver to a sequence wherein a set of control state variables is given higher priority over the rest variables appearing in the formula. The order for control state variables is chosen based on an increasing order of the control path distance of corresponding control states from the target control state. The order of the control variables is fixed, while that of the rest is determined by the SAT search. Such a decision variable ordering strategy leads to improved performance of SAT solver by early detection and pruning of the infeasible path segments that are closer to target control state.

Abstract: According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.

Abstract: Improved equivalent circuits and circuit analysis using the same for a multilayer capacitor are provided. In one aspect, the equivalent series capacitance C and part of the equivalent series resistance R of a basic equivalent circuit for a multilayer chip capacitor are replaced with a capacitance CO, and capacitances Cm and C1 and the resistance Rc1 to take into consideration abnormal characteristics in electromagnetic distribution that occur at the corners and edges of the internal electrodes in the multilayer chip capacitor. In one aspect, additional circuit elements, such as resistances Rp1 and Rp2, the capacitance Cp, the inductances Lm and L1, and the resistance RL1, are provided to take into consideration the skin effects of the internal electrodes within the multilayer chip capacitor, electromagnetic proximity effects, losses and parasitic capacitance of the dielectric material, as well as parasitic inductance of the external electrodes.

Abstract: An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.

Abstract: The execution environment provides for scalability where components will execute in parallel and exploit various patterns of parallelism. Dataflow applications are represented by reusable dataflow graphs called map components, while the executable version is called a prepared map. Using runtime properties the prepared map is executed in parallel with a thread allocated to each map process. The execution environment not only monitors threads, detects and corrects deadlocks, logs and controls program exceptions, but also data input and output ports of the map components are processed in parallel to take advantage of data partitioning schemes. Port implementation supports multi-state null value tokens to more accurately report exceptions. Data tokens are batched to minimize synchronization and transportation overhead and thread contention.

Abstract: A computer-implemented method includes receiving an input containing a candidate netlist, a target, and a number, K, of cycles of interest, where K represents a number of cycles required to be analyzed for the proof-based abstraction. In response to receiving the inputs, a computing device builds an inductively unrolled netlist, utilizing random, symbolic initial values, for K cycles and provides the unrolled netlist with a first initial value constraint to a satisfiability (SAT) solver, with the first initial value constraint empty. The method includes determining whether a result of the SAT solver is satisfiable, and in response to the result not being satisfiable, performing an abstraction on the netlist and outputting the abstraction. However, in response to the result being satisfiable, the method includes performing one of: (a) outputting a valid counterexample of the original netlist; and (b) lazily adding initial value constraints to avoid spurious counterexamples.

Abstract: A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Abstract: A concurrent circuit simulation system simulate analog and mixed mode circuit using by exploiting parallel execution in one or more graphic processing units. In one implementation, the concurrent circuit simulation system includes a general purpose central processing unit (CPU), a main memory, simulation software and one or more graphic processing units (GPUs). Each GPU may contain hundreds of processor cores and several GPUs can be used together to provide thousands of processor cores. Software running on the CPU partitions the computation tasks into tens of thousands of smaller units and invoke the process threads in the GPU to carry out the computation tasks.

Abstract: Approaches for analyzing a power grid of an integrated circuit are described. In one embodiment, a method includes selecting at least one portion of the integrated circuit to be analyzed. A power grid model corresponding to the integrated circuit is retrieved from a database, and a first simulation of the programmable integrated circuit is performed. The first simulation generates a respective waveform of an electrical characteristic over time for each connection of a component within the selected portion to voltage supply or voltage ground. A simulation is performed of the power grid model using the respective waveforms as input stimulus for each connection in the selected portion.

Abstract: Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: In an embodiment, in a graphical modeling environment, users may create models that can be executed. Within the graphical modeling environment, users may use implicit iterator systems to manage multiple iterations of systems whereby the indexing of input and output signals may be defined by a user and state may be managed for an iteration. The number of iterations taken by the implicit iterator system can adapt to input and output signal dimensions.

Abstract: A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior.

Abstract: A property generation tool that automatically generates a property for a circuit design from a signal trace of the circuit design. The property generation tool receives a trace of a circuit design. The trace includes signal values for a number of signals of the circuit design over a number of clock cycles. Signal signatures are generated from one or more characteristics of the signal values. Sets of candidate signals are identified from the circuit design signals based on the signal signatures. One or more properties of the circuit design are generated based on the signal values associated with the sets of candidate signals. The property can be output, for example, for display to a user of the property generation tool. Examples of properties that are generated by the property generation tool include handshaking properties and fairness properties.

Abstract: Computer-implementable recursive summation algorithms are disclosed that are useful for efficiently performing recursive convolution, such as is often required in Statistical Signal Analysis (SSA) techniques. The disclosed recursive summation algorithms can be more computationally-efficient from both a speed and memory perspective than other recursive convolution techniques known in the prior art, such as the techniques relying on Fast Fourier Transforms (FFTs).

Abstract: A simulator includes an analysis module for extracting a state-space model of response of a physical system to an input from a frequency-domain representation thereof, using a SVD, and singular vectors thereof, of a Loewner matrix derived from the frequency-domain representation, and a simulator module for simulating the response of the physical system in the time domain based on the extracted state-space model.

Abstract: A system and method analyze reliability of an electronic device using a computing device. The method generates a component coding rule for components of the electronic device, establishes a BOM table for the electronic device according to the component coding rule, and generates component codes for the components according to the component data. The method further classifies the components into different component types according to the component codes, and calculates a failure rate for each of the components according to a parameter equation, obtains mean time between failures (MTBF) of the electronic device by calculating a sum of the failure rates of all the components. In addition, the method generates a reliability analysis report of the electronic device according to the MTBF of the electronic device. and outputs the reliability analysis report to an output device.

Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic designs. An improved approach for providing seamless interaction between analog and digital blocks during simulation, even if the digital blocks include complex types or models.

Abstract: The present invention allows a verification environment to be used to control and coordinate interaction with a design running on an accelerator or emulator without significant speed penalty. For example, an interface capable of communicating with test software running on an embedded processor is used to control and monitor the flow of data into the external interface of the design. Thus, a connection is made between the verification environment and the design under test running on the accelerator/emulator via a connection formed directly between the verification environment and embedded software running on the emulator for simulation and monitoring purpose at a very low frequency so that high-speed acceleration may still be achieved.

Abstract: A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.

Abstract: A circuit simulation apparatus is provided with a parameter calculating tool and a circuit simulator. The parameter calculating tool is configured to extract gate spacings between gates of a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding to a threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.

Abstract: Waveform analysis is performed to identify and characterize power-consuming devices operating on a building electrical circuit. Current waveforms are measured from the building circuit with electrical devices operating thereon. The waveforms are separated into wavelets and analyzed to identify a representative wavelet model which is transmitted to a server for analysis. The server compares the representative wavelet model to a predictive model built from waveform signatures of known electrical devices operating on a circuit. When the predictive model matches the representative wavelet model, the electrical devices contributing to the representative wavelet, their operating mode(s) (e.g., “on”, “off”, “paused”, “hibernating”) and/or their performance state(s) (e.g., normal operation, deterioration, or failure modes) can be identified. This information can be communicated as feedback to the consumer to facilitate more efficient and more cost-effective energy usage.

Abstract: A system, method and computer program product for modeling electronic circuits via a sparse solution, or a sparse representation of a recurrent single or multi kernel support vector regression machine is provided. In one embodiment, the sparse representation may be attained, for example, by limiting a number of training data points for the method involving support vector regression. Each training data point may be selected based on the accuracy of a non-recurrent or fully recurrent model using an active learning principle applied to the non-successive or successive (time domain) data. A training time may be adjusted, for example, by (i) selecting how often one or more hyperparameters are optimized; or (ii) limiting the number of iterations of the method and consequently the number of support vectors.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: As to a plurality of components in a system, a state transition path covering transitions defined by a behavioral specification of a component is specified to satisfy an input restriction of the component. Action sequences are acquired from the state transition path. By selecting a pair of components connected in the system, it is verified whether an output action sequence of a first component as one of the pair satisfies an input restriction of a second component as the other of the pair. If unsatisfied, the input restriction of the second component is relaxed to satisfy the output action sequence of the first component, or an input restriction of the first component is tightened to acquire a new output action sequence satisfying the input restriction of the second component. Above processing is repeated for each pair of components, so that output action sequences of one and the other of a pair satisfies input restrictions of the other and the one of the pair respectively.

Abstract: Embodiments of the present invention provide a method of computing validation coverage of an integrated circuit model, comprising: obtaining a logical structure of a integrated circuit model under validation; searching and recording signal paths in the integrated circuit model under validation based on the logical structure; and computing coverage of validation with respect to the signal paths. According to the technical solution as provided in the embodiments of the present invention, a signal path-based validation coverage may be obtained, thereby providing data regarding validation completeness more accurately.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to extract circuit-specific process/environmental corners that is yield-aware and/or specification-aware. Simulation data from previous Monte Carlo-based verification actions can be re-used.

Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

Abstract: A simulation system and method for generating equivalent circuits compatible with HSPICE reads data corresponding to N-port network system format in a storage device, and obtains S-parameter matrixes from the N-port network system. S-parameters in the S-parameter matrix that satisfy passivity are checked, and an interpolation algorithm to supplement S-parameters with passivity when some S-parameters not satisfy passivity is performed. Numbers of pole-residue, times for recursion and a tolerant system error of a rational function are generated for determining S-parameters. A rational function matrix composed of S-parameters is generated by performing a vector fitting algorithm, and an equivalent circuit is generated compatible with HSPICE format based on the generated rational function matrix.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A model for a silicon controlled rectifier includes three diode models connected in series, with the middle diode model being reverse biased. Each diode model corresponds to and can be configured to simulate DC operation of a junction in the silicon controlled rectifier. The model can be used to evaluate behavior of a circuit that includes the silicon controlled rectifier. For example, the circuit can include an electrostatic discharge protection circuit that includes the silicon controlled rectifier.

Abstract: A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.

Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Abstract: Provided is a distributed parallel simulation method. In the method, a plurality of local simulations is executed in parallel for a plurality of local design objects, respectively. The local design objects are included in a model at a specific abstraction level and are spatially distributed. At least one actual output is generated using at least one of the local design objects in a current local simulation of the plurality of local simulations. At least one expected output and the at least one actual output in the current local simulation are compared. Values of the at least one actual output and position information of the values from the current local simulation are transmitted to at least one remaining local simulation of the plurality of local simulations in response to a determination from the comparison that a difference exists between the at least one expected output and the at least one actual output.

Abstract: A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.

Abstract: Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion.

Abstract: A method for identifying an anomaly in an electronic system includes receiving, from a computer-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, each of the plurality of entries including information about simulation time. The method also includes, with one or more computer processors, determining time sequence relationship between pairs of entries selected from the plurality of entries and identifying allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship. The method includes receiving a second plurality of entries from a failed simulation test of the electronic system, each of the second plurality of entries including information about simulation time. The method includes analyzing the second plurality of entries and identifying one or more anomalies in the electronic system based on the analysis of the failed simulation test.

Abstract: Methods and systems are provided for modeling a multiprocessor system in a graphical modeling environment. The multiprocessor system may include multiple processing units that carry out one or more processes, such as programs and sets of instructions. Each of the processing units may be represented as a node at the top level of the model for the multiprocessor system. The nodes representing the processing units of the multiprocessor system may be interconnected to each other via a communication channel. The nodes may include at least one read element for reading data from the communication channel into the nodes. The node may also include at least one write element for writing data from the nodes into the communication channel. Each of the processing unit can communicate with other processing unit via the communication channel using the read and write elements. Code may be generated to simulate each node and communication channel in the modeled multiprocessor system.

Abstract: According to various techniques of the present invention, probability models for circuit simulation are generated as linear, piecewise linear, nonlinear, and/or continuous probability waveforms. These waveforms represent probability values for logic levels over some period of time. Probability models are defined according to characteristics of the electronic components being modeled, so as to capture variability in characteristics and performance of logic circuits and their components. The probability waveforms of the present invention can be used to predict circuit component behavior resulting from state changes; a range in response time can be indicated by a probability waveform indicating the probability that the response has taken place at a given time after an input state change. Construction of a probability model for a circuit with interconnected electronic components allows timing problems resulting from variability in component performance to be identified.

Abstract: A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.

Abstract: A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

Abstract: Techniques are presented for improving parametric yield. As part of an automatic sizing process for a circuit, one set of techniques receives a target value for a performance goal and then optimizes, with respect to the number of standard deviations, the distance by which the mean value of a distribution of the performance goal differs from the target value. In a second set of techniques, as part of an automatic sizing process during a circuit design process, the operation of the circuit is simulated to determine the distribution of a performance goal for a first design point. It is then determined whether a second design point is sufficiently close to the first design point and, if so, the simulation for the first design point is used for evaluating the second design point in an optimization process.

Abstract: A simulation apparatus includes a storage device that stores a block of circuit data including a clock gating circuit including a control circuit and a first latch circuit, wherein the control circuit outputs a control signal according to a clock, and wherein the first latch circuit holds or outputs a block of input data according to the control signal; and a processor that executes a program having a procedure. The procedure includes: generating a block of substitution circuit data by substituting the first latch circuit by a selection circuit and a second latch circuit; and performing simulation with respect to the substitution circuit data using a pulse related to the reference clock and the reference clock.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.