Abstract: An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

Abstract: An event-driven simulation is performed on an operation of data transmission from a source hardware element to a destination hardware element. Upon receiving a first request for transmitting first data at a first time-point, data stored in a storage area of the destination hardware element is saved as backup data in a memory, and the first data is stored in the storage area. A first time-period for transmitting the first data is measured from the first time-point. When a second request having a higher priority than the first request is received at a second time-point, a portion of the backup data is restored to the storage area so that the storage area stores third data estimated to have been transmitted to the destination hardware element. After a second time-period for the second request is measured, the first data is again stored in the storage area.

Abstract: According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.

Abstract: A system, method, and computer program for validating a rule set for applicable checks of a part, comprising querying a validation rule set; correlating a part data to said validation rule set; comparing a part against said part data; and whereby said part is approved at an event, and appropriate means and computer-readable instructions.

Abstract: In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.

Abstract: Disclosed herein are methods and devices used for the physical design validation of integrated circuits. One method used for the physical design validation of integrated circuits includes comparing the original circuit netlist of an integrated circuit and the layout data of the integrated circuit and assigning labels to the input and output terminals of the components in the integrated circuit based on the results of the comparison.

Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.

Abstract: A system and method to analyze analog, mixed-signal, and custom digital circuits. The system and method displays to a user characteristic values of a circuit and statistical uncertainty values of the characteristic values early in a sampling or characterization run of the circuit. The characteristic values and their statistical uncertainties are updated as the sampling or characterization run progresses. The user can halt the sampling or characterization run once a desired level of uncertainty is attained. The system can automatically halt the sampling or characterization run, once the statistical uncertainty lie within a pre-determined range.

Abstract: A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a fault-generating circuit are used, the multiplexer being realized using a relay technology, and the fault-generating circuit being implemented using a semiconductor technology.

Abstract: The invention relates to a product design support system for supporting product design business so as to design and develop a product in a short time.

Abstract: A system, method and software product emulate and profile an application playing on a mobile device. The mobile device is emulated using a model based upon characteristics related to performance of the mobile device. The application is played and monitored within the model to determine resource utilization of the application for the mobile device.

Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.

Abstract: A method to build a unified simulator for simulating a design on a parallel computing platform. The parallel computing platform comprises two or more (processors) cores which are deemed as an integral part of the unified simulator. The design is modeled in a high-level hardware description language. The design is first translated into a set of elements each comprising one or more simulation operations. Simulation operations from elements are next assigned, dynamically or statically, to one or more cores in a central processing unit (CPU) or in a multi-core system on the parallel computing platform to perform a parallel logic or fault simulation. Multiple (simulation) operation processing systems are used to process simulation operations in parallel. Simulation data in each element is managed to be self-contained so a fine-grained parallelism among multiple cores is achieved.

Abstract: A method for operating a computer system to generate a layout of a device and a computer-readable medium containing instructions that cause a computer system to carry out that method are disclosed. The computer system has a display that includes a display area. The computer system provides a list of objects and creates user selected objects from the list for inclusion in the display area. The computer assigns one of a plurality of operating modes for each connectivity object in the layout. The computer generates a Net assignment for each connectivity object that is not forced to have a specific Net assignment and for which automatic assignment of a Net is allowed. The computer generated assignment depends on the operating mode associated with that connectivity object. The operating mode of at least one of the connectivity objects can be altered by input from a user of said computer system.

Abstract: An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.

Abstract: An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel.

Abstract: A variable is allocated to a statement that designates an event associated with a function call in an assertion. Generation of the event at an arbitrary time on a continuous time series is detected, and a value corresponding to a meaning of the statement is assigned to the variable. Whether or not a condition corresponding to the meaning of the statement is satisfied is determined based on the value of the variable at each time on a discrete time series.

Abstract: A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.

Abstract: Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.

Abstract: Interactive and real time web-based electrical circuit symbolic solvers and simulators. The invention includes an interactive and innovative graphical user interface (GUI) for creating circuit schematics and generating netlists, circuits symbolic solving and instant simulated solutions, their systems and methods. Users such as students can use GUI interfaces to remotely access a remote server controlled by educational institutions such as universities, or electronic book publishers, in order to draw, symbolically solve, and instantly simulate electrical circuits.

Abstract: A method and a system for predicting shrinkable yield for business assessment of integrated circuit design shrink are provided. An assessment system is provided to determine cost benefits of a design shrink of an integrated circuit chip. A cost benefit analysis across different design shrink technologies is provided early in the process, so that business decisions regarding employment of design shrinks can be made as early as possible.

Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.

Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.

Abstract: According to some embodiments, a method is provided for simulating an analog and mixed-signal circuit design comprising an analog circuit segment connected to a digital circuit segment at a connection point, the method comprising: inserting a bi-directional interface element at the connection point, wherein the analog circuit segment connects to an analog port of the bi-directional interface element and the digital circuit segment connects to a digital port of the bi-directional interface element; and operating the bi-directional interface element such that the bi-directional interface element detects a signal direction and, according to the signal direction, either converts a first analog signal received from the analog port to a first digital signal for the digital port while maintaining a first signal strength of the first analog signal, or converts a second digital signal received from the digital port to a second analog signal for the analog port while maintaining a second signal strength of the second d

Abstract: An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

Abstract: A method for disclosing an integrated circuit embedded in a resin is disclosed. In one embodiment, stabilizing vias can be formed within the resin and can couple to corresponding pads in the integrated circuit. The stabilizing vias can be used in areas prone to failure when the combined resin/integrated circuit is stressed or undergoes some amount of displacement. In one embodiment, the stabilizing vias can be non-functional vias that do not carry electrical signals or power to or from the integrated circuit.

Abstract: A medium voltage drive for driving a motor of an electric submersible pump can include inverter circuitry that includes an output for output of power and a load filter connected to the output that includes inductors and capacitors that include inductance (L) and capacitance (C) values that determine a resonance frequency (fr) value within a range from approximately 750 Hz to approximately 1000 Hz according to the equation fr=(2?(LC)0.5)?1. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A system and method are provided for actuating static and dynamic analysis tools in parametrically intercoupled manner for synergistic optimization of an electronic system design. The system and method execute a timing designer process for selectively actuating the static analysis tool to conduct timing analysis based on at least one predetermined timing model and generate a plurality of estimated values for certain signal parameters to be in compliance with predetermined timing constraints. A signal exploration process is executed to receive the estimated values from the timing designer process and configure the resources of the dynamic analysis tool responsive thereto. The signal exploration process actuates the dynamic analysis tool to conduct electrical integrity analysis based on transient simulation and generate a plurality of simulated values for signal parameters. The simulated values are back annotated to the timing designer process for timing closure.

Abstract: A mechanism is provided for increasing the scalability of transformation-based formal verification solutions through enabling the use of phase abstraction on logic models that include memory arrays. The mechanism manipulates the array to create a plurality of copies of its read and write ports, representing the different modulo time frames. The mechanism converts all write-before-read arrays to read-before-write and adds a bypass path around the array from write ports to read ports to capture any necessary concurrent read and write forwarding. The mechanism uses an additional set of bypass paths to ensure that the proper write data that becomes effectively concurrent through the unfolding inherent in phase abstraction is forwarded to the proper read port. If a given read port is disabled or fetches out-of-bounds data, the mechanism applies randomized data to the read port data output.

Abstract: To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A method for automating input/output buffer information specification (IBIS) model generation. A wrapper utility combines components into an automated generation flow to model multiple input/output (I/O) buffers that conform to single-ended and differential I/O standards. Configuration data files are imported to properly configure the modeled I/O buffers according to a specific set of signal parameters across all process corners. Output and input termination impedance may also be modeled within the I/O buffer. A simulation setup file of the modeled I/O buffer is generated to determine the voltage/current (V/I) and voltage/time (V/T) data for the modeled I/O buffer for each process corner. A raw IBIS model is then created, formatted, and validated to determine the accuracy of the IBIS model. Execution steps of the IBIS model generator are then iterated to automatically generate, correlate, and compile IBIS models for each I/O standard into a single file.

Abstract: A method of parsing integrated circuit layout design data. According to some implementations, the segment boundaries are designated by first identifying data in the integrated circuit layout design data that matches a cell record start value. Next, the subsequent data is parsed, until a threshold amount of subsequent data has been parsed without identifying another cell record start value. When the threshold amount of subsequent data has been parsed without identifying another cell record start value, the next data in the integrated circuit layout design data matching a cell record start value is designated as a segment boundary. Integrated circuit layout design data can be segmented sequentially, or by using dyadic division. Once the integrated circuit layout design data has been broken up into segments, the segments can be provided to a parallel processing computing system for parsing in parallel.

Abstract: In one embodiment, a method to simulate an HDL specification is provided. For each call to a procedure, an intermediate process is dynamically created during simulation. The process containing the call to the procedure is replaced with the intermediate process in an active process list of processes scheduled for execution. The intermediate process is configured to call the procedure and, in response to completing execution of the procedure, cause the simulator to add the calling process to the front of the active process list and remove the intermediate process from the active process list.

Abstract: Methods herein provide for estimating a high frequency performance of a PCB via model through simulation. A via model is generated to include a representation of structures of a via, such as input and output pads, and input and output stubs. A signal path in the model is defined from an input pad of the model to an output pad of the model along a transmission line segment between the input pad and the output pad. Frequency dependent input impedance values at the input pad are generated based on one or more of the input pad diameter value, the output pad diameter value, the input stub length value, and the output sub length value. A high frequency performance of the via model is estimated based on the frequency dependent input impedance values at the input pad.

Abstract: A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

Abstract: Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t1, can be determined. The state at the first time, t1, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t1, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.

Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.

Abstract: A method of simulating an integrated circuit device under test (DUT) is provided, wherein the DUT includes a plurality of terminals. For each terminal of the DUT, a probe pulse is applied to the terminal and a reaction is recorded at the terminal and each of the other terminals to obtain values representative of reactive tails for the terminal. For each terminal, the values representative of the reactive tails obtained for the terminal are stored as an entry of a look-up table. Each entry includes n+x fields, wherein n represents a number of arguments in the entry and x represents a number of functions in the entry. For each terminal, a signal value at a selected time step is calculated.

Abstract: A model for simulating the electrical behavior of a thyristor includes a model of an NPN bipolar transistor whose emitter forms the cathode of the thyristor and the base forms a low-side control terminal of the thyristor, and a model of a PNP bipolar transistor whose emitter forms the anode of the thyristor and the base forms a high-side control terminal of the thyristor, the collector of the PNP transistor being connected to the low-side control terminal and the collector of the NPN transistor being connected to the high-side control terminal. The transistor models are present a small signal behavior over the entire range of anode currents of the thyristor, whereby the transistor models exhibit a gain drop when the anode current exits the small signal range.

Abstract: A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Abstract: A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of “majority gates” and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.

Abstract: A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch 10 is configured to be capable of switching states, according to control signals input to control terminals, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A first impedance circuit is arranged on a signal line for the control signal to be input to the positive-electrode control terminal. Furthermore, a second impedance circuit is arranged on a signal line for the control signal to be input to the negative-electrode control terminal.

Abstract: Aspects of the disclosure provide methods and systems for improving test generation using constraint solving problem (CSP) techniques. A test method can include modeling a circuit as logic constraints to correlate outputs of the circuit as logic functions of inputs of the circuit, pre-determining at least a value constraint that specifies a desired output value for an output of the circuit, and solving input values for the inputs to satisfy the logic constraints for the circuit and the value constraint of the output.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

Abstract: Systems and methods for simulation with dynamic run-time accuracy adjustment. In one embodiment, a first portion of a sequence of software instruction is simulated by a first simulation model, during a simulation. During the same simulation, a second portion of the sequence is simulated by a second simulation model. State information may be transferred from the first simulation model to the second simulation model. A change from simulating the first portion of a sequence of software instructions by the first simulation model to simulating the second portion of the sequence by the second simulation model may be made responsive to a computer-based determination of an advantage obtained by the change.

Abstract: A multiple programmable logic controller (PLC) simulation system is provided.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.