Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

Abstract: An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against expected events. Based on the comparison detecting at least one of the expected events being absent in the sequence chart, providing the optimal global quantum value as being smaller than the provisional global quantum value. Based on the comparison detecting no difference between the events in the sequence chart and the expected events, providing the optimal global quantum value as being larger than the provisional global quantum value.

Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

Abstract: Systems and methods offer an efficient approach to computing similarity rankings in bipartite graphs. An example system includes at least one processor and memory storing a bipartite graph having a first set and a second set of nodes, with nodes in the first set being connected to nodes in the second set by edges. The memory also stores instructions that, when executed by the at least one processor, cause the system to assign each node in the second set to one of a plurality of categories and, for each of the plurality of categories, generate a subgraph. The subgraph comprises of a subset of nodes in the first set and edges linking the nodes in the subset, where the nodes in the subset are selected based on connection to a node in the second set that is assigned to the category. The system uses the subgraph to respond to queries.

Abstract: In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on different design layouts and properties. Each group is associated with a corresponding threshold setting that is optimal for detecting defects in the inspection care areas belonging to that group. The assignment of the care areas to the different groups and the association of the different threshold settings with the different groups are noted in an index. This index is accessible during the analysis and used to ensure that each of the inspection care areas in a specific care area group is analyzed based on a corresponding threshold setting that is optimal for that specific care area group.

Abstract: The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Abstract: Technologies are generally provided to integrate hardware accelerators in datacenters. In some examples, a datacenter customer may provide a hardware accelerator configuration to be implemented at a datacenter. The hardware accelerator configuration may include, for example, one or more customer accelerator blocks and one or more accelerator blocks. The datacenter may retrieve the accelerator block(s), integrate the accelerator block(s) with the customer accelerator block(s) to form the hardware accelerator, and then implement the hardware accelerator. In other examples, the datacenter may charge the customer for use of the accelerator block(s), but refrain from providing the accelerator block(s) to the customer.

Abstract: Disclosed is a method for controlling the voltage of an electrical apparatus of a motor vehicle. The method includes the steps of measuring (E2) the voltage at the terminals of the apparatus and measuring (E3) the strength of the output current of the apparatus, calculating (E4) the values of resistance, inductance and capacitance of the equivalent circuit on the basis of the measured current strength and the measured voltage, comparing (E7, E8, E9) the calculated values of resistance, inductance and capacitance with the values of resistance, inductance and capacitance, respectively, stored in a storage area of the electronic control unit, and initiating (E12) an action if the difference between at least one of the calculated values and the corresponding stored value is above a predetermined threshold.

Abstract: When a communication unit of an FPGA receives emulated signals of a design under test that are to be transmitted to another FPGA, the communication unit analyzes each signal to determine whether a signal event has occurred for the signal. The communication unit transmits to the other DUT FPGA a packet indicating for which signals a signal event has occurred. Subsequently, the communication unit transmits a packet for each signal for which an event has occurred.

Abstract: Systems and methods are disclosed for routing messages to one or more of a plurality of user devices associated with a particular user to whom a particular message is to be provided. The message destination user device(s) may be determined by evaluating the user interactions on each of the plurality of user device. The message destination user device(s) may be selected as the user device(s) that are predicted to have a relatively high level of interaction and/or activity with the user to whom the message is to be provided or is in relative proximity of the user to whom the message is to be provided. When the message destination user device(s) are determined, the message may be transmitted to that/those message destination user device(s) for rendering to the user to whom the message is to be provided.

Abstract: According to an exemplary embodiment of the present disclosure, a method of generating a network-on-chip (NoC) in an electronic device includes clustering a plurality of cores based on total communication energy comprising first communication energy between a plurality of voltage-frequency-islands (VFIs) and second communication energy inside the plurality of VFIs.

Abstract: To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance in a way that emulates the bus behavior of a legacy device when executing the legacy application.

Abstract: A system for verifying applications for Real-Time Execution (RTE) devices is provided. The system includes a memory, at least one processor coupled to the memory, and a simulation component executable by the at least one processor. The simulation component may be configured to receive device simulation information for an RTE device, the device simulation information including device configuration information, application information, and targeted performance information, configure a virtual device simulator to simulate performance of the RTE device, run the virtual device simulator to process one or more simulated events, and output simulation results.

Abstract: A method includes determining a sampling region in a sample space, generating samples in the sampling region without generating samples outside the sampling region, and simulating a performance of a device using the generated samples as input data. The sample space is defined by a plurality of variables associated with the device. Values of the plurality of variables in the sampling region having lower probabilities to meet a specification of the device than values of the plurality of variables outside the sampling region. The method is performed at least partially by at least one processor.

Abstract: Embodiments relate to designing of integrated circuits using generation and instantiation of circuit stencils. The circuit stencil represents an abstracted version of the circuit segment. The circuit stencils include collapsed versions of the connectivity information of components and nodes of the integrated circuit. The collapsed version of the connectivity information is generated by analyzing functionality of the circuit segment and removing or replacing at least one redundant component or node of the circuit segment without modifying the functionality. The circuit stencil is used for instantiating or referencing components into a second integrated circuit.

Abstract: Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC.

Abstract: Disclosed is a method (or a system or a non-transitory computer readable medium) for recreating states of an embedded processing unit of a design under test (DUT). In one aspect, a host system configures an emulator to implement the DUT. The DUT includes the embedded processing unit and a memory unit. The host system configures the emulator to execute design instructions for testing an operation of the DUT through the embedded processing unit. The host system receives a stream of values stored by the memory unit of the DUT. The values indicate execution results of the design instructions executed by the embedded processing unit. The host system stores the stream of the values and generates a log file for recreating one or more states of the embedded processing unit based on the stored stream of the values.

Abstract: According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract: Method for testing multiple signal transceiver devices under test (DUTs), such as data packet signal transceivers, with a shared DUT testing resource, such as a tester having a single vector signal generator (VSG) and a single vector signal analyzer (VSA). Requests by the DUTs for access to tester resources (e.g., to receive signals from the signal generator or provide signals to the signal analyzer) are prioritized based upon tester availability and whether the requesting DUT requires sole access or can share access to the tester. If the tester is unavailable, DUT requests are queued according to their respective priorities to await tester availability. As a result, access to shared tester resources can be managed dynamically to minimize test time while testing multiple DUTs concurrently.

Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.

Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.

Abstract: A system for simulating a semiconductor device comprises a data input module configured to receive structural data of the semiconductor device comprising a first region and a second region, and a spatial discretization generating module configured to divide a space of the semiconductor device using the structural data through division of the first region into first type meshes and division of the second region into second type meshes different from the first type meshes.

Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl

Abstract: Techniques relate to an interactive logic diagnostic process. A diagnostic iteration loop is performed. When a critical failure does not have the diagnostic resolution that meets a predefined diagnostic resolution, potential faults related to the critical failure are isolated. When the critical failure has a diagnostic resolution that meets the predefined diagnostic resolution, the diagnostic iteration loop ends. Path focused fault test patterns are applied to the device under test in order to generate updated results of the path focused fault test patterns, such that the diagnostic resolution has been increased because a number of the potential faults related to the critical failure has decreased, and/or a size of a physical area of the potential faults related to the critical failure has decreased. The diagnostic iteration loop is returned to.

Abstract: A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.

Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.

Abstract: Methods and systems are disclosed related to region based device bypass in circuit simulation. In one embodiment, a computer implemented method of performing region based device bypass in circuit simulation includes receiving a subcircuit for simulation, where the subcircuit includes a plurality of devices, and determining node tolerance of the plurality of devices. The computer implemented method further comprises for each device in the plurality of devices, determining whether the device has entered into a bypass region using the node tolerance of the plurality of devices, performing model evaluation in response to the device has not entered the bypass region, and skipping model evaluation in response to the device has entered the bypass region.

Abstract: The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.

Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

Abstract: A method for a system to generate a recipe for performing wafer alignment, includes: generating first and second alignment data sets, the first alignment data set including image information regarding a first site on a wafer and coordinates of characteristic points at the first site, and the second alignment data set including image information regarding a second site different than the first site on the wafer and coordinates of characteristic points at the second site; and saving the generated first and second alignment data sets as a recipe for wafer alignment; wherein the generating of the first alignment data set includes: selecting, as the first site, a site including a characteristic pattern on the wafer; determining first and second characteristic points at the selected site; and recording coordinates of the determined first and second characteristic points.

Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Abstract: Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.

Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.

Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.

Abstract: A complementary gate driver on array circuit employed for panel display includes a plurality of GOA units that are cascade connected, in which an nth GOA unit controls charge to an nth horizontal scanning line G(n) in a display area and includes a pull-up circuit module, a pull-down circuit module, a pull-down holding circuit module, a pull-up controlling circuit module, a pull-down circuit module of an nth gate signal point Q(n), and a bootstrap capacitor. The pull-up circuit module, the pull-down circuit module, the pull-down holding circuit module, the pull-down circuit module of the nth gate signal point Q(n), and the bootstrap capacitor are respectively coupled to the nth gate signal point Q(n) and the nth horizontal scanning line G(n), and the pull-up controlling circuit module is coupled to the nth horizontal scanning line G(n).

Abstract: Methods and systems for emulating cable services delivery are disclosed. One system includes a conditional access network handler emulator comprising a conditional access network handler simulator addressable by one or more applications within an emulation environment. The conditional access network handler emulator also includes a library of conditional access configuration data accessible to a conditional access network handler simulator, the configuration data unassociated with a physical cable card.

Abstract: An integrated circuit design tool apparatus includes a processing resource configured to support a circuit simulator, a circuit sensitivity optimizer and a circuit sensitivity calculator. The circuit sensitivity optimizer is adapted to communicate to the circuit simulator a first dynamic list of selected devices of the circuit; and a second dynamic list of selected process parameters associated with the selected devices of the first dynamic list. The circuit simulator is configured to communicate to the circuit sensitivity calculator, a performance metrics of the circuit in response thereto. The circuit sensitivity calculator is configured to determine one sensitivity coefficient for each device of the first dynamic list in response thereto. The circuit sensitivity calculator is further configured to determine and communicate to the circuit sensitivity optimizer a variance of the performance metrics and also adapted to gradually determine whether or not to further communicate with the circuit simulator.

Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can correlate transactions captured during simulation of a circuit design to distributed states for multiple components in the circuit design. The computing system can identify at least a portion of the distributed states for the multiple components correspond to system level coverage events. The computing system can generate a graphical presentation to illustrate the portion of the distributed states for the multiple components in the circuit design that correspond to system level coverage events.

Abstract: A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the cache line. The cache memory includes an engine comprising one or more finite state machines. The processor also includes an interface to a bus over which the processor writes back modified cache lines from the cache memory to the system memory in response to encountering an architectural writeback and invalidate instruction. The processor also invalidates the state of the entries of the cache memory in response to encountering the architectural writeback and invalidate instruction. In response to being instructed to perform a cache diagnostic operation, for each entry of the entries, the engine writes the state and the tag of the entry on the bus and does not invalidate the state of the entry.

Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Abstract: According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.

Abstract: The invention relates to an electronic system comprising a plurality of circuit lines and an error detection component for detecting errors on and between the plurality of circuit lines, wherein each circuit line having a voltage different to ground level, the error detection component being adapted to perform a test routine comprising the steps of: —selecting one circuit line out of the plurality of circuit lines; —determining the voltage of the selected circuit line and storing the voltage value; —discharging the selected circuit line to ground level; —iteratively repeating the aforementioned steps of selecting a circuit line, determining and storing its voltage and discharging for further circuit lines; —comparing the stored voltage values associated with the respective circuit lines with a threshold value; and —generating an error indicator if at least one stored voltage value is below the threshold value.

Abstract: The present disclosure relates to a computer-implemented method for electronic design configuration reuse. The process may include providing an electronic design having one or more mixed signal configurations. The process may further include storing at least one digital configuration and at least one analog configuration at an electronic design database. The process may further include allowing the one or more mixed signal configurations to access the at least one digital configuration or the at least one analog configuration from the electronic design database.

Abstract: A method of manufacturing an aircraft. A plurality of documents, each comprising corresponding unstructured text and each being from a different source, is received at a processor, a particular document being in the plurality of documents. The particular document is selected by the processor based on a policy. The corresponding unstructured text for the particular document is converted by the processor into a structured language. The structured language is compiled by the processor into rules for a rules engine comprising software stored on a non-transitory computer readable storage medium. The rules for the rules engine are parsed by the processor into a set of rules. The aircraft is constructed according to the set of rules.

Abstract: The embodiments of the present disclosure provide a touch driving unit and circuit, a display panel and a display device. The touch driving unit comprises a shift control module, a selection module, a buffer module and an amplitude control module; the shift control module includes a start signal terminal, an output terminal and at least one clock signal terminal; the selection module includes a first input terminal, a second input terminal and an output terminal; the buffer module including an input terminal and an output terminal; and the amplitude control module including an input terminal and an output terminal. The embodiments of the present disclosure are used for display manufacturing.

Abstract: The present disclosure is related to a method for detecting and ranking hotspots in a lithographic mask used for printing a pattern on a substrate. According to example embodiments, the ranking is based on defect detection on a modulated focus wafer or a modulated dose wafer, where the actual de-focus or dose value at defect locations is taken into account, in addition to a de-focus or dose setting applied to a lithographic tool when a mask pattern is printed on the wafer. Additionally or alternatively, lithographic parameters other than the de-focus or dose can be used as a basis for the ranking method.

Abstract: A method for obtaining server-side and client-side calculations performed on a spreadsheet includes loading, on a client computer, a spreadsheet stored on a server and receiving an input from a user on the client computer, where the input causes a calculation of one or more cell values in the spreadsheet. The client computer performs the calculation of the one or more cell values on the client computer and sends the input to the server to perform the calculation of the one or more cell values on the server. The client computer then displays in the spreadsheet a result of the calculation of the one or more cell values to the user, where the result of the calculation is taken from the quicker of the calculation performed on the client computer or the calculation performed on the server.