Abstract: The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports at each interface between one or more sub-zones. Embodiments may further include receiving a selection for an electromagnetic (EM) solver for each of the one or more sub-zones. Embodiments may also include modeling each of the one or more sub-zones.

Abstract: Regression testing of software applications is described. Breakpoints are inserted in a programming code of an object to perform testing of all software applications that use the object. A processor in a computing device can receive data representing a programming code of a functionality of a software application rectifying a problem associated with the functionality of the software application. The processor can determine another software application executing the functionality. The processor can insert a breakpoint in the programming code of the functionality of the software application and the another software application. The breakpoint can be inserted at a location in the programming code of the software application where the problem was rectified. The processor can execute the programming code of the functionality including the inserted breakpoint. The processor can determine, based on the executing, whether the problem has been rectified in the software application and the another software application.

Abstract: An improved approach is provided to displaying waveform data, where a schematic and corresponding waveform data can be displayed directly on a schematic of an electronic circuit. By providing both the schematic and waveform results in a same display, circuit designers and verification engineers are given more control over their working environments and can more efficiently utilize available data including the schematic and the waveform data. Furthermore, results can be pinned to a relevant net to which those results correspond providing circuit designers and verification engineers with an ability to view only the available data they wish to view, and to do so in a context of the electronic circuit itself on the schematic.

Abstract: Systems and methods related to fast simulation of power delivery networks are described. A method is provided for simulating the time-domain responses of a plurality of points of a multi-layer power delivery network, comprising selecting a model of the power delivery network of a circuit, parsing the characteristic data describing the power delivery network, forming a circuit matrix relating to said circuit characteristic data, creating a preconditioner matrix with a specialized structure that allows solution by a Fast Transform solver, simulating the circuit using said circuit and preconditioner matrices by a computer, including a non-transitory computer readable storage medium and at least one processor, but preferably multiple processors, and reporting the responses at selected nodes and branches of the power delivery network.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: There are provided a method of inspecting the inspection area and an inspection system thereof. The inspection system comprises an inspection control unit operatively coupled to an inspection tool unit and to a recipe generating unit. The inspection control unit is configured to obtain the design data and the inspection recipe; to provide local segmentation of at least one inspection PoI comprised in an inspection image captured from the inspection area by the inspection tool unit, thereby obtaining inspection structural elements comprised in the at least one inspection PoI, the local segmentation is provided using segmentation configuration data specified in the inspection recipe; to identify one or more target structural elements and design structural elements corresponding thereto, identifying is provided using design association data specified in the inspection recipe; and to enable metrology measurements for the one or more target structural elements using the identified design structural elements.

Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process is provided. The process includes: generating a second characteristic model from a plurality of first characteristic models by using a maximum value and a minimum value of a prescribed parameter in the plurality of first characteristic models; executing simulation by using the second characteristic model; calculating a plurality of first margins for an evaluation item according to a result of the simulation; calculating a plurality of second margins for the evaluation item with respect to each of the first characteristic models; calculating a ratio of each of the plurality of second margins to a maximum margin of the plurality at first margins; and ranking the plurality of first characteristic models according to the ratio.

Abstract: A device verification system includes a device under test (DUT) including digital logic and a plurality of digital memories coupled to the digital logic; a plurality of hardware Verification Intellectual Property (VIP) modules coupled to the DUT to verify hardware of the DUT; and a plurality of software VIP modules coupled to the DUT to verify firmware of the DUT. A method for verifying the functionality of a device under test includes automatically developing code segments representing a series of firmware test patterns with a software Verification Intellectual Property (VIP) module; transferring code segments representing the series of firmware test patterns into a digital memory of a device under test (DUT) that includes digital logic; and monitoring the functional operation of the DUT as it uses the digital logic to execute the code segments representing the series of firmware test patterns stored in digital memory.

Abstract: Techniques are described for implementing one or more logical routers within a single physical routing device. These logical routers, as referred to herein, are logically isolated in the sense that they achieve operational and organizational isolation within the routing device without requiring the use of additional or redundant hardware, e.g., additional hardware-based routing controllers. The routing device may, for example, include a computing platform, and a plurality of software process executing within the computing platform, wherein the software processes operate as logical routers. The routing device may include a forwarding component shared by the logical routers to forward network packets received from a network in accordance with the forwarding tables.

Abstract: A method for automatically verifying validity of application of a refinement rule includes calculating a set of values that characterize a hierarchy of elements of the emulation. A currently calculated value for a first element at a first level of the hierarchy is compared with a previously calculated value that characterized the first element at a previous time. If the currently calculated value is the same as the previously calculated value, application of the refinement rule is determined to be valid for unnamed entities of the first element. If the currently calculated value is different from the previously calculated value, each currently calculated value that characterizes a lower level element at a lower level of the hierarchy is compared with a corresponding previously calculated value to identify a change and it is determined whether the change invalidates application of the refinement rule to an unnamed entity of the emulation.

Abstract: A method for designing a circuit element of an integrated circuit (IC) includes receiving one or more desired characteristics of the circuit element from user input and iteratively determining a design solution through one or more simulations and modifications using a rule-set. The one or more desired characteristics are combined with other preset characteristics of the circuit element or the IC. A first model of the circuit element is defined and simulated to calculate performance. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

Abstract: System, method and computer program product for allocating FPGA resources in a resource pool. In an embodiment, the technical solution includes: receiving resource request for FPGA resources in the resource pool from a client; performing resource allocation operation based on resource pool state information record in response to the resource request, the resource pool state information record including utilization state information of the FPGA in the resource pool; and updating the resource pool state information record based on the result of the resource allocation operation. FPGA resource allocation can be implemented with the adoption of the technical solution of the application.

Abstract: Method for testing a radio frequency (RF) data packet signal transceiver device under test (DUT) including detecting transitions between RF data packet signal transmission and reception by the DUT, detecting transitions between different RF data packet signal transmission operations by the DUT, and detecting transitions between different RF data packet signal reception operations by the DUT.

Abstract: The invention is directed to a method for discrete-event simulation, using dynamic memory in a parallel environment under Cautious Optimistic Control (COC). The method is divided into three sub-processes. The first is the pre-processing phase, which prepares the simulation for event execution. The second is the execution phase, which prepares the simulation for event execution. The third is the post-processing phase, which handles the cleanup of the simulation after the end of event execution. The invention can be integrated into various software architectures for run-time use or in post-processing analysis for data analysis in test and evaluation environments.

Abstract: Various embodiments are to a simulation platform with dynamic device model libraries and the implementation therefor. The simulation platform includes one or more servers hosting thereupon a database management system, a simulation frontend, and a simulation backend. The simulation frontend includes or is operatively coupled to one or more electronic design databases managed by a database management system, stored in a persistent storage device, and including design data in one or more domains across one or more design fabrics. The simulation backend includes or is operatively coupled to one or more simulators that perform simulations, analyzes, and/or optimizations for an electronic design by obtaining simulation inputs that are appended to the one or more electronic design databases or are stored in one or more separate data structures that are co-managed by the database management system.

Abstract: An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensembl

Abstract: A battery simulator can operate to provide different outputs. These outputs provide different characteristics related to how a device under test operates. In an example, a controller such as an electronic control module (ECM) or battery energy control module (BECM) can be tested. The battery simulator may provide different modes, e.g., a high current mode or a voltage change over time mode. A traction battery simulator may include a controller, analog output circuitry being controlled by the controller to output test current and test voltage, and switching circuitry connected to the analog output circuitry that has a first state and a second state. The first state is to provide an increased change in voltage over change in time relative to the second state. The second state is to provide an increased capacitance over the first state.

Abstract: Aspects of the present invention provide a system and method to estimate the amount of memory a harmonic balance analysis will require by measuring the memory allocated for a circuit database for a circuit undergoing harmonic balance analysis, determining the problem size of the harmonic balance analysis based on the information in the database, calculating the amount of memory for matrices, solution and auxiliary vectors needed for the harmonic balance analysis, and estimating the additional memory needed to complete a Newton iteration of the harmonic balance analysis using previously compiled statistical distributions. The total needed memory will be the sum of the measured, calculated, and estimated needed memory. A lower and an upper bound estimation of the total memory usage is provided. This information can be used by the circuit or system designer and/or an analysis or simulation tool for planning the computing resources necessary to execute the harmonic balance analysis.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

Abstract: Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC.

Abstract: A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values.

Abstract: A method detects hot spots from overlay error data for photolithography defined device(s). The overlay error data corresponds to data for sites on a substrate for the photolithography defined device(s). The overlay error data is converted to residual overlay data, which indicates a residual overlay error for each of the sites. The residual overlay error is based on an expected overlay error for each of the sites. It is determined whether group(s) of overlay error sites are present. Each group includes at least two nearest neighbor sites that have the residual overlay error greater than a threshold. For each group of overlay error sites, it is determined whether the group fits a physical model, such as the derivative of a Gaussian, for a hotspot. Each group fitting the physical model is categorized as a hotspot. Hotspot parameters are determined for each group that fits the physical model.

Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

Abstract: A calculation device for deriving solutions of a system of linear equations, which realizes a solution of the system of linear equations using an iterative method belonging to a Krylov subspace method, includes a plurality of arithmetic units. In the calculation device, a vector sequence xk (k is a natural number containing 0) approximating to the solutions of the system of linear equations is formed by a plurality of components in accordance with an order of the vector sequence xk, and when the vector sequence xk is divided into a plurality of different regions corresponding to the plurality of components and the respective arithmetic units are caused to execute arithmetic processings corresponding to the plurality of different regions in parallel in iterative computation of causing the vector sequence xk to approximate to the solutions, a preconditioned matrix that is used in the iterative computation is a diagonal matrix.

Abstract: Embodiments include a method, system, and computer program product for verifying a counter design. A method includes receiving a plurality of events within the counter design. The plurality of events can include a context event and a design event. The method also includes determining a tolerance window in response to the receiving of the context. The tolerance window is defined around the context event and includes a first portion before an occurrence of the context event and a second portion after the context event. The method further includes performing a verification algorithm to identify whether the design event is within the tolerance window and should be accounted for by a design model counter of the counter design.

Abstract: A method for designing an integrated circuit. The method may include obtaining a register-transfer level (RTL) file for the integrated circuit. The RTL file may include hardware description language code that describes various modules for the integrated circuit. The method may further include selecting, within the RTL file, various state elements having a predetermined clock skew. The method may further include associating, in response to selecting the state elements, the state elements with a predetermined clock header. The method may further include generating a gate-level netlist using the RTL file. The state elements may be assigned to the predetermined clock header in the gate-level netlist. The method may further include generating, using the gate-level netlist, a clock network for the integrated circuit. The state elements in the clock network may have the predetermined clock skew.

Abstract: Systems and methods are provided for analyzing a via. A physical representation of a via intersecting with an upper layer and a lower layer is received, the physical representation comprising: (i) a pair of pad dimensions comprising an upper pad dimension a1 and a lower pad dimension a2, and/or (ii) a pair of anti-pad dimensions comprising an upper anti-pad dimension b1 and a lower anti-pad dimension b2, where at least one of first and second conditions: (A) the first condition being a1 is different than a2, and (B) the second condition being b1 is different than b2, is true. A determination is made as to which, if any, of the conditions are true. At least one model parameter is selected based on the determination. An admittance parameter corresponding to a section of the via located between the upper and lower layers is computed using the selected model parameter.

Abstract: Systems and methods are provided for generating an equivalent circuit model. RLGC parameters representing a segment of a layered structure of a specified length are received. The layered structure includes two conductors (also called planes) and at least one trace or a transmission line located between the two conductors. An admittance matrix corresponding to the segment is computed based at least in part on the received RLGC parameters. One or more loading parameters representing a loading of one of the two conductors due to the trace or traces are also computed, and a segment circuit model for the segment of the layered structure based at least in part on the admittance matrix and the one or more loading parameters.

Abstract: Methods and systems for setting up a wafer inspection recipe are provided. Inspection results produced by complete wafer inspection recipe candidates, each of which includes one or more optical mode candidates with at least one set of defect detection parameters, are compared to determine which of the complete wafer inspection recipe candidates is the best for use as the wafer inspection recipe. The method does not involve making any decisions regarding performance of the complete wafer inspection recipe candidates until after the inspection results have been compared. In other words, the method does not involve selecting optical mode(s) that will be used in the wafer inspection recipe followed by selecting the defect detection parameters for the selected optical mode(s). In this manner, a greater number of optical mode and defect detection parameters can be considered in an efficient manner to determine the best wafer inspection recipe for any given wafer.

Abstract: A system level simulation wrapper includes a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication. The system also includes a switch coupled to the plurality of port interfaces. The switch is selectively configured to communicate with a Cycle Accurate hardware description language (HDL) model of an intellectual property (IP) block or a system level model of the IP block.

Abstract: A computer implemented method of preserving functionality in a computer program by generating customized mock inputs may include identifying a set of functionalities of the computer program, where a first functionality has a first input, and a second functionality has a second input. The method may also include determining a first and a second constraint respectively on the first and second inputs, where the first constraint defines a set of values of the first input which enables the first functionality, and the second constraint defines a set of values of the second input which enables the second functionality. The method may then include generating a constraint satisfaction problem including the first and second constraints, and determining whether a tuple of mock input values exists that satisfy the constraint satisfaction problem. The method may additionally include providing the tuple to the computer program as the customized mock inputs.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.

Abstract: A system, method and computer program product for determining correlation coefficient(s) among different field effect transistor types for a same electrical parameter type and/or among different electrical parameter types for a same field effect transistor type. The correlation coefficient(s) are determined based on the results of a limited number of simulation runs. Specifically, the number of simulation runs required by the disclosed embodiments is limited to one plus the product of the number of different field effect transistor types at issue, the number of different electrical parameter types at issue and the number of statistical process parameter types that impact the different electrical parameter types. Such correlation coefficient(s) can subsequently be used to develop a compact model of a semiconductor process technology. This compact model can then be used to perform variation-aware design of an integrated circuit chip.

Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

Abstract: Multiple parallel slave processes and a master process are assigned to a node executing an operating system such that the operating system maintains a ready queue comprising a list of one or more processes that are ready to be executed by at least one processing core. A parallel slave process takes an action that causes the operating system to keep the parallel slave process out of the ready queue. Based on receiving an indication that the parallel slave process is to be kept out of the ready queue, the master process sets the parallel slave process to a blocking state, selects a second parallel slave process that is in a runnable state but is currently kept from being in the ready queue, and takes an action that causes the operating system to add the parallel slave process that is in the runnable state to the ready queue.

Abstract: Implementations of the present disclosure involve methods and systems for modeling input capacitance for a component of an electronic circuit design to accurately and quickly analyze the performance of the circuit. In particular, the methods and systems may provide for an estimated input capacitance for one or more transistor components of the circuit. To determine the estimated input capacitance of a transistor, a computing system may obtain technical information about the circuit and determine one or more virtual nets that include connections between the adjusted transistor and other transistors (or other components) of the circuit design. This information may be utilized by the computing system to calculate an estimated input capacitance for the adjusted transistor of the circuit design. The calculated input capacitance of the transistor may be added into a simple simulation of the circuit design to obtain one or more operational parameters or circuit performance characteristics.

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract: A measuring apparatus includes an optical image input unit to input optical image data of a figure pattern obtained by a pattern inspection apparatus, which inspects defects of a pattern on a target object to be inspected by scanning an inspection region of the target object, from the pattern inspection apparatus, a design data input unit to input design data of the pattern on the target object, a reference image generation unit to generate reference image data to be compared with the optical image data, by performing image development of the design data, a positional deviation distribution generation unit to generate positional deviation distribution by measuring a positional deviation amount of the pattern on the target object, by using the optical image data obtained from the pattern inspection apparatus and the reference image data having been generated, and an output unit to output generated positional deviation distribution of the pattern.

Abstract: Computer-implemented methods and systems are provided. The system includes a data store that is configured to store events in an event table, a temporary events file storage system (TEFSS), and a cluster of application servers. The cluster includes a first application server that generates events, and a second application server that includes an events file uploader service. When the first application server is unable to directly write events to the data store, an indirect events writer generates events file(s), and writes the events file(s) to the TEFSS. Each events file includes a plurality of events flushed from an in-memory buffer service at the first application server. When the events file uploader service determines that the first application server is inactive, it reads the events file(s) from the TEFSS, and writes the events from each of the events files to the data store.

Abstract: A system and method optimizes hardware description generated from a graphical program or model having oversampling constraints automatically. The system may include a streaming optimizer, a resource sharing optimizer, a delay balancing engine, and a global scheduler. The streaming optimizer may transform vector data paths to scalar or smaller-sized vector data paths. The resource sharing optimizer may replace multiple, functionally equivalent blocks with a single shared block. The delay balancing may insert one or more elements to correct for data path misalignment. The global scheduler may place portions of the program or model into conditional execution sections and create control logic that controls the model sample times or steps that the portions are enabled. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from a modified version of the model that is created.

Abstract: In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.

Abstract: A circuit diagram supplying apparatus 10, for supplying a user with whole contents of an device system circuit diagram, then requests a server 30 for first-of-all transmission of part-connection-drawing overall circuit diagram data in which connection diagrams LSd are added to a part placement diagram included in the circuit diagram and having electrical component parts PSd arranged therein. Then, after displaying a part-connection-drawing overall circuit diagram based on the transmitted and received part-connection-drawing overall circuit diagram data, the circuit diagram supplying apparatus 10 requests the server 30 for sequential transmission of circuit-element-drawing divisional circuit diagram data (a)-(e).

Abstract: Embodiments are disclosed for analyzing data storage devices. The present disclosure employs a “canary” test that selects multiple storage devices and tests the same for a predetermined period of time. By analyzing the statuses of the storage devices monitored and recorded during the applicable tests, the present disclosure can generate an analytical result regarding the characteristics of the storage devices. The analytical result can be presented to an operator in a meaningful way so as to enable him or her to make an informed decision when utilizing a storage device with characteristics similar to the tested storage devices.

Abstract: A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors associated with the initial plurality of random walks for each of the regions. Results from the random walks are averaged to estimate parasitic capacitance of the origin net. The method may include performing the random walks for each region in pairs, wherein a first random walk of the pair is selected in accordance with an anti-symmetric probability function, and a second random walk of the pair is antithetic to the first random walk of the pair.

Abstract: A device receives an initial model of a system and information that identifies a solving technique to be used to solve a mathematical problem associated with the initial model. The initial model includes an initial transfer function that describes a relationship between an input to and an output from the system. The device determines an error associated with the solving technique, resulting in an inaccurate solution to the mathematical problem. The device generates an adjusted model, based on the initial model and the error, that includes an adjusted transfer function, based on the initial transfer function, or an adjusted input to the system, based on the input to the system. The device applies the solving technique to the adjusted model, to generate a result that includes a more accurate solution to the mathematical problem than applying the solving technique to the initial model, and outputs or stores the result.

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract: The present invention discloses a digital integrated circuit simulation method and simulator. The method comprises: obtaining a circuit diagram of the digital integrated circuit and a checkpoint in the circuit diagram; determining a point relevant to a boundary between a two-value simulation and a multi-value simulation in the circuit diagram and a state of the relevant point according to the checkpoint; determining a boundary position, as well as a boundary type of the boundary position, of the boundary between the two-value simulation and the multi-value simulation in the circuit diagram according to the relevant point and the state of the relevant point; inserting a conversion circuit at the boundary position according to the boundary type of the boundary position; and modeling and simulating the circuit diagram into which the conversion circuit is inserted. The method and simulator can reduce simulation time and the needed storage resources.

Abstract: A method of configuring a system includes a selectable analog output device and an analog front end (AFE). The method includes selecting, via a graphical user interface (GUI), an analog output device that provides an analog output signal, the selected device having predetermined characteristics. The method further includes selecting an operating condition for the system and a performance criterion for the system. The method also includes providing a configuration value for programming the AFE based on the selected operating condition and performance criterion.