Abstract: A control system includes: a master station including a PLC executing user program; and a remote station including a communication memory to which a PLC device is assigned, a slave communication unit, and a unit to or from which one or more pieces of data is input or output, and being connected to the master station through a network. The PLC transmits, to the slave communication unit, assignment object designation information designating an object that is among unit data input or output to or from the unit and to which a PLC device is assigned, and an assignment rule. The slave communication unit assigns unit data that is among unit data input or output to or from the unit and is designated by the received assignment object designation information to the communication memory based on the received assignment rule.

Abstract: A system, method and non-transitory computer-readable medium utilize an equivalent circuit model in which electrostatic capacitance changes in response to an arbitrary DC bias voltage applied to a capacitor from the outside. The equivalent circuit model includes a capacitor equivalent circuit section composed of a base circuit and a multistage circuit, a reference current generator section that calculates a reference current, a multiplying factor generator section that calculates a multiplying factor, and a current source current generator section that generates a current of the current source based on the reference current and the multiplying factor. The multiplying factor generator section generates a voltage of an nth-degree polynomial corresponding to the DC bias voltage when applying the DC bias voltage, and defines a current to be generated when the generated voltage is applied to a resistance as the multiplying factor.

Abstract: Disclosed is a printed circuit board (PCB) having backdrill reliability anchors comprising nonfunctional pads to provide mechanical reinforcement for signal pads on backdrilled plated through hole (PTH) vias, as well as associated method and machine readable storage medium.

Abstract: A primitives library facilitates compiling, linking, and execution of programs that use specialized processors to perform primitive tasks. Data associated with a primitive may be accessed by a specialized-processor-based storage node manager independently of any other processing device.

Abstract: One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

Abstract: Performing RC analysis in a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; obtaining hierarchical RC information; combining RC information on boundary paths between blocks and RC information on boundary paths within blocks to generate boundary RC information; performing RC analysis using the boundary RC information to determine a timing delay; and comparing the timing delay with a desired delay to determine whether an RC timing is closed.

Abstract: An approach includes deriving an uplift factor as a function of a width of the device for each leakage current component based on an amount of uncorrelated random variations in the leakage current component for one specific width and using the uplift factor as a multiplier for the leakage current component. The approach includes using the uplift factor for sub-threshold drain current as a multiplier of the sub-threshold drain current so that a lowering of nominal threshold voltage of the device occurs in a single simulation run. The approach further includes deriving a threshold voltage mismatch expression related to an amount of an uncorrelated random variation in sub-threshold drain current which is not directly inversely proportional to a square root of the width. The uplift factors and the threshold voltage mismatch expression within a model are used to predict statistical characteristics of the leakage current.

Abstract: A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped.

Abstract: An apparatus and method for identifying an optimal harmonic number of a circuit are disclosed. In a simulation of the circuit, a periodic input waveform up to a particular number of periods is applied to the modeled circuit and an output waveform is obtained in response. In response to detection of a steady state response of the output waveform, embodiments simulate the circuit by applying an additional period of the periodic input waveform and obtaining the output waveform corresponding to the additional period of the periodic input waveform. A time domain power value and a frequency domain power value are calculated using the output waveform corresponding to the additional period of the periodic input waveform. Embodiments detect a harmonic of the output waveform corresponding to the additional period of the periodic input waveform at which the time domain power value and the frequency domain power value converge with each other.

Abstract: A test case for the application under test is determined for the quality assurance application where results for a test case can be received from a user. An interface is displayed to allow the user to enter a pass or fail indication for a manual test that has been performed for the test case. If a pass indication is received for the test case, the test case is marked as passed. Also, in response to receiving the pass indication for the test case, a plurality of steps for the test case are automatically marked as passed. If a fail indication is received for the test case, a request for the user to identify a step that failed the manual test is output. When the response indicating which step failed is received, that step is marked as failed.

Abstract: An online system transmits third-party content originating from a third-party system to a client device. The third-party content includes a pointer to a third-party application associated with the third-party system. When the client device receives an interaction with the third-party content from a user of the client device, the client device executes the third-party application and generates an attribution identifier from which the user's identity cannot be determined. The attribution identifier is transmitted to the online system. Subsequently, the client device determines information describing interactions by the user with the third-party application that is transmitted to the third-party system along with the attribution identifier.

Abstract: A computing device for a generating composite view for an intellectual property (IP) core may obtain constraints for multiple application specific integrated circuits (ASIC) designs in which the IP core is used; and determine composite constraints for the IP core based on the constraints for the multiple ASIC designs. The composite constraints may be within all constraints for the multiple ASIC designs. A freedom of change to update the particular IP core may be identified based on the composite constraints.

Abstract: A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.

Abstract: Methods and systems for providing an emulation session to emulate a computer product for a host device. A method and system involve providing a communication link between the host device and an emulation bridge module provided on an emulation server separate from the host device; providing a host resource library file including a list of the plurality of resources available on the host device to the emulation bridge module; operating the emulation bridge module to determine emulation session resources required to provide the emulation session; selecting at least one of the host device and the emulation server for providing each required emulation session resource in the emulation session resources required to provide the emulation session; and providing the emulation session using the required emulation session resources provided by at least one of the host device and the emulation server.

Abstract: Techniques are described for implementing one or more logical routers within a single physical routing device. These logical routers, as referred to herein, are logically isolated in the sense that they achieve operational and organizational isolation within the routing device without requiring the use of additional or redundant hardware, e.g., additional hardware-based routing controllers. The routing device may, for example, include a computing platform, and a plurality of software process executing within the computing platform, wherein the software processes operate as logical routers. The routing device may include a forwarding component shared by the logical routers to forward network packets received from a network in accordance with the forwarding tables.

Abstract: A semiconductor device capable of easily and properly detecting a defective element unit(s) and a quality management method for the semiconductor device are suggested. A semiconducting device simulating interactions between nodes in an interaction model is equipped with a quality management unit for managing the quality of each element unit provided corresponding to each node, wherein the quality management unit executes a specified quality test of each element unit, compares test results of the quality test with pre-given results to be obtained from the quality test, and detects a defective memory cell(s) and a defective element unit(s) based on the comparison results.

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.

Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.

Abstract: Methods and circuits for superclocked operation of a plurality of functionally-equivalent logic circuits are disclosed. One of the plurality of functionally-equivalent logic circuits is selected according to a selection algorithm. In response to selecting one of the plurality of functionally-equivalent logic circuits, superclocked operation of the selected one of the plurality of functionally-equivalent logic circuits is enabled. Superclocked operation of other ones of the plurality of functionally-equivalent logic circuits is disabled. The selected one of the plurality of functionally-equivalent logic circuits is used to process a portion of the input data set at the superclocked clock frequency.

Abstract: Disclosed are method and apparatus of generating noise that effectively performs performance evaluation of electronic equipment in a real environment by generating the noise having a statistic characteristic of real noise in a laboratory environment, by estimating a noise parameter set by measuring the noise and generating random noise data using a random noise data generation function having a statistic characteristic corresponding to the noise parameter set to generate radio noise.

Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

Abstract: As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system.

Abstract: In one embodiment, cycle-accurate information may be collected by stopping an input clock associated with a functional block of a SoC using a programmable trigger signal. The programmable trigger signal may also stops a root clock of the SoC. Cycle-accurate information may be collected regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal. The collected information may be outputted and used to debug the SoC in a time-efficient manner.

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph specification often is at least partially defined by an interactive visual programming section that allows the user to construct a graphic specification of the target netlist. The method first searches the netlist for target subgraphs that match the target subgraph specification, and the user can verify proper target selection. The method then performs rule checks on these search targets, and non compliant subnets identified. Flexibility is enhanced by use of search wildcards, attribute ranges, and various short user scripts which may contain various Boolean logical operations.

Abstract: Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

Abstract: A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.

Abstract: A method for deriving an equivalent circuit model of a capacitor which makes it possible to derive, with high accuracy and with ease, an equivalent circuit model having characteristics in accordance with a direct current voltage applied to a capacitor. Characteristic values of predetermined resistive elements and capacitive elements forming an equivalent circuit model of a capacitor change in response to a DC bias voltage being applied to the capacitor, and the change is attributable to the material of a dielectric forming the capacitor. However, by multiplying the characteristic values of the resistive elements and the capacitive elements held while the DC bias voltage is not applied by a dimensionless coefficient in accordance with an application rule, the characteristic values of the resistive elements and the capacitive elements are corrected to values in accordance with the voltage of the DC bias voltage applied to the capacitor.

Abstract: Disclosed is a computer system for system integration, wherein chip selection for a specific system is performance and reliability optimized and, thereby cost optimized. In the system, a memory stores a chip-level performance specification and a chip-level reliability specifications, each defined for a specific integrated circuit chip that is to be incorporated into a specific system. The memory also stores an inventory that references manufactured instances of the specific integrated circuit chip sorted into bins, which are associated with different performance process windows and which are assigned different reliability levels. A processor uses the inventory to select an instance of the specific integrated circuit chip from one of the bins for actual incorporation into the specific system and does so such that the chip-level performance specification and the chip-level reliability specification are met. Also disclosed are a method and a computer program product that can similarly perform system integration.

Abstract: A vehicle may include at least one operative sub-system that includes at least one sensor configured to output one or more sensor signals related to the at least one operative sub-system. A fault detection system may be in communication with the operative sub-system(s). The fault detection system is configured to generate at least one early warning signal based on the one more sensor signals, and determine at least one derivative of the early warning signal(s).

Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.

Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow. A user interface is provided for interfacing with a user by displaying a list of debuggable parameters, accepting a selection thereof from a user, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user interface will be generated and provided to the user with a display of the relevant source code, callback function, parameter names and values, system state, and the like.

Abstract: Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary.

Abstract: Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary.

Abstract: A simulation method for simulating a three-dimensional structure, comprises the steps of: discretizing the three-dimensional structure into two-dimensional (“2-D”) layers; constructing a two-dimensional basis for each of the 2-D layers; and constructing a one-dimensional finite difference basis between the 2-D layers.

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

Abstract: In one embodiment, an integrated circuit has a conductive layer, where the conductive layer has a first set of regions and a second set of fill material regions, and the second set of fill material regions has a line of symmetry. Other embodiments are described and claimed.

Abstract: Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units. The integrated circuit layout is incorporated in a device under test.

Abstract: The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles.

Abstract: Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes an integrated circuit development system for implementing design-based weighting for LBIST. The system includes a memory system to create an integrated circuit layout. A processing circuit is coupled to the memory system. The processing circuit is configured to execute integrated circuit development tools to perform a method. The method includes analyzing, by the processing circuit, a plurality of integrated circuit design organizational units to determine preferred weightings of the integrated circuit design organizational units that provide a highest level of failure coverage when applied to a random pattern generator. Based on determining the preferred weightings, the processing circuit creates an integrated circuit layout that includes a plurality of weighted test paths to respectively apply the preferred weightings to the integrated circuit design organizational units.

Abstract: Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values.

Abstract: In one general aspect, a non-transitory computer-readable storage medium can be configured to store instructions that when executed cause a processor to perform a process. The process can include defining a plurality of subsets from a representation of a circuit, and rank-ordering each subset from the plurality of subsets. The process can also include selecting at least one of the subsets for triplication based on the rank-ordering and a triplication condition.

Abstract: In one embodiment, a method includes receiving an identity of a metric of interest and a future time point. The method further includes retrieving a prediction configuration previously associated with the metric of interest. The prediction configuration comprising a period combination. The period combination comprises a plurality of time periods, each time period comprises one or more segments, and each segment of the one or more segments comprises adapted historical values of the metric of interest incrementally inserted therein. The method also includes, for each time period of the plurality of time periods, identifying, for the future time point, a corresponding segment of the one or more segments, accessing a set of adapted historical values from the corresponding segment, and computing an intermediate predicted value from the set of adapted historical values. Moreover, the method includes calculating a predicted value for the metric of interest based on the computing.

Abstract: A debugger graphical user interface (GUI) system, method, and computer program product are provided. In use, a list of constructs is displayed a first portion of the GUI of the debugger. Further, waveforms corresponding to the constructs or source code corresponding to the constructs is displayed in a second portion of the GUI of the debugger.

Abstract: The present invention is to enable a user to input authentication information without burden, such that the user only has to memorize part of the authentication information even when inputting lengthy authentication information in order to ensure high-level security. When an operation of inputting and arranging authentication information in an information arrangement region is performed in a state where an arrangement status of a specified portion in the information arrangement region is set in advance as partial-authentication reference information in a reference authentication information memory, a CPU detects an arrangement status of the specified portion from an overall arrangement status in the information arrangement region, and performs, as partial authentication, processing of matching the detected arrangement status of the specified portion and the arrangement status of the specified portion set as the partial-authentication reference information.

Abstract: Systems, computer-readable storage media, and methods of providing RLCK parasitic extraction for electronic design of integrated circuits are presented herein. For one implementation, the method includes: importing a simulator netlist extracted from the schematic file that simulates the IC, the simulator netlist providing nets and devices in the schematic; importing the layout file which represents the physical layout of the IC; generating from the layout file a connectivity list with connectivity points in the IC for connecting generated RLCK parasitics; extracting from the layout file an RLCK netlist for the connectivity points; generating from the layout data file and the connectivity list a cross-reference between the connectivity points and the nets and devices in the simulator netlist; from the cross-reference, simulator netlist, and RLCK netlists, update the simulator netlist to includes RLCK parasitics for the connectivity points in the IC; and output an indication of the updated simulator netlist.

Abstract: The various aspects provide for an IC design and methods for utilizing the IC design to emulate corner case ICs during power/thermal testing of a test system by installing a specially chosen IC on the test system. The chosen IC may be a fully functioning IC that also includes a leakage-add controller and a current leak circuit. The current leak circuit may simulate additional current leakage on the IC and may be driven by the leakage-add controller. The chosen IC may also include a programmable voltage table for adjusting the chosen IC's operational voltage. The chosen IC may emulate the thermal characteristics of various corner-case ICs while performing normal IC activities on the test system during power/thermal testing, thereby eliminating current limitations in thermal/power testing of test systems due to the difficulty of providing corner-case ICs and testing those corner-case ICs on various test systems.