Abstract: When an electric current flowing through an electronic appliance is simulated by solving simultaneous linear equations defined depending on an analytic frequency, the simultaneous linear equations are solved in the direct method using a frequency other than the frequencies on both ends of an analytic frequency area as an analysis target, and the simultaneous linear equations are solved in the iterative method while transforming the simultaneous linear equations using the coefficient matrix analyzed in the direct method on the frequencies other than the above described frequency defined as the analysis target.

Abstract: A method and system are disclosed for generating descriptions of circuits representative of the behavior of dynamic systems. A state space model representing a dynamic system may be used to generate an electronic circuit equivalent having operating characteristics equivalent to the operating characteristics of the dynamic system. The electronic circuit equivalent may be then described as a SPICE circuit description which is simulated to determine the time and frequency domain characteristics of the dynamic system.

Abstract: For modeling a first device, a measured electrical behavior in at least one of time and frequency domain is received, wherein the measured electrical behavior at least substantially represents at least a portion of the electrical behavior of the first device. The first device is modeled by using a circuit with one or more circuit device, wherein each circuit device has a known model for its electrical behavior, and the circuit substantially represents the measured electrical behavior of the first device. The modeling comprises a step of approximating the measured signal response by sections of a curve.

Abstract: Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for geometric considerations of the semiconductor devices thereby allowing for a more flexible model and simulation by providing for geometric scaling capabilities.

Abstract: A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the states, and the test element is applied to a design-under-test. At least one result is determined based on the application of the test element to the design-under-test.

Abstract: A machine for determining field-dependent physical characteristics contains tables of precomputed quadratures and employs them to integrate numerically over a problem boundary. The quadratures are based on products of a kernel function and a basis that spans a wide range of density functions. The kernel function is dependent on a target node's position, and different quadratures are precomputed for different target-node positions or ranges thereof. In the case of at least some of the quadratures, some the basis functions include integrable singularities. The solver divides the problem boundary into a plurality of problem intervals, to which it maps the canonical interval. To integrate a problem interval for a target point, the solver employs a precomputed quadrature that is associated with the target point's relative position and that was generated by using a basis in which a singularity occurs at each canonical-interval location that was mapped to a geometrical singularity on the problem interval.

Abstract: A method for predicting stability of a closed loop apparatus is disclosed. The closed loop apparatus has an open loop impedance and at least one inherent internal gain. The method comprises the steps of: (a) identifying an impedance scaling factor associated with the closed loop apparatus that may be expressed in terms including the open loop impedance, the at least one inherent internal gain, a gain variable and a phase variable; (b) vectorally establishing a first scaling value for the impedance scaling factor as a function of frequency while maintaining a first variable of the gain variable and the phase variable at a first working value to record the first scaling value for a plurality of frequencies.

Abstract: A method for modeling digital signal processors (DSP) in a C++ environment is disclosed. In particular, the method models and converts an operation (or function) from a floating-point model to a given DSP fixed-point processor model. The invention defines a vector space for each DSP fixed-point processor, as a direct sum of each distinct fixed bit length data representation sub-space. The direct sum of all DSP fixed-point processor vector sub-spaces forms a working vector space. Furthermore, the invention defines an operator projection to be performed on the working vector space such that redundancy in the operational behavior of the DSP's to be modeled may be exploited. In the preferred embodiment, the working vector space is in a C++ environment. A C++ class is defined for each distinct fixed bit length data representation of a given DSP fixed-point processor.

Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

Abstract: A method to simulate an electronic circuit includes determining process parameters and a process variation for each process parameter, and determining a value for each of a plurality of components of the circuit as a function of the process variations.

Abstract: An apparatus is provided for simulating switched-capacitor circuits. The apparatus includes a programmable computing device, a design tool, and a behavioral simulator. The design tool is associated with the programmable computing device and is configured for interaction with a user. The design tool includes a sub-circuit definition for defining a sub-circuit of a programmable circuit device. The behavioral simulator is associated with the design tool. The behavioral simulator is configured to represent each sub-circuit via a set of discrete time-domain equations giving output of the sub-circuit as a function of input to the sub-circuit. A method is also provided.

Abstract: Method and apparatus for recognizing data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.

Abstract: A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.

Abstract: System and methods for analyzing the design of the hardware device as a whole, rather than in fragments. This provides a basis for a high-performance simulation of the hardware device from a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: System and methods for simulating a software object generated from a hardware description of an electronic device. The hardware description is a register transfer level description of the device written in a hardware description language, such as Verilog. The invention uses global analysis techniques (i.e., analysis of the design of the hardware device as a whole) to produce cycle accurate simulations of hardware devices. These global analysis techniques include generation of a static schedule for the simulation, based on clock edges and other selected signals present in the design. In some embodiments, reusing results from a previous simulation optimizes the simulation. In some embodiments, the software object that is generated may be linked with software that is being developed or tested for use with the hardware that is simulated by the software object. The software that is being developed or tested may interact with the simulation using a high-throughput application program interface (API).

Abstract: A formal verification method and apparatus allowing a user, via a waveform-based graphical user interface, to modify the waveform displayed by a verification algorithm by highlighting specific values at specific cycles. The user may begin either from scratch or from an existing trace produced by the tool. After running the tool, the resultant waveform represents a trace that the user wishes to extract from the model using the verification tool. The annotations input by the user are translated to “cycle-specific invariants” to force the tool to produce a trace that satisfies the desired annotated waveform and to insure a much faster and more efficient query. The invariants are then passed to a verification algorithm, which outputs a trace satisfying these invariants. The user determines whether the trace is satisfactory and may add additional constraints to the waveform to derive a subsequent trace until the user is satisfied.

Abstract: A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.

Abstract: A system and method for detecting accesses to non-existing hardware entities using a simulator environment. When an application running on a simulated target platform issues a transaction that involves accessing a hardware address, wherein the address is within a range of addresses allocated to a simulated hardware block, a set of instructions provided with the simulator are operable to determine if there exists a backing that corresponds to the transaction's address. If there is no backing (i.e., a control status register) associated with the address, an appropriate notification or warning is provided as a response.

Abstract: A method and apparatus (500) for simulating a magnetoresistive random access memory (MRAM) (102) uses non-linear functions to model both non-linear magnetic tunnel junction (MTJ) effects and non-linear state switching effects. The method includes calculating a high threshold (THI) and a low threshold (TLO) based on a function of the hard axis current (IH). The easy axis current (IE) is compared to the high threshold (THI). If the easy axis current is greater than the high threshold, the MTJ resistance (RHI) is set to represent a stored high value. The easy axis current is compared to the low threshold. If the easy axis current is less than the low threshold, the MTJ resistance (RLO) is set to represent a stored low value. By using non-linear functions to model the MTJ effects and switching effects, the behavior of an MRAM (102) can be more accurately simulated.

Abstract: One embodiment of the invention provides a system that uses simulation results to select evaluation points for a model-based optical proximity correction (OPC) operation. Upon receiving a layout, the system first selects critical segments in the layout, and then performs a dense simulation on the critical segments. This dense simulation identifies deviations (or low contrast) between a desired layout and a simulated layout at multiple evaluation points on each of the critical segments. Next, for each critical segment, the system selects an evaluation point from the multiple evaluation points on the critical segment based on results of the dense simulation. The system then performs a model-based OPC operation using the selected evaluation point for each critical segment.

Abstract: A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.

Abstract: Access is restricted to software objects that simulate the operation of electronic devices from register transfer level descriptions thereof. Objects are initially provided in an inaccessible state, typically as object code. A “player” module mediates user access to the simulation object, allowing the user to link to it and otherwise perform the simulation it encodes, but only in response to satisfaction of one or more authorization criteria. The nature of these criteria depend on the reason for the restriction and the party benefited.

Abstract: As to at least two transistors different only in channel lengths from each other, Ids−Vgs characteristics in a linear region are measured under two drain-to-source voltages Vds. Consequently, a graph of Rtot=Vds/Ids vs. channel lengths is obtained for two Vds, whereby an effective channel length Leff for each Vds is extracted. A velocity saturation coefficient U1 is obtained by expressing the relation between two effective channel lengths Le1 and Le2 corresponding to the two Vds on the graph and dividing the value of Le2 at Le1=0 by the difference &Dgr;Vds between the two Vds. Thus, parameters related to mobility and a velocity saturation effect are extracted with consistency in a form matching with remaining E-T data.

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Abstract: The present invention provides a hardware software co-verification tool for use by software and hardware designers of a computing system that uses an operating system having a strongly specified hardware interface specification. The present invention receives and tests the functionality of the software code intended for interaction with a hardware component within the computer system. An actual physical implementation of the hardware component is not used but is substituted with a hardware model running under simulation to provide the expected functional and behavioral patterns of the hardware component in response to the execution of the software code. An interface model is used to integrate the hardware model and software code, enabling the hardware operations called for by the software code to be processed through simulation of the hardware model.

Abstract: A method and apparatus for converting a testcase written for a first member of a processor family to run on a second member of a processor family. The first and second members of the processor family have cache memory used by the testcase. The method includes steps of reading the testcase into a digital computer and searching for, and tabulating, cache initialization commands of the testcase. Tabulated cache initializations are then sorted by cache line address and way number and displayed. This information is used to determine whether the testcase will fit on the second member without modification, and to assist in making modifications to the testcase.

Abstract: Noise estimation for coupled interconnects in deep submicron integrated circuits. One aspect of the invention is a method for interconnect coupling noise estimation. Another aspect of the invention is a computer readable medium embodying computer program code. The computer program code is configured to cause a computer to perform steps for estimating the interconnect coupling noise. The interconnect coupling noise estimation (hereafter noise estimation) includes modeling a circuit. The circuit includes a pair of interconnects, each interconnect connecting a driver gate to a load gate, where signal activity at a first interconnect of the pair of interconnects is having an impact on a second interconnect of the pair of interconnects. The circuit modeling includes modeling the first and second interconnects, driver gates, and load gates. Driver gates are modeled using a voltage source driving a resistance. Load gates are modeled using a capacitance.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: This invention features a method of simultaneously conducting simulation testing of a plurality of simulated device designs using cycle-based software which is capable of simultaneously executing a number of simulation tests along separate test pathways for each simulated device. The method is appropriate for situations in which the simulated device designs each comprise essentially identical sequences of boolean instructions. The method contemplates designating a single bit location of a multiple-word memory device for each test of each simulated device. As the test progress, the results of each test are stored in the appropriate designated bit location for such test. This allows a total number of simultaneous tests equal to the number of bits available in the words making up the memory of the memory device.

Abstract: An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:

Abstract: A bridge fault modeling and simulation apparatus including a neural network simulates the effects of bridge defects in complementary metal oxide semiconductor integrated circuits. The apparatus includes a multilayer feedforward neural network (MLFN), implemented within the framework of a very high speed integrated circuit hardware description language (VHDL) saboteur. The saboteur is placed between logic cells in the IC simulation. The apparatus computes exact bridged node voltages and propagation delay times with due attention to surrounding circuit elements. It results in faster simulation and achieves excellent accuracy.

Abstract: A test circuit for measuring the delay of a signal through a manufactured integrated circuit in order to find discrepancies between simulation models corresponding to the used manufacturing process and the process itself, comprises a delay circuit (DLY). The simulation models of the delay circuit (DLY) are used to predetermine maximum and minimum allowable delays of a pulse edge supplied to the input terminal of the delay circuit. A first verifying circuit (4, 5, 6) connected to the output terminal of the delay circuit (DLY) verifies whether or not the delay of the pulse edge is above this predetermined minimum value. A second verifying circuit (7, 8, 9, DLYC, DLYS) connected to the output terminal of the delay circuit (DLY) verifies whether or not the delay of the pulse edge is below this predetermined maximum value.

Abstract: A semiconductor test program debugging apparatus is disclosed to which data concerning a packet input to and output from the packet transfer memory device is supplied, and which extracts a part corresponding to the packet from data input to and output from the memory device with response to a test signal generated by a tester simulator and displays the details of the part.

Abstract: The present invention provides Performance groups based Simulated Annealing (PGSA) for VLSI circuit placement. This method reduces the computation time required for VLSI circuit placement using Simulated Annealing by reducing the size of the placement problem by forming Performance groups while maintaining a high quality of the final placement solution. Performance groups are formed by picking circuits connected by a net and counting their local-net-count. These circuits are then grouped based on certain pre-determined conditions and placed suitably using simulated annealing based placement approach.

Abstract: Methods and apparatus for modeling noise present in an integrated circuit substrate are disclosed. A position on a surface of the integrated circuit substrate is obtained. A combination of layers associated with the position and defining a vertical column beneath the position is ascertained. A doping profile associated with the combination of layers is obtained. The doping profile includes a plurality of portions, each of which is associated with a different range of substrate depth. Noise in the integrated circuit substrate is then modeled using the obtained doping profile.

Abstract: The present invention includes a method for generating typical and corner device models to account for statistical variations in a semiconductor device fabrication process. The typical and corner models can be generated before the semiconductor device fabrication process is fully developed based on a process specification associated with the semiconductor device fabrication process. The typical and corner models can also be generated with better accuracy after the semiconductor device fabrication process is developed and measured data are available for model generation.

Abstract: A method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of a circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible when providing a first representation of the circuit design and effectively invisible when providing a second representation of the circuit design.

Abstract: A method and system for simulating a circuit design that includes analog and/or digital circuitry uses a hybrid system of static analysis and dynamic simulation. Once the user's circuit is read in and partitioned into stages, the input vectors are applied. A hybrid vector is used to represent a number of possible signal states, for example, a logic 0 or logic 1, as well as a number of possible signal transitions, for example, a rising signal or a falling signal. The possible combinations of states are enumerated and the network in the stage is solved for all possible combinations. The results from the network solutions for the different combinations are recomposed into the hybrid notation, which is then applied to the next stage.

Abstract: A method and apparatus for mesh-free engineering analysis of geometric models is described. The method and apparatus, which are preferably software-based and implemented on personal computers or other programmable processing devices, represent geometric models by implicit mathematical functions. The implicit functions allow interpolation of all desired boundary conditions over the geometry without meshing, and the boundary conditions may then may be combined with a piecewise continuous model of the solution structure (i.e., the analysis problem). By solving for elements of the solution structure (its basis or coordinate functions) which satisfy the given boundary conditions either exactly or approximately, the solution structure will define the behavior and boundary conditions (exactly or approximately) throughout the geometric model.

Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.

Abstract: A device and automated method of calculating bulk states information and interface states information of a thin film transistor from a current-voltage measurement and a capacitance-voltage measurement comprising the steps of: calculating the flat band voltage from the input capacitance-voltage measurement; applying a general expression of Gauss's Law and the calculated flat band voltage to a capacitance voltage relationship which define capacitance so as to calculate a relationship between gate surface potential and gate/source voltage; applying Gauss's Law to the calculated relationship between gate surface potential and gate/source voltage to thereby calculate and ouput the interface states; calculating conductance/gate voltage data from the current-voltage measurement using the calculated flat band voltage; conducting an initialisation process using the calculated conductance/gate voltage data and the calculated relationship between gate surface potential and gate/source voltage, said initialisat

Abstract: An electrical circuit can be described by a layout and by a network list. A network list has one or more cells each having one or more cell entities. From an existing layout, intrinsic capacitance values and coupling capacitance values of the networks are determined for all of the cell entities. Using these capacitance values, the cell entities are classified into variants. These variants are used in the simulation of the behavior of the electrical circuit.

Abstract: A method and system for providing a realizable reduced-order model for a circuit. The method includes calculating a value for each component of said realizable reduced-order model. The calculating is based upon properties of a signal provided to the circuit and a voltage range associated with the circuit. If at least one of the values is not positive, the voltage range is modified and the calculating step is repeated until each of the values is positive.

Abstract: From the data of diffusion-length-dependent parameters extracted from the parameters of the transistor model of MOS transistors and from the parameters of transistors having various diffusion lengths, a diffusion-length-dependent parameter correcting unit creates approximate expressions of the diffusion length dependence of these parameters, and calculates parameter correction values to be used instead of original parameter values by using the created approximate expressions. Hence, the correction values can be used easily instead of the original parameter values, whereby a transistor model of MOS transistors having a different diffusion length DL can be created easily. Circuit simulation in consideration of the diffusion length dependence of the drain currents of MOS transistors can thus be carried out, whereby highly accurate simulation can be attained.

Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).

Abstract: An on-board self test system for an electrical power monitoring device includes a test signal circuit in an electronic circuit of the monitoring device, and responsive to a programmable test input signal for producing an analog signal simulating an electrical power waveform, and a programmable memory in an electronic circuit of the monitoring device and operatively coupled with the test signal circuit for storing and reproducing upon command, one or more of the programmable test input signals.

Abstract: A microprocessor core 4 is modeled using an obscured model 22 of the core functionality and a non-obscured model 24 of the scan chains that in that particular instance are associated with the microprocessor core 4. Validation of the design of a scan chain controller 12 can be achieved using the non-obscured scan chain model 24. Different scan chain models 24 can be relatively easily provided to model different scan chain physical configurations whilst leaving the more difficult to produce obscured core model 22 unaltered.