Abstract: Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then realized to form various realized logic portions. A first realized logic portion can then be wrapped and formally verified against it's respective model. The wrapper can then be verified by first applying the wrapper to a second logic model portion and a second realized logic portion, then formally verifying them against each other. The resulting output can then be prove wrapper correctness.

Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.

Abstract: Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.

Abstract: An apparatus and method for determining certain correction factors in analyzing the vibration frequency characteristics of an electroded crystal plate. The developed correction factors are introduced to correct the inaccuracies of third-order thickness-shear cut-off frequencies. The analysis is preferably carried out during the design of a piezoelectric device incorporating the electroded crystal plate before production of the device.

Abstract: The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIMPD model. The method comprises obtaining terminal current data corresponding to various bias conditions in a set of test devices and extracting a portion of a plurality of DC model parameters for the device model from the terminal current data. The terminal current are then modified based on the extracted portion of the DC model parameters before extracting additional DC model parameters. The present invention also includes novel methods for extracting some of the DC model parameters.

Abstract: A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error.

Abstract: What is described is a method to reduce variations in signal delays along paths in a design of an integrated circuit by balancing wire widths. The method operates by performing a circuit simulation to determine simulated signal delays along the circuit paths based on first wire widths for a given circuit, then running a delay model analysis to calculate predicted signal delays along the circuit paths based on first wire widths for the given circuit. The method then calculates a correction difference between the predicted signal delays and the simulated signal delays, and derives delay targets from the correction difference. Finally, the method calculates second wire widths using the delay model analysis to meet the delay targets. Preferably, the signal delays are clock signal delays, the circuit simulation is a SPICE circuit simulation, and the delay model is an Elmore delay model. Also described is a system which includes a CPU and certain memory components for accomplishing the method.

Abstract: A method and apparatus for characterizing a device under test (“DUT”) calibrates a multiport test set and measures S-parameters [S] of the DUT. The method and apparatus further involves determining elements of a scalar orthogonal matrix [M] corresponding to terminals of the DUT and DUT modes of operation. The scalar orthogonal matrix [M] comprises a row of elements representing a single-ended terminal of the DUT, and four rows of elements representing a balanced terminal of the DUT. The S-parameters of the DUT are then transformed into mixed-mode S-parameters [Smm] according to Smm=MSM−1. A method of and apparatus for characterizing a DUT involves calibrating a multiport test set, coupling the DUT to the multiport test set, and measuring S-parameters of the DUT. The S-parameters are converted to a time domain representation and at least one of the S-parameters is convolved with a simulated input signal to generate an output response.

Abstract: First, a graph of a set of transition sequences representing the property to be satisfied by a finite state machine which is a model of a logical device. Then, a node to be processed is selected from the graph, and one of the branches connected to the node is selected. A mapping operation is performed on a set of states of the node on the starting side of the selected branch, and the result is added to the set of states of the node on the ending side. As a result of the mapping operation, it is determined whether or not the set of states which satisfies the target property has been obtained, that is, whether or not an example of a transition sequence has been successfully detected. If it has been successfully detected, then it is assumed that there is a transition sequence, the process terminates. If it has not been successfully detected, then it is determined whether or not there is an unprocessed branch connected to the node. If yes, the above described process is repeated.

Abstract: Techniques are provided for determining certain correction factors and using these correction factors in analyzing the vibration frequency characteristics of a piezoelectric material. The correction factors are developed based on the Mindlin plate theory and are introduced to correct the inaccuracies of higher-order thickness-shear cut-off frequencies. The analysis is preferably carried out during the design of a piezoelectric device incorporating the piezoelectric material and before production of the piezoelectric device. The design state may also include determining whether the device and its electrodes exhibit appropriate stiffness characteristics.

Abstract: A chip development system includes debugging software for simulating chip operation. A function library is also included for processing chip functions in the form of software, the function library being driven by the debugging software.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: The present invention is directed to a simulation testbench 10 which includes a circuit under test 14 and a plurality of test models 12 designated 1 through N. The test models 12 include at least one of a driver and a monitor. The drivers selectively apply stimuli to the circuit under test 14, and the monitors observe responses to the stimuli from the circuit under test 14. A single controller 16 is provided for the plurality of test models 12. The controller 16 has an instruction source 18 including a list of commands which control the plurality of test models 12. The commands are routed from the instruction source 18 over a model control bus 24 to the plurality of test models 12.

Abstract: A design aid apparatus includes an input section, an antenna propensity determination section, an output section, and a memory storing design data for a plurality of structures comprising an electronic device to be designed. Conductivity of a structure is determined based on conductivity information of the structure read out from the memory. The antenna propensity determination section determines a contact relation, which expresses a state of electrical contact between a conductive structure having conductivity and another conductive structure, based on information relating to shapes and arrangements of structures stored in the memory. A length of a route between a reference conductive structure and the conductive structure is determined. The antenna propensity of the electronic device is evaluated based on the route length.

Abstract: A method for efficient integrated circuit (“IC”) dynamic IR-drop analysis algorithm is disclosed. In one aspect, this method eliminates the need for peak-power input stimulus vectors or Verilog's value change dump (“VCD”). Rather than performing transient simulation over a long set of input vectors to determine the worst dynamic IR-drop, the disclosed method statistically determines the switching direction and the timing for each instance based on its block or module switching scenario. Full-chip transient simulation, including the RLC extracted from the power-ground network, is then performed accordingly over a few clock cycles. This approach makes feasible full-chip dynamic IR verification with the consideration of power-ground inductance and capacitance.

Abstract: A method for modeling junction capacitance of the MOSFET transistor is proposed and implemented for high-speed circuit simulator. A region-based value of the capacitance of MOSFET is proposed, and its regional capacitance value model is more accurate and takes less computation time than the conventional bias independent average capacitance model.

Abstract: The present invention provides a method and system for simulating the effect on the frequency response of a transmission line due to the coupling of a second electrical network to the transmission line. It is observed that signals propagating through the second electrical network are reflected at the end of the second electrical network, thereby propagating back to the point of coupling with the transmission line causing partial cancellations of signals present. Thus, the second network effectively operates as a delay line, with an overall effect of creating nulls of various widths and depths in the frequency response of the transmission line. This second delay-line like network is replaced with a significantly simpler configuration.

Abstract: Technique to improve circuit level simulation speed through the block characterization of the RC network based on the AWE (Asymptotic Waveform Evaluation) is proposed. Since the numbers of RC network of the recent VLSI circuit becomes huge, the complexities of them are the most difficult and time-consuming task in the circuit verification. In addition to the increasing size of the RC networks, the accuracy is another big concern in the circuit simulation and verification. To have the speed while maintaining the accuracy in the circuit simulation, abstraction by block characterization is devised, implemented, and benchmarked. It first extracts transfer equation from the complex RC networks by applying AWE, modeled them as simple &pgr;-model, then find effective capacitance. The effective capacitance is modeled as pin capacitance of the input of the block, the transfer equation is modeled as a function of the between pins in the block.

Abstract: An apparatus and method of generating an application for a control system. A control process is defined by a physical model and a topological model. An application generator utilizes the physical and topological models to generate an application for the control system.

Abstract: A method of generating transistor scattering parameters employs a single circuit simulation with a self-correction scheme for the artificial DC voltage dropped across the 50-Ohm resistor representing transmission line impedance. A sub-circuit without 50-Ohm transmission line resistance is used to compute transistor bias current via a current-controlled voltage source to compensate for the DC voltage dropped across a 50-Ohm resistor contained in the network.

Abstract: An apparatus comprising a system configuration generator, a system builder and a simulation verification environment. The system configuration generator may be configured to generate a random system configuration file of a structurally variable and complex system. The system builder may be configured to build a system level netlist in response to the random system configuration file. The simulation verification environment may be configured to verify the structurally variable and complex system in response to the system level netlist. The simulation verification environment may be configured to provide automatic random verification of the system in response to the random system configuration file.

Abstract: A system is disclosed in which a single tool-independent model of a circuit design is used to generate a plurality of tool-specific circuit models suitable for use with a plurality of target tools, such as Automatic Test Pattern Generation (ATPG) tools and/or equivalence tools. A plurality of circuit block class definitions provide abstract interfaces to a plurality of circuit block classes. Each circuit block class definition includes a plurality of tool-specific models of the corresponding circuit block class. The tool-independent circuit model models at least some of the blocks in the circuit design by reference to the circuit block class definitions. A circuit model processor generates a tool-specific circuit model by replacing tool-independent block models in the tool-independent circuit model with corresponding tool-specific block models suitable for use with a particular one of the target tools.

Abstract: A system and method is described for the simulation of the transfer function of very large RC networks of IC chips, such as VLSI. Both the real and imaginary components of the transfer function of RC networks have a property of changing more rapidly at lower frequencies but changing less rapidly at higher frequencies. Methods are employed which interpolate between transfer functions of the RC network for specific frequencies in order to derive an interpolated transfer function of the RC network.

Abstract: The invention relates to simulating an electronic circuit with an uncharacterized hardware circuit. In one embodiment, a method for modeling a circuit that comprises uncharacterized hardware and a simulation system is disclosed. Uncharacterized hardware is coupled to the simulation system. The simulation system comprises at least one simulation model written with a hardware description language (HDL). An interface module integrates a computer port of the simulation system with HDL-based simulation software. The interface module is coded in a language different from the simulation model.

Abstract: Data clusters are added between functional blocks in a higher-level hierarchical circuit model. The data clusters account for inter-level parasitic values without flattening the circuit model to a lower hierarchical level and operate as an information graph or network between nodes, which can be used with the standard, or default, information graph between nodes. The data clusters also allow the use of standard functional blocks without introducing artificial nodes into the circuit at a lower level that could create a coupling point at a higher level. The use of data clusters allows rapid and accurate modeling of the circuit without flattening the circuit to the lowest level.

Abstract: An improved ASIC design support system is described. In accordance with the ASIC design support system, it is possible to easily download the latest versions of a necessary library (or libraries) and a necessary simulator. The ASIC design support system includes a web server which receives a request of the customer including the specification of the ASIC he wants to design. The web server serves to generate and transfer to the customer a library (or libraries) or a simulator required for designing said ASIC and performing simulation thereof.

Abstract: A method and apparatus are provided for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits. A method of logical effort is applied to the CMOS logic circuits. Selected circuits within the CMOS logic circuits are checked for noise immunity utilizing a noise test simulation to identify each selected circuit failing the noise test simulation. An electrical effort is fixed to a value for providing noise immunity for each identified selected circuit failing the noise test simulation. The method of logical effort is applied to each remaining selected circuit not failing the noise test simulation. The sequential steps are repeated for each remaining selected circuit not failing the noise test simulation until no selected circuit failing the noise test simulation is identified. The selected circuits that are checked for noise immunity include, for example, dynamic circuits and passgate circuits.

Abstract: An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.

Abstract: A method, system, and computer program product for emulating a sequence of events resulting from user interaction with an applet in which the storing and retrieval of queued event objects is facilitated through the use of an index to a component vector. When an applet event recorder is invoked and the applet selected, an automator initializes the applet and generates a component vector that includes a reference to each component of the applet. Events are then detected by the applet event recorder via automator listeners. The automator then generates queued event objects and stores the queued event objects in an automator queue. The generation of queued event objects in one embodiment includes the generation of a component index value that points to the component of component vector that references the applet component that was responsible for generating the corresponding user interaction event.

Abstract: In a mutual immittance calculation apparatus, an input section inputs data of a model of an electric circuit apparatus, being a target for analysis of the electromagnetic-field strength and being divided into a plurality of patches. A mutual immittance calculation section calculates respective mutual immittance for combinations of patches corresponding to the main portion and to the additional portion. The mutual immittance calculation section uses a stored calculation result corresponding to the main portion when the model in which only the additional portion has been changed is calculated for a second time onward, and recalculates the mutual immittance corresponding to the changed additional portion.

Abstract: A system and method for automatically calculating an optimum layout of a wireless cell station in an environment using a wireless communication system, thereby achieving a timesaving and resources-saving cell design procedure. The system calculates an optimum layout of the wireless cell station based on information of terminal locations.

Abstract: A circuit includes both an analog-digital converter cell and a digital cell. The circuit has six digital input terminals and one analog input terminal. Similarly, the analog-digital converter cell has six digital input terminals, six digital output terminals, and one analog input terminal. The digital input terminals of the circuit are connected to the digital input terminals of the analog-digital converter cell and in turn to the digital output terminals of the analog-digital converter cell. The signals output from the analog-digital converter cell are input to the digital cell. Test patterns are input to the digital input terminals of the circuit. The circuit has four output terminals. Whether the wiring connection between the analog-digital converter cell and the digital cell is correct is determined based on signals output from the circuit.

Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.

Abstract: The methods and apparatus of the present invention are directed to optimizing configurable processors to assist a designer in efficiently matching a design of an application and a design of a processor. In one aspect, methods and apparatus according to the present invention optimize a hardware architecture having one or more application specific processors. The methods and apparatus include modeling one or more of the application specific processors to generate a simulated hardware architecture and analyzing a compiled program for the simulated hardware architecture to determine one or more resource parameters for one or more program sections of the compiled program. The methods and apparatus provide one or more suggestions for modifying one or more of the application specific processors and the program sections in response to the resource parameter to optimize one or both of the compiled program and the hardware architecture.

Abstract: A method of transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects includes designing a functional block based on a set of design considerations; generating a parallel functional pattern for testing the functional block; and translating the parallel functional pattern into a serial pattern. An apparatus for transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects, comprising a functional block designed based on a set of design considerations and comprising a scan boundary, the scan boundary comprising a scan in chain and a scan out chain, a parallel functional pattern for testing the functional block; and software for translating the parallel functional pattern into a serial pattern that is fed into the scan in chain, evaluated, and fed out of the scan out chain.

Abstract: A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: A method and system and computer program product for automatically creating computer simulations or analyses of signal transfers of a circuit or system design are disclosed. A description of a physical design of a circuit or system is provided. The physical design has physical components and at least one of the physical components may transfer a signal to at least one other physical component. The physical design description includes an identification of the physical components and information descriptive of physical inter-connectivity among the physical components. A signal transfer description is provided for at least one signal transfer. The signal transfer description includes a set of source nodes and a set of receiver nodes. The set of source nodes provide the signal to be transferred and the receiver nodes receive the signal transferred from the corresponding set of source nodes. Each node is described by information associated with physical components.

Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.

Abstract: A method for efficiently changing the embedded processor type in verification of system-on-chip (SOC) integrated circuit designs containing embedded processors. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. Typically, the embedded processor type changes as SOC designs change. However, changing the processor type may cause errors in verification due to the presence of processor-specific code distributed throughout the verification software. Thus, changing the processor type can entail a substantial re-write of the verification software. In the method according to the present invention, in verification software for verifying a SOC design including an embedded processor, processor-specific code is localized in a processor driver.

Abstract: In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.

Abstract: An approach for representing integrated circuit device characteristics using polynomial equations involves analyzing integrated circuit device characterization data in a lookup table form and using an order incremental scheme to determine a polynomial equation of a relatively low-order that satisfies specified accuracy criteria. In situations where a polynomial equation that has an order less than a maximum allowable order cannot be determined, the integrated circuit device characterization data is partitioned into sub-domains and polynomial equations are determined separately for each sub-domain. The separate polynomial equations are then combined to generate a piecewise polynomial equation that represents all of the integrated circuit device characterization data.

Abstract: The invention includes a method and a system for generating integrated circuit (IC) simulation information regarding the effect of design and fabrication process decisions. One embodiment includes creating and using a data store of profile-based information comprising metrology signal, structure profile data, process control parameters, and IC simulation attributes.

Abstract: A control system and control method provides improved control of various loads by selecting the switch configuration of an associated power circuit having N binary switches, based in part on a finite state machine. The control system includes an embedded simulator, a present state contemplator and a next state contemplator to predict the operation of the load based on various switch configurations of the power circuit. The various switch states of the power circuit are modeled by the finite state machine (having up to 2N switch states) such that at any time, the power circuit switches are in a Present State and there are a plurality of Next States which are one or more switch transitions away from the Present State. The embedded simulator estimates the operating conditions of the load based on measured operational characteristics and the Present State. The present state contemplator determines, based on the operating conditions, whether a switch state transition should be contemplated.

Abstract: This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and concurrently solved in a distributed computing environment. This permits the user to use, in a scalable fashion, additional computing resources to rapidly solve difficult equivalent functionality checks. The method allows difficult checks to be solved using (1) a divide-and-conquer approach, (2) by a competitive approach in which many independent attempts are made to solve the same check, or (3) by allocating more resources to solve the difficult check.

Abstract: A method and apparatus are disclosed for verifying the functional design of a system's response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays. A programmable delay.element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior.

Abstract: Start and stop signals are obtained from a user, with associated start and stop times, as well as circuit simulation results. The simulation results are utilized to determine which of the components in the circuit are active components, which are any components that have an active output signal. Active output signals obtain a state between the start and stop times in response to a state change of the start signal. The user output equipment is utilized to provide the active components and the active output signals to the user. Signal activity is presented in a graphical form that shows the active path circuit, and active value changes that cause output signals to become active. The user may select time values at which signals become active to see in a graphical manner the propagation of a start signal state change through the circuit.

Abstract: A method for optimizing decoupling capacitance in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and an amount of the decoupling capacitance is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing decoupling capacitance in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize decoupling capacitance in a delay locked loop is provided.