Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Abstract: The simulation method of the present invention for simulating a system having a plurality of circuit modules using software, comprises the steps of: using an object oriented language; preparing a plurality of circuit base classes, which describe base circuit modules as classes, as a library; describing the circuit modules, to be simulated, as classes by inheriting the circuit base classes prepared as the library; and describing the system, to be simulated, by combining the circuit modules described as the classes.

Abstract: A method for hierarchical specification and modeling of scheduling in system-level simulations. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. A scheduling policy governs how behaviors assigned to a resource, gain access and share the resource. The invention includes a general framework for modeling a scheduling policy, which includes a simple mechanism that covers many common cases. This framework is part of a Virtual Component Codesign (VCC) process, which is targeted at consumer embedded system design. Two orthogonal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol.

Abstract: A system, method, and computer program product is presented for simulating a system of hardware components. Each component is simulated in a hardware definition language such as VERILOG. Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module. The invention synchronizes the simulation modules by issuing clock credit to each simulation module. Each simulation module can only operate when clock credit is available, and can only operate for some number of clock cycles corresponding to the value of the clock credit. Operation is said to consume the clock credit. After a simulation module has consumed its clock credit, its DUT halts. Once every simulation module has consumed its clock credit and halted, another clock credit can be issued. This allows checkpointing of the operation of each DUT and simulates parallelism of the DUTs using executable images of manageable size.

Abstract: An apparatus for calculating immunity from a radiated electromagnetic field which makes possible high-speed simulation of the electric current flowing through an electronic apparatus due to a radio wave radiated from an antenna, and a method and a storage medium storing programs used for the same which divides a radio wave radiated from an antenna into a carrier wave, upper sideband wave, and lower sideband wave, and uses the moment method to simulate the effect of the radio wave on an electronic apparatus by calculating the mutual impedance for one frequency component out of the above three frequency components and using that mutual impedance to solve the simultaneous equations under the moment method so as to calculate the electric current flowing through the electronic apparatus.

Abstract: Electronic circuits and systems which include digital and analog circuit sections are simulated with a combination of analog and digital simulation. For the interface matching of the two types of simulation, there is used, between a connection of an analog-simulated circuit element and a connection of a digitally simulated circuit element, a transport element for transporting current values between the circuit elements.

Abstract: A method and apparatus are provided for assembling and operating a physical system having a plurality of structural elements and structural interconnections from a remote location. The method includes the step of creating a graphical representation of the physical system at the remote location showing the elements and connections of the system to be assembled. The method further includes the steps of converting the graphical representation into an element list delineating the elements and the interconnections, transferring the element list from the remote location to an element controller and assembling and operating the system by the element controller in accordance with the element list.

Abstract: An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.

Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Abstract: Method and apparatus for determining power dissipation for an integrated circuit using computer simulation is described. More particularly, the integrated circuit is divided into cells, and one or more nodes are identified within each of the cells. A capacitive load value is ascribed to each of the nodes, and code is generated to track charges in state of each of the nodes. A total for changes in state for each node is divided by simulation time to determine a switching frequency. Using switching frequency, capacitive load and source voltage, dynamic power dissipation for each node may be determined. By summing dynamic power dissipation for all said nodes, total dynamic power dissipation may be determined.

Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

Abstract: For use in an integral equation formulation of capacitance, a system for, and method of, generating a representation of charge distribution for a given capacitive structure (which may be an integrated circuit). In one embodiment, the system includes: (1) a charge variation function generator that creates a multidimensional charge variation function that is not directly dependent on a conductive geometry of the structure and (2) a conductive geometry generator, associated with the charge variation generator, that creates a conductive geometry that is independent of charge variation in the structure, the charge variation function and the conductive geometry employable in the integral equation formulation to reduce a complexity thereof.

Abstract: A method and apparatus for simulating a circuit is described. In one embodiment, the method comprises representing a plurality of identical components in a reduced form as a circuit having a single instance of the identical component with encoding for each input of the single instance to represent corresponding inputs to all of the plurality of identical components and decoding for each output port of the single instance to create output ports for the outputs associated with all of the plurality of identical components and symbolically simulating the reduced form of the circuit with simulation results being the same as results of symbolically simulating the plurality of identical components.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: The present invention is directed to reduce the number of measuring processes of an actual apparatus. A final model for estimating the behavior of an engine 3 is generated by the following procedure. First, a simulation model in which physical properties of the engine 3 are considered is set. Next, measurement is roughly performed by an actual apparatus. Based on the difference between the simulation data and the measurement data, a correction function is Err, 130 derived. By combining the physical model and the correction function Err, 130, a final model is obtained. By using the final model, a final adaptive value is determined.

Abstract: The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.

Abstract: A method includes sending a query from graphical user interface to a hardware configuration database. The query requests information located within a simulation model. The hardware configuration database including locations of hardware devices. The hardware devices represent functional processes. The method also includes searching the functional processes to locate the information and directly accessing the information in the simulation model from the graphical user interface without assistance from the hardware configuration database.

Abstract: A method for predicting transient response of a closed loop apparatus includes the steps of: (a) providing a first reference tool that relates load-free impedance response with a first design gain-phase variable; (b) providing a second reference tool that relates load-free impedance response with a second design gain-phase variable; (c) determining a combined impedance response as a function of frequency; (d) employing at least one of the first and second reference tool to establish a first design value for one of the phase variable and the design load impedance at a characteristic frequency that occurs at a peak value of the combined impedance response; (e) employing at least one of the first and second reference tool to establish a second design value for the other parameter of the phase variable and the design load impedance at the characteristic frequency; (f) establishing a transient multiplier as a function of frequency associated with the output voltage with the design load impedance for selected value

Abstract: A method for evaluating a power distribution network for a circuit has steps of creating a circuit model of the circuit in which all wires and transistors are represented as circuit elements, with the model comprising a plurality of nodes. A DC power analysis is performed on the circuit model to determine voltage drops at a plurality of the nodes.

Abstract: A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.

Abstract: A method that creates a string that models a trace, the string having a collection of lumped elements, where at least one of the lumped elements has a cross capacitor. The method reduces the string to a pi model where the pi model has a cross capacitor. The method simulates the application of an applied noise voltage to the cross capacitor.

Abstract: A system and method for estimating interconnect delay are disclosed that include determining inductance of an interconnect. A transfer function is determined using the inductance, and two poles of the transfer function are determined. An interconnect delay is estimated using the two poles.

Abstract: A method and apparatus that utilize time-domain measurements of a nonlinear device produce or extract a behavioral model from embeddings of these measurements. The method of producing a behavioral model comprises applying an input signal to the nonlinear device, sampling the input signal to produce input data, measuring a response of the device to produce output data, creating an embedded data set, fitting a function to the embedded data set, and verifying the fitted function. The apparatus comprises a signal generator that produces an input signal that is applied to the nonlinear device, the device producing an output signal in response. The apparatus further comprises a data acquisition system that samples and digitizes the input and output signals and a signal processing computer that produces an embedded data set from the digitized signals, fits a function to the embedded data set, and verifies the fitted function.

Abstract: A computer system (30) and method of operating the same to model worst case performances of an analog circuit is disclosed. The computer system (30) includes disk storage devices for storing a process parameter data base (32), design of the circuit (31), and program instructions for performing the modeling method (33). Under the control of the program instructions, the system computer (22) retrieves the process parameters and desired performances, and performs a designed experiment to determine a Jacobian matrix of the dependence of the performances upon the process parameters. Singular value decomposition of the Jacobian matrix provides a set of singular values and a rotation vector, from which the coefficients of a worst case vector of the process parameters for each of the circuit performances are then derived. The system computer (22) then applies the simulation to the worst case vectors, to evaluate the worst case performances of the designed circuit.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: A method is described for distinguishing between an input or output signal on a bi-directional pin of a model of a hardware circuit. The method includes the steps of for a bi-directional pin of said model applying signals to said pin at a reduced drive strength such that a driven signal on said pin will be superimposed over the applied signal, and comparing the drive strength on the bi-directional pin and responsive to said comparison determining whether the bi-directional pin is an input or output.

Abstract: A method and system are described in a logic simulator machine for efficiently creating a trace of an array which includes a plurality of storage locations. The logic simulator machine executes a test routine. Prior to executing the test routine, an initial copy of all data included within each of the storage locations of the array is stored as a first trace of the array. During execution of a first cycle the test routine, all of the write control inputs into the array are read to identify ones of the storage locations which were modified during the execution of the first cycle. A new trace of the array is generated which includes a copy of all of the data of the first trace. In addition, only those ones of the storage locations in the first trace which were modified during the first cycle are updated. A trace is thus generated by updating only those ones of the storage locations which were modified during execution of a cycle of the test routine.

Abstract: A simulation device and method to simulate the electric current flowing in electronic devices using the moment method, and to execute accurate simulation processing when the electronic device has an amplifier. An allocating device allocates defining dipoles to the input terminal and output terminal of an amplifier of an electronic device for the purpose of deriving the electric current flowing in the element. A creating device creates a simultaneous equation of the moment method having a form such that the amplifier input impedance is inserted into the input terminal dipole allocated by the allocating device, and the amplifier output impedance, or its inverse, and a dependent energy source responding to the amplification characteristics of the amplifier are inserted into the output terminal dipole allocated by the allocating device. A solving device solves the simultaneous equation of the moment method created by creating device.

Abstract: A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.

Abstract: Method and apparatus determine the performance of an integrated circuit that includes at least one of a plurality of deep-well trench dynamic random-access memory (DRAM) cells. The method includes executing a circuit simulator for designing an integrated circuit that contains at least one of a plurality of DRAM cells. Further, the method includes calculating a set of output parameters with the circuit simulator for each of the plurality of DRAM cells utilizing, for example, a deep-well trench DRAM cell model for each of the plurality of DRAM cells.

Abstract: A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.

Abstract: A method for performing input/output (I/O) floor planning on an integrated circuit design is disclosed. User design data related to I/O circuit associated with each package pin is initially collected. The collected user design data is then sorted according to operating conditions. Next, an I/O behavioral model and a package model are chosen based on the sorted data. A simulation deck is dynamically built with appropriate operating conditions. Finally, a simulation is performed through a circuit simulator using the chosen I/O behavioral model and the operating conditions.

Abstract: A new computer based method is provided for the evaluation of dielectric film properties. These properties are for a given dielectric derived from measurements of the chemical bonding of that dielectric. Previously collected reference data are maintained in a reference data base from where data are extracted and used as input to mathematical modeling software that predicts thin film properties. The output of these prediction algorithms is used, together with chemical bonding measurements of the dielectric that is being investigated, as input to a program that computers the dielectric properties of the dielectric.

Abstract: The invention provides an electronic circuit means for injecting virtual flaw signals into the signal path between a NDT test instrument and an associated probe. This enables a system that is capable of generating virtual flaw signals to present virtual flaws to an NDT inspector while enabling the test probe to present actual flaws to the NDT inspector. An eddy current test (ECT) embodiment of the invention comprises a means for deriving a reference signal from an ECT instrument excitation signal, a means for modulating the gain and phase of the reference signal by commands from a control computer, and a means for summing the modulated signal with the ECT probe output signal for transmission to the ECT instrument.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: The present invention provides a method and system for representing the simulation results in a much more compact format than the current state of the art and speeds up significantly both the storing of the results and the processing of the database, especially speeding up the comparison of two databases. This is achieved by (1) providing the database with more information which is typically available in the simulator or could easily be made available directly from the design description, and by (2) using the dependency graph of the signals in the database to implement a much faster comparison of two databases.

Abstract: A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceed a maximum acceptable length for that given driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.

Abstract: DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e.g., the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: A system for analyzing a circuit includes a computer. The computer operates on a model of the circuit. The model has an input, an output, and multiple controlled sources. The computer is configured to supply a stimulus to the input of the model of the circuit. The input stimulus has an associated value. Each of the multiple controlled sources has a current value derived from the input value. The computer is also configured to supply a stimulus to the output of the model. The output stimulus has an associated value. The computer is further configured to sweep the values for the input and output stimuli through a two sets of swept values, and to obtain an output current of the model of the circuit as a function of the swept values.

Abstract: A system and method for performing circuit simulation is described. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: A functional verification method and method that uses automatic extraction of coverage metrics to verify pipeline designs in a simulation-based validation flow. The method can target data transfer features of pipelined designs. Several of the metrics used are a one stage transfer metric (OST), a path metric, a one stage sequence (OSS) metric, a microinstruction flow (MIF) metric, and a microinstruction sequence (MIS) metric.

Abstract: Simulation of electromagnetic characteristics of an electrical circuit uses netlist data defining component instances, including layout component instances, and their topological interconnection in an electrical circuit. A circuit simulation is performed using the netlist data, involving use of a model for each said layout component instance. An attempt is made to retrieve an existing simulation model of the layout component instance from a database of such layout component simulation models. If no suitable simulation model can be found in the database, an attempt is made to interpolate a new simulation model from among existing simulation models in the database. If interpolation is determined not to be feasible, then an electromagnetic simulation of the layout component instance is performed to develop a new electromagnetic simulation model. This new model is used in the circuit simulation, and added to the database for future use.

Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.

Abstract: According to an embodiment of the invention, a system and method for performing simulations is provided. Using parallelism in systems, the method decomposes a larger problem into several smaller partitions. A series of iterations is performed until the waveforms exchanged between the partitions converge. Approximate pre-view solutions of strongly coupled partitions are introduced to reduce the number of iterations required for convergence. These approximate pre-view solutions are introduced before the simulations occur. Once the waveforms converge, the simulation has determined a solution.

Abstract: The multi-user server technology allows multiple host stations to configure, load, and execute multiple jobs in a reconfigurable hardware unit for emulation purposes, simulation acceleration purposes, and a combination of emulation and simulation in a concurrent manner. The reconfigurable hardware unit includes a plurality of hardware resources (e.g., FPGA chips on slot module boards) for modeling at least a portion of one or more user designed. The server includes a bus arbiter for deciding which one of the host stations will be coupled to the hardware resources via the bus multiplexer. The plurality of hardware resources includes slot modules, which includes one or more boards of FPGA chips. An arbitration decision is made to assign a particular slot(s) to a particular host. A host and its respective assigned slot(s) can communicate with each other while other hosts and their respective assigned slot(s) communication with each other.