Abstract: Geographically oriented units of a given first hierarchical level of a radio communication system are assigned to geographically oriented units of at least one higher second hierarchical level by: Setting up functions that specify, as a function of a number of subscribers of a radio communication system, a size of a load, that is selected from the group consisting of a radio load and a switching load, and that is caused by a geographically oriented unit of a first hierarchical level at a node of the radio communication system. Setting up a formula which, using the functions, permits a size of a processing load occurring at each node, in a case of a given assignment of geographically oriented units of the first hierarchical level to geographically oriented units of the second hierarchical level, to be calculated for a given number of the subscribers.

Abstract: The inventive lightweight occurrence model uses a folded connectivity model which includes occurrence nodes. Each occurrence node includes occurrence specific data or a pointer to such data, a pointer to a parent occurrence node, and a pointer to a folded model describer. Thus, the information that would present in a full occurrence model can be included in the inventive lightweight occurrence model. The inventive model does not maintain duplicate information and requires less memory to store the inventive model. Since the inventive occurrence model is smaller than the full occurrence model, complex circuit designs, e.g. microprocessors, can be represented by the inventive lightweight occurrence model. Thus, low level characteristics of the design, e.g., timing delays, can be examined.

Abstract: A computer-implemented graphics system defines an object-oriented framework for describing three-dimensional (3D) graphical objects, systems, and simulations. A 3D graphical image, a system, and a simulation are implemented as a directed multi-graph that includes a plurality of components defined by nodes connected by edges. A directed multi-graph engine in a graphics computer program processes the directed multi-graphs, wherein each node in the graph performs some specific function and the edges define relationships between the nodes. There are no restrictions on node types, and thus nodes may represent graphic objects (a visual representation), rules (rule-base behavior), attributes (data that does not affect the fundamental definition of the object), properties (data that affects the fundamental definition of the object), behaviors (methods), finite state machines (a sequence of actions and states), and any other user-defined component.

Abstract: The complexity of present ASIC designs has increased considerably with the integration of multiple asynchronous frequency clock domains. The verification of these hardware models before actual tape out has become more and more important. A system and method are described herein to perform asynchronous stress testing using a single cycle random simulation environment. The system and method both include three phases. First, the domain frequency values are manipulated and a greatest common factor (GCF) mathematical approach is used to calculate a common unit of time. Secondly, corresponding default simulation cycles per system clock for each domain are calculated using the common unit of time determined from the previous phase. Lastly, a stress test is performed by randomly selecting a specific range above and below the default simulation cycle value for each clock domain.

Abstract: A data collection system for transmitting data from user equipment to a user application server over a GSM network is provided. According to an aspect of the invention, a data terminal apparatus is configured to simulate a circuit switched call link to the user equipment, while providing a communications call link to the GSM network over a non-circuit switched call link. According to embodiments described herein, the non-circuit switched call link is achieved via packetizing serial data from the user equipment into short message service messages, or alternatively via general packet radio service messages. As a result of the methods and apparatuses of the present inventions, legacy serial communications equipment can be integrated into a data collection network and remotely monitored without the costs associated with deploying service personnel or more costly circuit switched type equipment and services.

Abstract: A method and system for simulating a circuit design that includes analog and/or digital circuitry uses a hybrid system of static analysis and dynamic simulation. Once the user's circuit is read in and partitioned into stages, the input vectors are applied. A hybrid vector is used to represent a number of possible signal states, for example, a logic 0 or logic 1, as well as a number of possible signal transitions, for example, a rising signal or a falling signal. The possible combinations of states are enumerated and the network in the stage is solved for all possible combinations. The results from the network solutions for the different combinations are recomposed into the hybrid notation, which is then applied to the next stage.

Abstract: A simulation system simulates an operation of a memory. This system includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a read/write operation of a memory model only by setting a memory address. A set of free bits, which is not used for the simulation of a memory operation, is used as a memory address for indicating the error generation. It is thus unnecessary to prepare a new description of a signal line exclusively for indication of error generation and it is possible to simulate a memory operation containing an error only by the normal descriptions of an address, data, and the like.

Abstract: According to the electrical modeling system and method provided by the present invention, the electronic structure to be modeled is segmented into an ordered sequence of segments, each segment is electrically analyzed individually, and the resulting data is collated, or integrated back again whereby the model output is preferably created in a format generally suitable for electrical models of integrated circuits. Examples of electronic structures which can be modeled by the system and method of the invention include leadframes, packages, complete devices, and electronic devices assembled on motherboards.

Abstract: Inductive effects in an integrated circuit device and/or system are modeled by partitioning the integrated circuit device and/or system into multiple windows or portions and determining a first localized inductance matrix for a first portion of the circuit and/or system and a second localized inductance matrix for a second portion of the circuit and/or system. The first and second localized inductance matrices are solved to obtain first and second localized susceptance vectors. The first and second localized susceptance vectors may be combined to form a susceptance matrix, which may be used directly in a susceptance-based simulator, or inverted to obtain a sparser inductance matrix that is representative of the inductive couplings in the entire integrated circuit device and/or system.

Abstract: Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

Abstract: A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.

Abstract: In a logic simulation method, one of an algorithm level simulation and a register transfer level simulation is executed. The algorithm level simulation corresponds to an algorithm level description and the register transfer level simulation corresponds to a register transfer level description. The simulation is switched from one of the algorithm level simulation and the register transfer level simulation into the other in response to a switching instruction using a relation between states of the algorithm level description and states of the register transfer level description. The algorithm level description is associated with arithmetic and logic algorithm and not associated with logic circuits. The register transfer level description is associated with logic circuits.

Abstract: A method and system unbind a rise/fall tuple of a VHDL generic variable and create rise time and fall time generics of each generic variable that are independent of each other. Then, according to a predetermined correlation policy, the method and system collect delay values in a VHDL standard delay file, sort the delay values, remove duplicate delay values, group the delay values into correlation sets, and output an analysis file. The correlation policy may include collecting all generic variables in a VHDL standard delay file, selecting each generic variable, and performing reductions on the set of delay values associated with each selected generic variable.

Abstract: A logic network is simulated, including partitioning logic operations into domains and ranking the operations. Some operations are dependent on source operations from other domains. Pairs of operations having common dependencies are then separated by at least as many operations as the total number of operations in the domains of the respective source operations. All operations are then merged into an order having a certain relation to the respective domain orderings, but omitting nop's inserted to achieve desired separation. Then pairs of operations having common dependency are again separated, this time making advantageous use of overlaps, so that nop's are reduced, to improve simulation time. Due to separations, after one value is computed for one instance of an operation depending on a source operation, a next value is computed for the source operation before computing the next instance of an operation depending on the source operation.

Abstract: An MWL signal encoding part encodes a signal occurring on a main word signal line, an SD signal encoding part encodes a signal occurring on a subdecode signal line, a WL calculating part calculates a WL value, based on an MWL signal encoded value and an SD signal encoded value; an input and output operation part allows one-word data in a memory cell selected by the WL value to be read and written via the bit signal line; and a read and write control part controls a read operation and a write operation of the input and output operation part, based on a signal level on the bit signal line.

Abstract: Method and apparatus for the synthesis of electronic circuits and, more particuarly, to the synthesis of analog circuitry and mixed digital and analog circuitry, and related to the reuse of circuit designer knowledge for the simulation of mixed analog and digital circuitry to determine data points and to curve fit the data points to determine a polynomial equation that closely approximates simulated circuit performance, and related to the parameterization of circuit features with respect to circuit performance.

Abstract: A method for efficiently simulating memory structures of a sequential circuit for design verification of the sequential circuit. The method is implemented by an computer system having a processor coupled to a memory via a bus, the memory storing computer readable code which when executed by the processor cause the computer system to perform the steps of the memory structure simulation method. The method includes accessing a netlist description of a sequential circuit, wherein the description is for realizing the sequential circuit in a physical form. Memory elements included within the description are identified. For these memory elements, inputs to the memory elements and outputs from the memory elements are identified. Using this information, the memory elements are grouped into at least one group of functionally related memory elements. Subsequently, the memory elements of the one or more groups are collectively addressed as a group.

Abstract: A digital system includes a plurality of hierarchically arranged design entity instantiations including a first entity instantiation containing second and third instantiations of the same design entity. Each of the instantiations contains a respective instance of a configurable entity having a plurality of possible configuration values that each corresponds to a different configuration of a functional portion of the digital system. A configuration specification for the digital system is received including a Dial containing a mapping between each of a plurality of possible Dial input values and a respective one of a plurality of configuration values. The configuration specification generically refers to the design entity. In response to receipt of the configuration specification, both instance of the configurable entity are automatically located.

Abstract: A system configuration database is constructed in volatile memory by first determining which types of integrated circuits are present in a hardware system and the number of each type. In response to a determination, a system configuration database is loaded into volatile memory that includes a respective chip hardware database for each type of integrated circuit in the hardware system. Each chip hardware database defines a Dial entity controlling which of a plurality of different possible latch values is placed in a hardware latch of the associated type of integrated circuit. The system configuration database includes at least a first chip hardware database for a first type of integrated circuit that contains per-instance information for each of the multiple instances of the first type of integrated circuit within the hardware system.

Abstract: A method of and system for generating tests and using the tests to identify VLSI simulation and circuit operation faults and errors and validate performance uses a genetic algorithm. Each generation of tests is further processed to eliminate redundant tests and make room for the insertion of new genetic material into the population in the form of random test vectors. The resulting family of tests generated using a simulation of the VLSI can then be ported to the circuit once prototyped in silicon and adapted to the new environment using, once again, the genetic algorithm to suitably evolve the test population.

Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.

Abstract: The present invention discloses a PS2 simulator installed at a PS2 interface of a computer so as to simulate signals from a keyboard and a mouse such that the computer using an earlier OS version is booted after one of the signals is detected. Therefore, a KVM switching device based on other interface specifications such as USB and IEEE 1394 can be used.

Abstract: A method and system for emulating the optical behavior of an optical communications generates wavelength modeled objects for each emulated optical signal and a variety of other modeled objects for the optical communications modules of the emulated system such as transmitter modeled objects, a combiner modeled object, an amplifier modeled object, a splitter modeled object, and receiver modeled objects. Each of the modeled objects includes certain optical attributes and a behavior modeling function particular to the module being emulated. The optical modules themselves are also represented as emulated processes. The modeled objects are propagated along a logical path from emulated process to emulated process. Upon receipt of a modeled object the emulated process executes the behavior modeling function and updates modeling objects affected by the execution.

Abstract: A system and a method for performing circuit simulation on a integrated circuit design that is represented by a hierarchical netlist. The system and method utilize, in one embodiment, an event driven simulator that divides or “cuts” along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into their Thevenin equivalents. Once a Thevenin equivalent is computed, matrix computations are used to compute the cut node voltages and sensitivity vectors may be used to then determine the internal node voltages. This is done for each event. In the event driven example, a group of leaf cells are identified that are touched by a given event. This group is then cut based on the hierarchical boundaries of the input netlist. The system maintains dynamic node voltages across the entire netlist and also maintains instance specific dynamic information for each cell.

Abstract: A method for designing high performance products incorporating signal processing and feedback control is disclosed. In one embodiment, a block diagram may be used for a design cycle, for design optimization, or for design estimation. The block diagram contains a set of differential equations or difference equations, and the solution of these sets of equations may be performed by commercially available software tools. In order to utilize the software tools without requiring access to source code or other descriptions of the internal structure of the tools, the system is decomposed using the technique of waveform relaxation. The decomposition using waveform relaxation operates directly to speed up the computations for the block diagram system. The remaining interprocessor communications may be held pending until the end of each iteration's calculations in each block, allowing the software tools to be executed on independent multiple processors.

Abstract: The present invention provides for a method and an apparatus for implementing a control simulation environment into a manufacturing environment. A process task is defined. A process simulation function is performed to produce simulation data corresponding to the process task. The simulation data is integrated with a process control environment for controlling a manufacturing process of a semiconductor device.

Abstract: The invention provides a method, program and system for designing an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to a jth input transistor, of the plurality of input transistors, is coupled to the (n−j)th output node, and wherein (n−j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The methodology determines relative sizes of each input transistor within a stage for a given number of stages, a total transconductance of the input transistors per stage, and a minimum relative attenuation of undesired modes.

Abstract: The present invention is a method and apparatus for implementing in embedded software the functionality of one or more external user interface circuits either in a surface mountable integrated circuit or in the main system CPU of a telecommunication unit.

Abstract: The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

Abstract: A focusing portion of a mounting process simulation system selects necessary data, and a result table forming portion forms a result table by using the data and stores the table in a result table storing portion. A condition setting portion forms a condition table based on process condition data input from an input device and stores the table in a condition table storing portion. A sample calculating portion calculates calculated result data by using the result table and the condition table. The condition table storing portion lists the calculated result data on the condition table, and outputs the data to the sample calculating portion as the calculated result data in the pre-step.

Abstract: A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.

Abstract: The present invention includes a system and method for generating a signal particularly useful in testing JMX monitors using a generator bean, such as a signal generating Java Mbean. A user can specify equations and/or parameters in order to determine the type of signal to be generated. The generator bean is then polled at a frequency at least twice the frequency of the generated signal using a monitor MBean of the JMX monitor. A testing value is returned for each polling of the generator bean.

Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.

Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.

Abstract: A method of designing an MOSFET of the present invention is concerned with design of a photomask which is used in a patterning process for forming an element isolation insulating film. An element forming region includes in top view a projecting portion (8a, 8b) along its perimeter. With respect to the structure in which the projecting portion (8a, 8b) is not provided, stress exerted on a semiconductor substrate (1) from an element isolation insulating film (2) varies. Provision of the projecting portion (8a, 8b) thus allows fine control of stress exerted on an area of the semiconductor substrate (1) holding a gate structure (3) thereover. As a result, the current driving capability of an MOSFET can be controlled at a desirable level.

Abstract: One embodiment of the present invention relates to a method for constructing a circuit for controlling an electromagnetic actuator. Another embodiment of the present invention relates to a method for designing a circuit for controlling an electromagnetic actuator.

Abstract: A method, system, and product are disclosed for determining an inductance of an entire integrated circuit package taken as a whole. A model is generated of the entire integrated circuit package which has a first port, a second port, and a third port. The first port of the model is coupled in parallel to an energy source and a resistor having a known resistance. The second port of the model is shorted. And, the third port of the model is opened. The package is simulated by exciting the first port utilizing the energy source and measuring a voltage at the first port in order to produce a waveform. A time constant is determined utilizing the waveform. The inductance of the entire integrated circuit package is then determined from the first port with respect to the second port using the known resistance and the time constant.

Abstract: A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. The method may involve the use of the S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. Such process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis may be performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the subcircuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

Abstract: A method for mapping moments in a reduced order system of approximation order q for use in simulating a circuit or system having n state variables at n nodes, the circuit or system having I inputs. The method includes calculating only q+I moments, where q is the approximation order and I is the number of inputs of the circuit or system being simulated, sorting the state variables at the n nodes, selecting q nodes of the n nodes, and calculating the dominate poles and zeros using a multi-point moment matching algorithm to simultaneously match q+I moments at the selected q nodes of the circuit or system. In one embodiment, the method includes using extra dummy inputs such that the total number of inputs equals I, such that K*I>q where K is a constant having a value in the range of about 4 to 8.

Abstract: A method is described for converting a data set for use with a digital model of a hardware cell into an expanded data set for use with an analog model of the hardware cell. The method including the steps of determining the signal required to drive one or more pins of said analog model by analyzing whether the signals used in said digital model are in a first category or a second category, said first category containing relatively simple signals and said second category containing relatively complex signals, and providing the signal required for the one or more pins in the analog model in dependence on said analysis.

Abstract: 42Method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). Behavioral models of memories of simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e.g., Verilog). Simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. Structural models are stored for subsequent access during pattern generation. In another embodiment for modeling random access memories (RAMs), the ATPG memory primitives include memory primitives, data bus primitives, address bus primitives, read-port primitives and macro output primitives. In another embodiment for modeling content addressable memories (CAMs), the ATPG memory primitives include memory primitives, compare port primitives and macro output primitives.

Abstract: A hardware design emulation system that includes one or more emulators and one or more associated run-time assist units (RTAUs). The emulator logic is a combination of user model logic, reflecting the hardware design, and non-user model logic. A handshaking controller produces a domain step signal and a model step signal. The domain step signal indicates that the emulator is entering a state for executing the next step of the logic with which it is programmed, be it user model logic or non-user model logic. The model step signal indicates that the emulator is entering a state for advancing the user model defined by the user model logic. This dual handshaking protocol enhances versatility by enabling a wide variety of RTAUs to be used, particularly in combination with one another.

Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: The system and method provides an NDT inspector with a realistic simulation of inspecting a test piece while injecting virtual flaws for display on an NDT instrument, while also presenting actual flaws to the inspector. A conventional NDT test probe and instrument are connected to the system at the probe leads interface. The system provides means for monitoring probe position and probe liftoff, means for storing virtual flaw signals and associated locations on a test piece, and means for providing a virtual flaw signal to the NDT instrumentation to simulate the response of the actual probe. The invention provides for nondestructive test method qualification and probability of detection determination, for establishing and maintaining nondestructive testing proficiency of inspectors, for periodically presenting flaw signals to inspectors during routine inspections, and for ensuring sufficient scan coverage for detection of material defects in a test piece.

Abstract: A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.

Abstract: A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

Abstract: The present invention is directed to a development methodology for integrated circuits. Central to this methodology is elimination of the dependence of software development on actual silicon for system integration and functional validation. In a first aspect of the present invention, a method for designing an integrated circuit and software for implementation by the integrated circuit includes receiving a specification for an integrated circuit design, the integrated circuit design specification including desired integrated circuit functionality. The integrated circuit design specification is modeled by defining a behavioral model of the integrated circuit design specification modeling the desired integrated circuit functionality. The integrated circuit design specification is simulated by utilizing the behavioral model as a virtual platform. The software developed on the virtual platform may be run on a hardware based prototyping platform.

Abstract: A method of checking correctness of scheduling of a circuit where a schedule for the circuit is obtained from a behavioral description. The method comprising extracting loop invariants to determine a sufficient set of acyclic threads when loops are present, performing symbolic simulation to extract the above loop invariants, and proving equivalence of the acyclic threads. Systems, computer systems and computer program products that incorporate the techniques of verification and correctness checking according to the present invention have also been disclosed.

Abstract: A method and system for power node current waveform modeling provides improved accuracy for logic gate and functional block power node current models in computer-based verification and design tools. An output voltage waveform is generated, with each point a linear function of a set of input values corresponding to times at which the output voltage reaches predetermined fractions of the supply voltage. A set of coefficients is used for each point, as each output voltage has a different linear dependency on the input values. The output voltage waveform model is differentiated and multiplied by an effective load capacitance to determine an output current waveform. The method and system retain compatibility with existing software by using input values already present in the digital simulation models (e.g., delay times) that yield a subset of output voltage points. The coefficients of the model are predetermined for a circuit from principle components analysis.